14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 35ff5ef992SAlex Deucher #include "mpc.h" 364562236bSHarry Wentland 374562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 384562236bSHarry Wentland 39c9614aebSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, 404562236bSHarry Wentland uint32_t controller_id); 414562236bSHarry Wentland 424562236bSHarry Wentland #include "grph_object_id.h" 434562236bSHarry Wentland #include "link_encoder.h" 444562236bSHarry Wentland #include "stream_encoder.h" 454562236bSHarry Wentland #include "clock_source.h" 464562236bSHarry Wentland #include "audio.h" 474562236bSHarry Wentland #include "hw_sequencer_types.h" 484562236bSHarry Wentland 494562236bSHarry Wentland 504562236bSHarry Wentland /************ link *****************/ 514562236bSHarry Wentland struct link_init_data { 524562236bSHarry Wentland const struct core_dc *dc; 534562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 544562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 554562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 564562236bSHarry Wentland TODO: remove it when DC is complete. */ 574562236bSHarry Wentland }; 584562236bSHarry Wentland 59d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 60d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 614562236bSHarry Wentland 624562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 634fa086b9SLeo (Sunpeng) Li const struct dc_stream *stream, 64d0778ebfSHarry Wentland struct dc_link *link, 654562236bSHarry Wentland const struct dc_crtc_timing *timing); 664562236bSHarry Wentland 67d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 684562236bSHarry Wentland 694562236bSHarry Wentland void core_link_enable_stream(struct pipe_ctx *pipe_ctx); 704562236bSHarry Wentland 714562236bSHarry Wentland void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 724562236bSHarry Wentland 7315e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 744562236bSHarry Wentland /********** DAL Core*********************/ 75e11b86adSDmytro Laktyushkin #include "display_clock.h" 764562236bSHarry Wentland #include "transform.h" 774562236bSHarry Wentland 784562236bSHarry Wentland struct resource_pool; 794562236bSHarry Wentland struct validate_context; 804562236bSHarry Wentland struct resource_context; 814562236bSHarry Wentland 824562236bSHarry Wentland struct resource_funcs { 834562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 844562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 854562236bSHarry Wentland const struct encoder_init_data *init); 864562236bSHarry Wentland enum dc_status (*validate_with_context)( 874562236bSHarry Wentland const struct core_dc *dc, 884562236bSHarry Wentland const struct dc_validation_set set[], 894562236bSHarry Wentland int set_count, 90430ef426SDmytro Laktyushkin struct validate_context *context, 91430ef426SDmytro Laktyushkin struct validate_context *old_context); 924562236bSHarry Wentland 934562236bSHarry Wentland enum dc_status (*validate_guaranteed)( 944562236bSHarry Wentland const struct core_dc *dc, 954fa086b9SLeo (Sunpeng) Li struct dc_stream *stream, 964562236bSHarry Wentland struct validate_context *context); 974562236bSHarry Wentland 9845209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 994562236bSHarry Wentland const struct core_dc *dc, 1004562236bSHarry Wentland struct validate_context *context); 1014562236bSHarry Wentland 1024562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 103745cc746SDmytro Laktyushkin struct validate_context *context, 104a2b8659dSTony Cheng const struct resource_pool *pool, 1054fa086b9SLeo (Sunpeng) Li struct dc_stream *stream); 106792671d7SAndrey Grodzovsky 107c9614aebSHarry Wentland enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); 1084562236bSHarry Wentland }; 1094562236bSHarry Wentland 1104562236bSHarry Wentland struct audio_support{ 1114562236bSHarry Wentland bool dp_audio; 1124562236bSHarry Wentland bool hdmi_audio_on_dongle; 1134562236bSHarry Wentland bool hdmi_audio_native; 1144562236bSHarry Wentland }; 1154562236bSHarry Wentland 116f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 117f0e3db90SHarry Wentland 1184562236bSHarry Wentland struct resource_pool { 1194562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 1204562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 1214562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 1224562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 1234562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 1244562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 125f0558542SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 126cc408d72SDmytro Laktyushkin struct mpc *mpc; 127f0558542SDmytro Laktyushkin #endif 1284562236bSHarry Wentland 1294562236bSHarry Wentland unsigned int pipe_count; 1304562236bSHarry Wentland unsigned int underlay_pipe_index; 1314562236bSHarry Wentland unsigned int stream_enc_count; 1325ac3d3c9SCharlene Liu unsigned int ref_clock_inKhz; 1334562236bSHarry Wentland 1344562236bSHarry Wentland /* 1354562236bSHarry Wentland * reserved clock source for DP 1364562236bSHarry Wentland */ 1374562236bSHarry Wentland struct clock_source *dp_clock_source; 1384562236bSHarry Wentland 1394562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 1404562236bSHarry Wentland unsigned int clk_src_count; 1414562236bSHarry Wentland 1424562236bSHarry Wentland struct audio *audios[MAX_PIPES]; 1434562236bSHarry Wentland unsigned int audio_count; 1444562236bSHarry Wentland struct audio_support audio_support; 1454562236bSHarry Wentland 1464562236bSHarry Wentland struct display_clock *display_clock; 1474562236bSHarry Wentland struct irq_service *irqs; 1484562236bSHarry Wentland 1495e7773a2SAnthony Koo struct abm *abm; 1505e7773a2SAnthony Koo struct dmcu *dmcu; 1515e7773a2SAnthony Koo 1524562236bSHarry Wentland const struct resource_funcs *funcs; 1534562236bSHarry Wentland const struct resource_caps *res_cap; 1544562236bSHarry Wentland }; 1554562236bSHarry Wentland 1564562236bSHarry Wentland struct pipe_ctx { 157c9614aebSHarry Wentland struct dc_plane_state *surface; 1584fa086b9SLeo (Sunpeng) Li struct dc_stream *stream; 1594562236bSHarry Wentland 1604562236bSHarry Wentland struct mem_input *mi; 1614562236bSHarry Wentland struct input_pixel_processor *ipp; 1624562236bSHarry Wentland struct transform *xfm; 1634562236bSHarry Wentland struct output_pixel_processor *opp; 1644562236bSHarry Wentland struct timing_generator *tg; 1654562236bSHarry Wentland 1664562236bSHarry Wentland struct scaler_data scl_data; 1674562236bSHarry Wentland 1684562236bSHarry Wentland struct stream_encoder *stream_enc; 1694562236bSHarry Wentland struct display_clock *dis_clk; 1704562236bSHarry Wentland struct clock_source *clock_source; 1714562236bSHarry Wentland 1724562236bSHarry Wentland struct audio *audio; 1734562236bSHarry Wentland 1744562236bSHarry Wentland struct pixel_clk_params pix_clk_params; 1754562236bSHarry Wentland struct pll_settings pll_settings; 1764562236bSHarry Wentland 1774562236bSHarry Wentland /*fmt*/ 1784562236bSHarry Wentland struct encoder_info_frame encoder_info_frame; 1794562236bSHarry Wentland 1804562236bSHarry Wentland uint8_t pipe_idx; 1814562236bSHarry Wentland 1824562236bSHarry Wentland struct pipe_ctx *top_pipe; 1834562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 184f0558542SDmytro Laktyushkin 185ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 186ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 187ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 188ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 189ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 190ff5ef992SAlex Deucher #endif 1914562236bSHarry Wentland }; 1924562236bSHarry Wentland 1934562236bSHarry Wentland struct resource_context { 1944562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 1954562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 1964562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 1974562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 1984562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 1994562236bSHarry Wentland }; 2004562236bSHarry Wentland 2019037d802SDmytro Laktyushkin struct dce_bw_output { 2029037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 2039037d802SDmytro Laktyushkin bool cpup_state_change_enable; 2049037d802SDmytro Laktyushkin bool stutter_mode_enable; 2059037d802SDmytro Laktyushkin bool nbp_state_change_enable; 2069037d802SDmytro Laktyushkin bool all_displays_in_sync; 2079037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 2089037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 2099037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 2109037d802SDmytro Laktyushkin int sclk_khz; 2119037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 2129037d802SDmytro Laktyushkin int yclk_khz; 2139037d802SDmytro Laktyushkin int dispclk_khz; 2149037d802SDmytro Laktyushkin int blackout_recovery_time_us; 2159037d802SDmytro Laktyushkin }; 2169037d802SDmytro Laktyushkin 2179037d802SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 2189037d802SDmytro Laktyushkin struct dcn_bw_clocks { 2199037d802SDmytro Laktyushkin int dispclk_khz; 2209037d802SDmytro Laktyushkin bool dppclk_div; 2219037d802SDmytro Laktyushkin int dcfclk_khz; 2229037d802SDmytro Laktyushkin int dcfclk_deep_sleep_khz; 2239037d802SDmytro Laktyushkin int fclk_khz; 2249037d802SDmytro Laktyushkin int dram_ccm_us; 2259037d802SDmytro Laktyushkin int min_active_dram_ccm_us; 2269037d802SDmytro Laktyushkin }; 2279037d802SDmytro Laktyushkin 2289037d802SDmytro Laktyushkin struct dcn_bw_output { 2299037d802SDmytro Laktyushkin struct dcn_bw_clocks cur_clk; 2309037d802SDmytro Laktyushkin struct dcn_bw_clocks calc_clk; 2319037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 2329037d802SDmytro Laktyushkin }; 2339037d802SDmytro Laktyushkin #endif 2349037d802SDmytro Laktyushkin 2359037d802SDmytro Laktyushkin union bw_context { 2369037d802SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 2379037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 2389037d802SDmytro Laktyushkin #endif 2399037d802SDmytro Laktyushkin struct dce_bw_output dce; 2409037d802SDmytro Laktyushkin }; 2419037d802SDmytro Laktyushkin 2424562236bSHarry Wentland struct validate_context { 2434fa086b9SLeo (Sunpeng) Li struct dc_stream *streams[MAX_PIPES]; 244ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 245ab2541b6SAric Cyr uint8_t stream_count; 2464562236bSHarry Wentland 2474562236bSHarry Wentland struct resource_context res_ctx; 2484562236bSHarry Wentland 2494562236bSHarry Wentland /* The output from BW and WM calculations. */ 2509037d802SDmytro Laktyushkin union bw_context bw; 2519037d802SDmytro Laktyushkin 2525ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 2534562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 254ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 255ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 256ff5ef992SAlex Deucher #endif 2578a76708eSAndrey Grodzovsky 2588a76708eSAndrey Grodzovsky int ref_count; 2594562236bSHarry Wentland }; 2604562236bSHarry Wentland 2614562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 262