14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36dc37a9a0SLeo (Sunpeng) Li #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 37ff5ef992SAlex Deucher #include "mpc.h" 38391e20d8SDuke Du #endif 39345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 40345429a6SHarry Wentland #include "dwb.h" 41345429a6SHarry Wentland #include "mcif_wb.h" 42345429a6SHarry Wentland #endif 434562236bSHarry Wentland 444562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 454562236bSHarry Wentland 463be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 474562236bSHarry Wentland uint32_t controller_id); 484562236bSHarry Wentland 494562236bSHarry Wentland #include "grph_object_id.h" 504562236bSHarry Wentland #include "link_encoder.h" 514562236bSHarry Wentland #include "stream_encoder.h" 524562236bSHarry Wentland #include "clock_source.h" 534562236bSHarry Wentland #include "audio.h" 54a185048cSTony Cheng #include "dm_pp_smu.h" 554562236bSHarry Wentland 564562236bSHarry Wentland 574562236bSHarry Wentland /************ link *****************/ 584562236bSHarry Wentland struct link_init_data { 59fb3466a4SBhawanpreet Lakha const struct dc *dc; 604562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 614562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 624562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 634562236bSHarry Wentland TODO: remove it when DC is complete. */ 644562236bSHarry Wentland }; 654562236bSHarry Wentland 66d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 67d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 684562236bSHarry Wentland 694562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 700971c40eSHarry Wentland const struct dc_stream_state *stream, 71d0778ebfSHarry Wentland struct dc_link *link, 724562236bSHarry Wentland const struct dc_crtc_timing *timing); 734562236bSHarry Wentland 74d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 754562236bSHarry Wentland 76ab8db3e1SAndrey Grodzovsky void core_link_enable_stream( 77ab8db3e1SAndrey Grodzovsky struct dc_state *state, 78ab8db3e1SAndrey Grodzovsky struct pipe_ctx *pipe_ctx); 794562236bSHarry Wentland 8057430404SSu Sung Chung void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 814562236bSHarry Wentland 8215e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 834562236bSHarry Wentland /********** DAL Core*********************/ 844562236bSHarry Wentland #include "transform.h" 85d94585a0SYue Hin Lau #include "dpp.h" 864562236bSHarry Wentland 874562236bSHarry Wentland struct resource_pool; 88608ac7bbSJerry Zuo struct dc_state; 894562236bSHarry Wentland struct resource_context; 904562236bSHarry Wentland 914562236bSHarry Wentland struct resource_funcs { 924562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 9366b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 944562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 954562236bSHarry Wentland const struct encoder_init_data *init); 9645209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 97fb3466a4SBhawanpreet Lakha struct dc *dc, 98afcd526bSJoshua Aberback struct dc_state *context, 99afcd526bSJoshua Aberback bool fast_validate); 1004562236bSHarry Wentland 101ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 102ed07237cSIlya Bakoulin struct dc *dc, 103ed07237cSIlya Bakoulin struct resource_context *res_ctx, 104ed07237cSIlya Bakoulin display_e2e_pipe_params_st *pipes); 105ed07237cSIlya Bakoulin 1061dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1071dc90497SAndrey Grodzovsky struct dc *dc, 108608ac7bbSJerry Zuo struct dc_state *context); 1091dc90497SAndrey Grodzovsky 1104562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 111608ac7bbSJerry Zuo struct dc_state *context, 112a2b8659dSTony Cheng const struct resource_pool *pool, 1130971c40eSHarry Wentland struct dc_stream_state *stream); 1141dc90497SAndrey Grodzovsky 1158e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1161dc90497SAndrey Grodzovsky 1171dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1181dc90497SAndrey Grodzovsky struct dc *dc, 119608ac7bbSJerry Zuo struct dc_state *new_ctx, 1201dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 121e56ae556SNikola Cornij 122e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 123e56ae556SNikola Cornij struct dc *dc, 124e56ae556SNikola Cornij struct dc_state *new_ctx, 125e56ae556SNikola Cornij struct dc_stream_state *stream); 12674eac5f3SSu Sung Chung enum dc_status (*get_default_swizzle_mode)( 12774eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 12874eac5f3SSu Sung Chung 12978cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 13078cc70b1SWesley Chalmers struct resource_context *res_ctx, 13178cc70b1SWesley Chalmers const struct resource_pool *pool, 13278cc70b1SWesley Chalmers struct dc_stream_state *stream); 133345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 134345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 135345429a6SHarry Wentland struct dc *dc, 136345429a6SHarry Wentland struct resource_context *res_ctx, 137345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 13878cc70b1SWesley Chalmers 139345429a6SHarry Wentland void (*set_mcif_arb_params)( 140345429a6SHarry Wentland struct dc *dc, 141345429a6SHarry Wentland struct dc_state *context, 142345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 143345429a6SHarry Wentland int pipe_cnt); 144345429a6SHarry Wentland #endif 145c9ae6e16SNikola Cornij 1464562236bSHarry Wentland }; 1474562236bSHarry Wentland 1484562236bSHarry Wentland struct audio_support{ 1494562236bSHarry Wentland bool dp_audio; 1504562236bSHarry Wentland bool hdmi_audio_on_dongle; 1514562236bSHarry Wentland bool hdmi_audio_native; 1524562236bSHarry Wentland }; 1534562236bSHarry Wentland 154f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 155f0e3db90SHarry Wentland 1564562236bSHarry Wentland struct resource_pool { 1574562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 1588feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 1594562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 1604562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 161d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 1624562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 1634562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 1644562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 165c9ef081dSYue Hin Lau struct hubbub *hubbub; 166cc408d72SDmytro Laktyushkin struct mpc *mpc; 1670f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 1681877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 169c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 170c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 171c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 1724562236bSHarry Wentland 173345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 174345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 175345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 176345429a6SHarry Wentland struct { 177345429a6SHarry Wentland unsigned int gsl_0:1; 178345429a6SHarry Wentland unsigned int gsl_1:1; 179345429a6SHarry Wentland unsigned int gsl_2:1; 180345429a6SHarry Wentland } gsl_groups; 181345429a6SHarry Wentland #endif 182345429a6SHarry Wentland 18397bda032SHarry Wentland #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 18497bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 18597bda032SHarry Wentland #endif 186345429a6SHarry Wentland 1874562236bSHarry Wentland unsigned int pipe_count; 1884562236bSHarry Wentland unsigned int underlay_pipe_index; 1894562236bSHarry Wentland unsigned int stream_enc_count; 190929c3aaaSEric Bernstein 19133d7598dSJun Lei struct { 19233d7598dSJun Lei unsigned int xtalin_clock_inKhz; 19333d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 19433d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 19533d7598dSJun Lei } ref_clocks; 1963be1406aSYongqiang Sun unsigned int timing_generator_count; 197345429a6SHarry Wentland unsigned int mpcc_count; 1984562236bSHarry Wentland 199345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 200345429a6SHarry Wentland unsigned int writeback_pipe_count; 201345429a6SHarry Wentland #endif 2024562236bSHarry Wentland /* 2034562236bSHarry Wentland * reserved clock source for DP 2044562236bSHarry Wentland */ 2054562236bSHarry Wentland struct clock_source *dp_clock_source; 2064562236bSHarry Wentland 2074562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 2084562236bSHarry Wentland unsigned int clk_src_count; 2094562236bSHarry Wentland 2107352193aSTai Man struct audio *audios[MAX_AUDIOS]; 2114562236bSHarry Wentland unsigned int audio_count; 2124562236bSHarry Wentland struct audio_support audio_support; 2134562236bSHarry Wentland 214ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 2154562236bSHarry Wentland struct irq_service *irqs; 2164562236bSHarry Wentland 2175e7773a2SAnthony Koo struct abm *abm; 2185e7773a2SAnthony Koo struct dmcu *dmcu; 2195e7773a2SAnthony Koo 2204562236bSHarry Wentland const struct resource_funcs *funcs; 2214562236bSHarry Wentland const struct resource_caps *res_cap; 2224562236bSHarry Wentland }; 2234562236bSHarry Wentland 224f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 22569338c1fSDmytro Laktyushkin int dppclk_khz; 226f553e681SDmytro Laktyushkin }; 227f553e681SDmytro Laktyushkin 22879b06f0cSHarry Wentland struct stream_resource { 229a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 23097bda032SHarry Wentland #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 23197bda032SHarry Wentland struct display_stream_compressor *dsc; 23297bda032SHarry Wentland #endif 2336b670fa9SHarry Wentland struct timing_generator *tg; 2348e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 235afaacef4SHarry Wentland struct audio *audio; 23610688217SHarry Wentland 23710688217SHarry Wentland struct pixel_clk_params pix_clk_params; 23896c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 2399aef1a31SSivapiriyanKumarasamy 2409aef1a31SSivapiriyanKumarasamy struct abm *abm; 241345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 242345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 243345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 244345429a6SHarry Wentland */ 245345429a6SHarry Wentland uint8_t gsl_group; 246345429a6SHarry Wentland #endif 24779b06f0cSHarry Wentland }; 24879b06f0cSHarry Wentland 24979b06f0cSHarry Wentland struct plane_resource { 2506702a9acSHarry Wentland struct scaler_data scl_data; 2518feabd03SYue Hin Lau struct hubp *hubp; 25286a66c4eSHarry Wentland struct mem_input *mi; 25386a66c4eSHarry Wentland struct input_pixel_processor *ipp; 25486a66c4eSHarry Wentland struct transform *xfm; 255d94585a0SYue Hin Lau struct dpp *dpp; 256e07f541fSYongqiang Sun uint8_t mpcc_inst; 257f553e681SDmytro Laktyushkin 258f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 25979b06f0cSHarry Wentland }; 26079b06f0cSHarry Wentland 26124c18794SDmytro Laktyushkin union pipe_update_flags { 26224c18794SDmytro Laktyushkin struct { 26324c18794SDmytro Laktyushkin uint32_t enable : 1; 26424c18794SDmytro Laktyushkin uint32_t disable : 1; 26524c18794SDmytro Laktyushkin uint32_t odm : 1; 26624c18794SDmytro Laktyushkin uint32_t global_sync : 1; 26724c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 26824c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 26924c18794SDmytro Laktyushkin uint32_t mpcc : 1; 27024c18794SDmytro Laktyushkin uint32_t dppclk : 1; 27124c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 27224c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 27324c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 27424c18794SDmytro Laktyushkin uint32_t scaler : 1; 27524c18794SDmytro Laktyushkin uint32_t viewport : 1; 27624c18794SDmytro Laktyushkin } bits; 27724c18794SDmytro Laktyushkin uint32_t raw; 27824c18794SDmytro Laktyushkin }; 27924c18794SDmytro Laktyushkin 2804562236bSHarry Wentland struct pipe_ctx { 2813be5262eSHarry Wentland struct dc_plane_state *plane_state; 2820971c40eSHarry Wentland struct dc_stream_state *stream; 2834562236bSHarry Wentland 28479b06f0cSHarry Wentland struct plane_resource plane_res; 28579b06f0cSHarry Wentland struct stream_resource stream_res; 28679b06f0cSHarry Wentland 2874562236bSHarry Wentland struct clock_source *clock_source; 2884562236bSHarry Wentland 2894562236bSHarry Wentland struct pll_settings pll_settings; 2904562236bSHarry Wentland 2914562236bSHarry Wentland uint8_t pipe_idx; 2924562236bSHarry Wentland 2934562236bSHarry Wentland struct pipe_ctx *top_pipe; 2944562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 295b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 296b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 297f0558542SDmytro Laktyushkin 298dc37a9a0SLeo (Sunpeng) Li #ifdef CONFIG_DRM_AMD_DC_DCN1_0 299ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 300ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 301ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 302ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 303ff5ef992SAlex Deucher #endif 30424c18794SDmytro Laktyushkin union pipe_update_flags update_flags; 305345429a6SHarry Wentland #ifdef CONFIG_DRM_AMD_DC_DCN2_0 306345429a6SHarry Wentland struct dwbc *dwbc; 307345429a6SHarry Wentland struct mcif_wb *mcif_wb; 308345429a6SHarry Wentland #endif 3094562236bSHarry Wentland }; 3104562236bSHarry Wentland 3114562236bSHarry Wentland struct resource_context { 3124562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 3134562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 3144562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 3154562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 3164562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 317345429a6SHarry Wentland #ifdef CONFIG_DRM_AMD_DC_DCN2_0 318345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 319345429a6SHarry Wentland #endif 3204562236bSHarry Wentland }; 3214562236bSHarry Wentland 3229037d802SDmytro Laktyushkin struct dce_bw_output { 3239037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 3249037d802SDmytro Laktyushkin bool cpup_state_change_enable; 3259037d802SDmytro Laktyushkin bool stutter_mode_enable; 3269037d802SDmytro Laktyushkin bool nbp_state_change_enable; 3279037d802SDmytro Laktyushkin bool all_displays_in_sync; 3289037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 3299037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 330b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 3319037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 3329037d802SDmytro Laktyushkin int sclk_khz; 3339037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 3349037d802SDmytro Laktyushkin int yclk_khz; 3359037d802SDmytro Laktyushkin int dispclk_khz; 3369037d802SDmytro Laktyushkin int blackout_recovery_time_us; 3379037d802SDmytro Laktyushkin }; 3389037d802SDmytro Laktyushkin 339345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 340345429a6SHarry Wentland struct dcn_bw_writeback { 341345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 342345429a6SHarry Wentland }; 343345429a6SHarry Wentland #endif 344345429a6SHarry Wentland 3459037d802SDmytro Laktyushkin struct dcn_bw_output { 346d578839cSDmytro Laktyushkin struct dc_clocks clk; 3479037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 348345429a6SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 349345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 350345429a6SHarry Wentland #endif 3519037d802SDmytro Laktyushkin }; 3529037d802SDmytro Laktyushkin 353813d20dcSAidan Wood union bw_output { 3549037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 3559037d802SDmytro Laktyushkin struct dce_bw_output dce; 3569037d802SDmytro Laktyushkin }; 3579037d802SDmytro Laktyushkin 358813d20dcSAidan Wood struct bw_context { 359813d20dcSAidan Wood union bw_output bw; 360813d20dcSAidan Wood struct display_mode_lib dml; 361813d20dcSAidan Wood }; 3622119aa17SDavid Francis /** 3632119aa17SDavid Francis * struct dc_state - The full description of a state requested by a user 3642119aa17SDavid Francis * 3652119aa17SDavid Francis * @streams: Stream properties 3662119aa17SDavid Francis * @stream_status: The planes on a given stream 3672119aa17SDavid Francis * @res_ctx: Persistent state of resources 368813d20dcSAidan Wood * @bw_ctx: The output from bandwidth and watermark calculations and the DML 3692119aa17SDavid Francis * @pp_display_cfg: PowerPlay clocks and settings 3702119aa17SDavid Francis * @dcn_bw_vars: non-stack memory to support bandwidth calculations 3712119aa17SDavid Francis * 3722119aa17SDavid Francis */ 373608ac7bbSJerry Zuo struct dc_state { 3740971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 375ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 376ab2541b6SAric Cyr uint8_t stream_count; 3774562236bSHarry Wentland 3784562236bSHarry Wentland struct resource_context res_ctx; 3794562236bSHarry Wentland 380813d20dcSAidan Wood struct bw_context bw_ctx; 3819037d802SDmytro Laktyushkin 3825ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 3834562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 384dc37a9a0SLeo (Sunpeng) Li #ifdef CONFIG_DRM_AMD_DC_DCN1_0 385ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 386ff5ef992SAlex Deucher #endif 3878a76708eSAndrey Grodzovsky 3880de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 389ab8db3e1SAndrey Grodzovsky 390e85c2d63SJun Lei struct { 391e85c2d63SJun Lei bool full_update_needed : 1; 392e85c2d63SJun Lei } commit_hints; 393e85c2d63SJun Lei 3948ee5702aSDave Airlie struct kref refcount; 3954562236bSHarry Wentland }; 3964562236bSHarry Wentland 3974562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 398