14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 37ff5ef992SAlex Deucher #include "mpc.h" 38391e20d8SDuke Du #endif 39345429a6SHarry Wentland #include "dwb.h" 40345429a6SHarry Wentland #include "mcif_wb.h" 41d4caa72eSAnthony Koo #include "panel_cntl.h" 424562236bSHarry Wentland 434562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 444562236bSHarry Wentland 453be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 464562236bSHarry Wentland uint32_t controller_id); 474562236bSHarry Wentland 484562236bSHarry Wentland #include "grph_object_id.h" 494562236bSHarry Wentland #include "link_encoder.h" 504562236bSHarry Wentland #include "stream_encoder.h" 514562236bSHarry Wentland #include "clock_source.h" 524562236bSHarry Wentland #include "audio.h" 53a185048cSTony Cheng #include "dm_pp_smu.h" 54d462fcf5SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_HDCP 55d462fcf5SBhawanpreet Lakha #include "dm_cp_psp.h" 56d462fcf5SBhawanpreet Lakha #endif 574562236bSHarry Wentland 584562236bSHarry Wentland /************ link *****************/ 594562236bSHarry Wentland struct link_init_data { 60fb3466a4SBhawanpreet Lakha const struct dc *dc; 614562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 624562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 634562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 644562236bSHarry Wentland TODO: remove it when DC is complete. */ 659fa0fb77SMeenakshikumar Somasundaram bool is_dpia_link; 664562236bSHarry Wentland }; 674562236bSHarry Wentland 68d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 69d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 704562236bSHarry Wentland 714562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 720971c40eSHarry Wentland const struct dc_stream_state *stream, 73d0778ebfSHarry Wentland struct dc_link *link, 744562236bSHarry Wentland const struct dc_crtc_timing *timing); 754562236bSHarry Wentland 76d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 774562236bSHarry Wentland 78ab8db3e1SAndrey Grodzovsky void core_link_enable_stream( 79ab8db3e1SAndrey Grodzovsky struct dc_state *state, 80ab8db3e1SAndrey Grodzovsky struct pipe_ctx *pipe_ctx); 814562236bSHarry Wentland 8257430404SSu Sung Chung void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 834562236bSHarry Wentland 8415e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 854562236bSHarry Wentland /********** DAL Core*********************/ 864562236bSHarry Wentland #include "transform.h" 87d94585a0SYue Hin Lau #include "dpp.h" 884562236bSHarry Wentland 894562236bSHarry Wentland struct resource_pool; 90608ac7bbSJerry Zuo struct dc_state; 914562236bSHarry Wentland struct resource_context; 92aa919167SBhawanpreet Lakha struct clk_bw_params; 934562236bSHarry Wentland 944562236bSHarry Wentland struct resource_funcs { 954562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 9666b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 97d4caa72eSAnthony Koo struct panel_cntl*(*panel_cntl_create)( 98d4caa72eSAnthony Koo const struct panel_cntl_init_data *panel_cntl_init_data); 994562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 1004562236bSHarry Wentland const struct encoder_init_data *init); 101e1f4328fSJimmy Kizito /* Create a minimal link encoder object with no dc_link object 102e1f4328fSJimmy Kizito * associated with it. */ 103e1f4328fSJimmy Kizito struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 104e1f4328fSJimmy Kizito 10545209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 106fb3466a4SBhawanpreet Lakha struct dc *dc, 107afcd526bSJoshua Aberback struct dc_state *context, 108afcd526bSJoshua Aberback bool fast_validate); 1098e02c26aSJoshua Aberback void (*calculate_wm_and_dlg)( 110b3ff538cSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 111b3ff538cSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 112b3ff538cSDmytro Laktyushkin int pipe_cnt, 113b3ff538cSDmytro Laktyushkin int vlevel); 114443dfba0SDmytro Laktyushkin void (*update_soc_for_wm_a)( 115443dfba0SDmytro Laktyushkin struct dc *dc, struct dc_state *context); 116ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 117ed07237cSIlya Bakoulin struct dc *dc, 1182f488884SAlvin Lee struct dc_state *context, 119fa896813SIsabel Zhang display_e2e_pipe_params_st *pipes, 120fa896813SIsabel Zhang bool fast_validate); 121ed07237cSIlya Bakoulin 122f42ef862SJimmy Kizito /* 123f42ef862SJimmy Kizito * Algorithm for assigning available link encoders to links. 124f42ef862SJimmy Kizito * 125f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 126f42ef862SJimmy Kizito * struct resource_context. 127f42ef862SJimmy Kizito */ 128f42ef862SJimmy Kizito void (*link_encs_assign)( 129f42ef862SJimmy Kizito struct dc *dc, 130f42ef862SJimmy Kizito struct dc_state *state, 131f42ef862SJimmy Kizito struct dc_stream_state *streams[], 132f42ef862SJimmy Kizito uint8_t stream_count); 133f42ef862SJimmy Kizito /* 134f42ef862SJimmy Kizito * Unassign a link encoder from a stream. 135f42ef862SJimmy Kizito * 136f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 137f42ef862SJimmy Kizito * struct resource_context. 138f42ef862SJimmy Kizito */ 139f42ef862SJimmy Kizito void (*link_enc_unassign)( 140f42ef862SJimmy Kizito struct dc_state *state, 141f42ef862SJimmy Kizito struct dc_stream_state *stream); 142f42ef862SJimmy Kizito 1431dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1441dc90497SAndrey Grodzovsky struct dc *dc, 145608ac7bbSJerry Zuo struct dc_state *context); 1461dc90497SAndrey Grodzovsky 1474562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 148608ac7bbSJerry Zuo struct dc_state *context, 149a2b8659dSTony Cheng const struct resource_pool *pool, 1500971c40eSHarry Wentland struct dc_stream_state *stream); 1511dc90497SAndrey Grodzovsky 1528e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1531dc90497SAndrey Grodzovsky 1541dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1551dc90497SAndrey Grodzovsky struct dc *dc, 156608ac7bbSJerry Zuo struct dc_state *new_ctx, 1571dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 158e56ae556SNikola Cornij 159e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 160e56ae556SNikola Cornij struct dc *dc, 161e56ae556SNikola Cornij struct dc_state *new_ctx, 162e56ae556SNikola Cornij struct dc_stream_state *stream); 1638d8c82b6SJoseph Gravenor enum dc_status (*patch_unknown_plane_state)( 16474eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 16574eac5f3SSu Sung Chung 16678cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 16778cc70b1SWesley Chalmers struct resource_context *res_ctx, 16878cc70b1SWesley Chalmers const struct resource_pool *pool, 16978cc70b1SWesley Chalmers struct dc_stream_state *stream); 170345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 171345429a6SHarry Wentland struct dc *dc, 172345429a6SHarry Wentland struct resource_context *res_ctx, 173345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 17478cc70b1SWesley Chalmers 175345429a6SHarry Wentland void (*set_mcif_arb_params)( 176345429a6SHarry Wentland struct dc *dc, 177345429a6SHarry Wentland struct dc_state *context, 178345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 179345429a6SHarry Wentland int pipe_cnt); 1801b2c7b2cSBhawanpreet Lakha void (*update_bw_bounding_box)( 1811b2c7b2cSBhawanpreet Lakha struct dc *dc, 1821b2c7b2cSBhawanpreet Lakha struct clk_bw_params *bw_params); 18320f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 1845dba4991SBhawanpreet Lakha bool (*acquire_post_bldn_3dlut)( 1855dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1865dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1875dba4991SBhawanpreet Lakha int mpcc_id, 1885dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1895dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1905dba4991SBhawanpreet Lakha 1915dba4991SBhawanpreet Lakha bool (*release_post_bldn_3dlut)( 1925dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1935dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1945dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1955dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1965dba4991SBhawanpreet Lakha #endif 197b4f71c8cSAurabindo Pillai enum dc_status (*add_dsc_to_stream_resource)( 198b4f71c8cSAurabindo Pillai struct dc *dc, struct dc_state *state, 199b4f71c8cSAurabindo Pillai struct dc_stream_state *stream); 2004562236bSHarry Wentland }; 2014562236bSHarry Wentland 2024562236bSHarry Wentland struct audio_support{ 2034562236bSHarry Wentland bool dp_audio; 2044562236bSHarry Wentland bool hdmi_audio_on_dongle; 2054562236bSHarry Wentland bool hdmi_audio_native; 2064562236bSHarry Wentland }; 2074562236bSHarry Wentland 208f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 209f0e3db90SHarry Wentland 2104562236bSHarry Wentland struct resource_pool { 2114562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 2128feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 2134562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 2144562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 215d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 2164562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 2174562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 2184562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 219c9ef081dSYue Hin Lau struct hubbub *hubbub; 220cc408d72SDmytro Laktyushkin struct mpc *mpc; 2210f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 2221877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 223c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 224c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 225c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 2264562236bSHarry Wentland 227345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 228345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 229345429a6SHarry Wentland struct { 230345429a6SHarry Wentland unsigned int gsl_0:1; 231345429a6SHarry Wentland unsigned int gsl_1:1; 232345429a6SHarry Wentland unsigned int gsl_2:1; 233345429a6SHarry Wentland } gsl_groups; 234345429a6SHarry Wentland 23597bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 236345429a6SHarry Wentland 2374562236bSHarry Wentland unsigned int pipe_count; 2384562236bSHarry Wentland unsigned int underlay_pipe_index; 2394562236bSHarry Wentland unsigned int stream_enc_count; 240929c3aaaSEric Bernstein 241e1f4328fSJimmy Kizito /* An array for accessing the link encoder objects that have been created. 242e1f4328fSJimmy Kizito * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 243e1f4328fSJimmy Kizito */ 244e1f4328fSJimmy Kizito struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 245e1f4328fSJimmy Kizito /* Number of DIG link encoder objects created - i.e. number of valid 246e1f4328fSJimmy Kizito * entries in link_encoders array. 247e1f4328fSJimmy Kizito */ 248e1f4328fSJimmy Kizito unsigned int dig_link_enc_count; 249eabf2019SJimmy Kizito /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 250eabf2019SJimmy Kizito unsigned int usb4_dpia_count; 251e1f4328fSJimmy Kizito 25220f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 25383228ebbSFangzhi Zuo unsigned int hpo_dp_stream_enc_count; 25483228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 2553bc8d921SFangzhi Zuo unsigned int hpo_dp_link_enc_count; 2563bc8d921SFangzhi Zuo struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 25783228ebbSFangzhi Zuo #endif 25883228ebbSFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 2595dba4991SBhawanpreet Lakha struct dc_3dlut *mpc_lut[MAX_PIPES]; 2605dba4991SBhawanpreet Lakha struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 2615dba4991SBhawanpreet Lakha #endif 26233d7598dSJun Lei struct { 26333d7598dSJun Lei unsigned int xtalin_clock_inKhz; 26433d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 26533d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 26633d7598dSJun Lei } ref_clocks; 2673be1406aSYongqiang Sun unsigned int timing_generator_count; 268345429a6SHarry Wentland unsigned int mpcc_count; 2694562236bSHarry Wentland 270345429a6SHarry Wentland unsigned int writeback_pipe_count; 2714562236bSHarry Wentland /* 2724562236bSHarry Wentland * reserved clock source for DP 2734562236bSHarry Wentland */ 2744562236bSHarry Wentland struct clock_source *dp_clock_source; 2754562236bSHarry Wentland 2764562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 2774562236bSHarry Wentland unsigned int clk_src_count; 2784562236bSHarry Wentland 2797352193aSTai Man struct audio *audios[MAX_AUDIOS]; 2804562236bSHarry Wentland unsigned int audio_count; 2814562236bSHarry Wentland struct audio_support audio_support; 2824562236bSHarry Wentland 283ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 2844562236bSHarry Wentland struct irq_service *irqs; 2854562236bSHarry Wentland 2865e7773a2SAnthony Koo struct abm *abm; 2875e7773a2SAnthony Koo struct dmcu *dmcu; 2884c1a1335SWyatt Wood struct dmub_psr *psr; 2895e7773a2SAnthony Koo 29020f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 291d99f1387SBhawanpreet Lakha struct abm *multiple_abms[MAX_PIPES]; 292d99f1387SBhawanpreet Lakha #endif 293d99f1387SBhawanpreet Lakha 2944562236bSHarry Wentland const struct resource_funcs *funcs; 2954562236bSHarry Wentland const struct resource_caps *res_cap; 296d9a07577SJun Lei 297d9a07577SJun Lei struct ddc_service *oem_device; 2984562236bSHarry Wentland }; 2994562236bSHarry Wentland 300f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 30169338c1fSDmytro Laktyushkin int dppclk_khz; 302799c5b9cSWesley Chalmers 303f553e681SDmytro Laktyushkin }; 304f553e681SDmytro Laktyushkin 30579b06f0cSHarry Wentland struct stream_resource { 306a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 30797bda032SHarry Wentland struct display_stream_compressor *dsc; 3086b670fa9SHarry Wentland struct timing_generator *tg; 3098e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 31083228ebbSFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 31183228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 31283228ebbSFangzhi Zuo #endif 313afaacef4SHarry Wentland struct audio *audio; 31410688217SHarry Wentland 31510688217SHarry Wentland struct pixel_clk_params pix_clk_params; 31696c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 3179aef1a31SSivapiriyanKumarasamy 3189aef1a31SSivapiriyanKumarasamy struct abm *abm; 319345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 320345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 321345429a6SHarry Wentland */ 322345429a6SHarry Wentland uint8_t gsl_group; 32379b06f0cSHarry Wentland }; 32479b06f0cSHarry Wentland 32579b06f0cSHarry Wentland struct plane_resource { 3266702a9acSHarry Wentland struct scaler_data scl_data; 3278feabd03SYue Hin Lau struct hubp *hubp; 32886a66c4eSHarry Wentland struct mem_input *mi; 32986a66c4eSHarry Wentland struct input_pixel_processor *ipp; 33086a66c4eSHarry Wentland struct transform *xfm; 331d94585a0SYue Hin Lau struct dpp *dpp; 332e07f541fSYongqiang Sun uint8_t mpcc_inst; 333f553e681SDmytro Laktyushkin 334f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 33579b06f0cSHarry Wentland }; 33679b06f0cSHarry Wentland 337*4c3adc0bSWenjing Liu #if defined(CONFIG_DRM_AMD_DC_DCN) 338*4c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 339*4c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 340*4c3adc0bSWenjing Liu #endif 341*4c3adc0bSWenjing Liu 342ef30f441SWenjing Liu /* all mappable hardware resources used to enable a link */ 343ef30f441SWenjing Liu struct link_resource { 344f3fac948SWenjing Liu #if defined(CONFIG_DRM_AMD_DC_DCN) 345f3fac948SWenjing Liu struct hpo_dp_link_encoder *hpo_dp_link_enc; 346f3fac948SWenjing Liu #else 347ef30f441SWenjing Liu void *dummy; 348f3fac948SWenjing Liu #endif 349ef30f441SWenjing Liu }; 350ef30f441SWenjing Liu 35124c18794SDmytro Laktyushkin union pipe_update_flags { 35224c18794SDmytro Laktyushkin struct { 35324c18794SDmytro Laktyushkin uint32_t enable : 1; 35424c18794SDmytro Laktyushkin uint32_t disable : 1; 35524c18794SDmytro Laktyushkin uint32_t odm : 1; 35624c18794SDmytro Laktyushkin uint32_t global_sync : 1; 35724c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 35824c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 35924c18794SDmytro Laktyushkin uint32_t mpcc : 1; 36024c18794SDmytro Laktyushkin uint32_t dppclk : 1; 36124c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 36224c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 36324c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 36424c18794SDmytro Laktyushkin uint32_t scaler : 1; 36524c18794SDmytro Laktyushkin uint32_t viewport : 1; 366498563cfSJinZe.Xu uint32_t plane_changed : 1; 367ba5a5371SNicholas Kazlauskas uint32_t det_size : 1; 36824c18794SDmytro Laktyushkin } bits; 36924c18794SDmytro Laktyushkin uint32_t raw; 37024c18794SDmytro Laktyushkin }; 37124c18794SDmytro Laktyushkin 3724562236bSHarry Wentland struct pipe_ctx { 3733be5262eSHarry Wentland struct dc_plane_state *plane_state; 3740971c40eSHarry Wentland struct dc_stream_state *stream; 3754562236bSHarry Wentland 37679b06f0cSHarry Wentland struct plane_resource plane_res; 37779b06f0cSHarry Wentland struct stream_resource stream_res; 378ef30f441SWenjing Liu struct link_resource link_res; 37979b06f0cSHarry Wentland 3804562236bSHarry Wentland struct clock_source *clock_source; 3814562236bSHarry Wentland 3824562236bSHarry Wentland struct pll_settings pll_settings; 3834562236bSHarry Wentland 3844562236bSHarry Wentland uint8_t pipe_idx; 385a896f870SMeenakshikumar Somasundaram uint8_t pipe_idx_syncd; 3864562236bSHarry Wentland 3874562236bSHarry Wentland struct pipe_ctx *top_pipe; 3884562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 389b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 390b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 391f0558542SDmytro Laktyushkin 392b86a1aa3SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_DCN 393ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 394ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 395ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 396ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 3971f2fcc81SHarry Wentland struct _vcs_dpi_display_rq_params_st dml_rq_param; 3981f2fcc81SHarry Wentland struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 3991f2fcc81SHarry Wentland struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 400ba5a5371SNicholas Kazlauskas int det_buffer_size_kb; 401ba5a5371SNicholas Kazlauskas bool unbounded_req; 402ba5a5371SNicholas Kazlauskas #endif 40324c18794SDmytro Laktyushkin union pipe_update_flags update_flags; 404345429a6SHarry Wentland struct dwbc *dwbc; 405345429a6SHarry Wentland struct mcif_wb *mcif_wb; 406d209124dSBhawanpreet Lakha bool vtp_locked; 4074562236bSHarry Wentland }; 4084562236bSHarry Wentland 4090d4b4253SJimmy Kizito /* Data used for dynamic link encoder assignment. 4100d4b4253SJimmy Kizito * Tracks current and future assignments; available link encoders; 4110d4b4253SJimmy Kizito * and mode of operation (whether to use current or future assignments). 4120d4b4253SJimmy Kizito */ 4130d4b4253SJimmy Kizito struct link_enc_cfg_context { 4140d4b4253SJimmy Kizito enum link_enc_cfg_mode mode; 4150d4b4253SJimmy Kizito struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 4160d4b4253SJimmy Kizito enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 4170d4b4253SJimmy Kizito struct link_enc_assignment transient_assignments[MAX_PIPES]; 4180d4b4253SJimmy Kizito }; 4190d4b4253SJimmy Kizito 4204562236bSHarry Wentland struct resource_context { 4214562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 4224562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 4234562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 4244562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 4254562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 426345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 4270d4b4253SJimmy Kizito struct link_enc_cfg_context link_enc_cfg_ctx; 42820f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 42983228ebbSFangzhi Zuo bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 4306dd8931bSWenjing Liu unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 4316dd8931bSWenjing Liu int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 43283228ebbSFangzhi Zuo #endif 43383228ebbSFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 4345dba4991SBhawanpreet Lakha bool is_mpc_3dlut_acquired[MAX_PIPES]; 4355dba4991SBhawanpreet Lakha #endif 4364562236bSHarry Wentland }; 4374562236bSHarry Wentland 4389037d802SDmytro Laktyushkin struct dce_bw_output { 4399037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 4409037d802SDmytro Laktyushkin bool cpup_state_change_enable; 4419037d802SDmytro Laktyushkin bool stutter_mode_enable; 4429037d802SDmytro Laktyushkin bool nbp_state_change_enable; 4439037d802SDmytro Laktyushkin bool all_displays_in_sync; 4449037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 4459037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 446b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 4479037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 4489037d802SDmytro Laktyushkin int sclk_khz; 4499037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 4509037d802SDmytro Laktyushkin int yclk_khz; 4519037d802SDmytro Laktyushkin int dispclk_khz; 4529037d802SDmytro Laktyushkin int blackout_recovery_time_us; 4539037d802SDmytro Laktyushkin }; 4549037d802SDmytro Laktyushkin 455345429a6SHarry Wentland struct dcn_bw_writeback { 456345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 457345429a6SHarry Wentland }; 458345429a6SHarry Wentland 4599037d802SDmytro Laktyushkin struct dcn_bw_output { 460d578839cSDmytro Laktyushkin struct dc_clocks clk; 4619037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 462345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 463ba5a5371SNicholas Kazlauskas int compbuf_size_kb; 4649037d802SDmytro Laktyushkin }; 4659037d802SDmytro Laktyushkin 466813d20dcSAidan Wood union bw_output { 4679037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 4689037d802SDmytro Laktyushkin struct dce_bw_output dce; 4699037d802SDmytro Laktyushkin }; 4709037d802SDmytro Laktyushkin 471813d20dcSAidan Wood struct bw_context { 472813d20dcSAidan Wood union bw_output bw; 473813d20dcSAidan Wood struct display_mode_lib dml; 474813d20dcSAidan Wood }; 4752119aa17SDavid Francis /** 4762119aa17SDavid Francis * struct dc_state - The full description of a state requested by a user 4772119aa17SDavid Francis * 4782119aa17SDavid Francis * @streams: Stream properties 4792119aa17SDavid Francis * @stream_status: The planes on a given stream 4802119aa17SDavid Francis * @res_ctx: Persistent state of resources 481813d20dcSAidan Wood * @bw_ctx: The output from bandwidth and watermark calculations and the DML 4822119aa17SDavid Francis * @pp_display_cfg: PowerPlay clocks and settings 4832119aa17SDavid Francis * @dcn_bw_vars: non-stack memory to support bandwidth calculations 4842119aa17SDavid Francis * 4852119aa17SDavid Francis */ 486608ac7bbSJerry Zuo struct dc_state { 4870971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 488ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 489ab2541b6SAric Cyr uint8_t stream_count; 4900825d965SEric Yang uint8_t stream_mask; 4914562236bSHarry Wentland 4924562236bSHarry Wentland struct resource_context res_ctx; 4934562236bSHarry Wentland 494813d20dcSAidan Wood struct bw_context bw_ctx; 4959037d802SDmytro Laktyushkin 4965ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 4974562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 498b86a1aa3SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_DCN 499ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 500ff5ef992SAlex Deucher #endif 5018a76708eSAndrey Grodzovsky 5020de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 503ab8db3e1SAndrey Grodzovsky 5048ee5702aSDave Airlie struct kref refcount; 5056b85151fSMartin Leung 5066b85151fSMartin Leung struct { 5076b85151fSMartin Leung unsigned int stutter_period_us; 5086b85151fSMartin Leung } perf_params; 5094562236bSHarry Wentland }; 5104562236bSHarry Wentland 5114562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 512