14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 35391e20d8SDuke Du #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 36ff5ef992SAlex Deucher #include "mpc.h" 37391e20d8SDuke Du #endif 38391e20d8SDuke Du #include "dwb.h" 394562236bSHarry Wentland 404562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 414562236bSHarry Wentland 423be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 434562236bSHarry Wentland uint32_t controller_id); 444562236bSHarry Wentland 454562236bSHarry Wentland #include "grph_object_id.h" 464562236bSHarry Wentland #include "link_encoder.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "clock_source.h" 494562236bSHarry Wentland #include "audio.h" 504562236bSHarry Wentland #include "hw_sequencer_types.h" 514562236bSHarry Wentland 524562236bSHarry Wentland 534562236bSHarry Wentland /************ link *****************/ 544562236bSHarry Wentland struct link_init_data { 554562236bSHarry Wentland const struct core_dc *dc; 564562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 574562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 584562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 594562236bSHarry Wentland TODO: remove it when DC is complete. */ 604562236bSHarry Wentland }; 614562236bSHarry Wentland 62d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 63d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 644562236bSHarry Wentland 654562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 660971c40eSHarry Wentland const struct dc_stream_state *stream, 67d0778ebfSHarry Wentland struct dc_link *link, 684562236bSHarry Wentland const struct dc_crtc_timing *timing); 694562236bSHarry Wentland 70d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 714562236bSHarry Wentland 724562236bSHarry Wentland void core_link_enable_stream(struct pipe_ctx *pipe_ctx); 734562236bSHarry Wentland 744562236bSHarry Wentland void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 754562236bSHarry Wentland 7615e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 774562236bSHarry Wentland /********** DAL Core*********************/ 78e11b86adSDmytro Laktyushkin #include "display_clock.h" 794562236bSHarry Wentland #include "transform.h" 804562236bSHarry Wentland 814562236bSHarry Wentland struct resource_pool; 824562236bSHarry Wentland struct validate_context; 834562236bSHarry Wentland struct resource_context; 844562236bSHarry Wentland 854562236bSHarry Wentland struct resource_funcs { 864562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 874562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 884562236bSHarry Wentland const struct encoder_init_data *init); 894562236bSHarry Wentland enum dc_status (*validate_with_context)( 904562236bSHarry Wentland const struct core_dc *dc, 914562236bSHarry Wentland const struct dc_validation_set set[], 924562236bSHarry Wentland int set_count, 93430ef426SDmytro Laktyushkin struct validate_context *context, 94430ef426SDmytro Laktyushkin struct validate_context *old_context); 954562236bSHarry Wentland 964562236bSHarry Wentland enum dc_status (*validate_guaranteed)( 974562236bSHarry Wentland const struct core_dc *dc, 980971c40eSHarry Wentland struct dc_stream_state *stream, 994562236bSHarry Wentland struct validate_context *context); 1004562236bSHarry Wentland 10145209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 1024562236bSHarry Wentland const struct core_dc *dc, 1034562236bSHarry Wentland struct validate_context *context); 1044562236bSHarry Wentland 1054562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 106745cc746SDmytro Laktyushkin struct validate_context *context, 107a2b8659dSTony Cheng const struct resource_pool *pool, 1080971c40eSHarry Wentland struct dc_stream_state *stream); 109c9614aebSHarry Wentland enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); 1104562236bSHarry Wentland }; 1114562236bSHarry Wentland 1124562236bSHarry Wentland struct audio_support{ 1134562236bSHarry Wentland bool dp_audio; 1144562236bSHarry Wentland bool hdmi_audio_on_dongle; 1154562236bSHarry Wentland bool hdmi_audio_native; 1164562236bSHarry Wentland }; 1174562236bSHarry Wentland 118f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 119f0e3db90SHarry Wentland 1204562236bSHarry Wentland struct resource_pool { 1214562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 1224562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 1234562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 1244562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 1254562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 1264562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 127f0558542SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 128cc408d72SDmytro Laktyushkin struct mpc *mpc; 129f0558542SDmytro Laktyushkin #endif 1304562236bSHarry Wentland 131391e20d8SDuke Du struct dwbc *dwbc[MAX_DWB_PIPES]; 132391e20d8SDuke Du 1334562236bSHarry Wentland unsigned int pipe_count; 1344562236bSHarry Wentland unsigned int underlay_pipe_index; 1354562236bSHarry Wentland unsigned int stream_enc_count; 1365ac3d3c9SCharlene Liu unsigned int ref_clock_inKhz; 1374562236bSHarry Wentland 1384562236bSHarry Wentland /* 1394562236bSHarry Wentland * reserved clock source for DP 1404562236bSHarry Wentland */ 1414562236bSHarry Wentland struct clock_source *dp_clock_source; 1424562236bSHarry Wentland 1434562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 1444562236bSHarry Wentland unsigned int clk_src_count; 1454562236bSHarry Wentland 1464562236bSHarry Wentland struct audio *audios[MAX_PIPES]; 1474562236bSHarry Wentland unsigned int audio_count; 1484562236bSHarry Wentland struct audio_support audio_support; 1494562236bSHarry Wentland 1504562236bSHarry Wentland struct display_clock *display_clock; 1514562236bSHarry Wentland struct irq_service *irqs; 1524562236bSHarry Wentland 1535e7773a2SAnthony Koo struct abm *abm; 1545e7773a2SAnthony Koo struct dmcu *dmcu; 1555e7773a2SAnthony Koo 1564562236bSHarry Wentland const struct resource_funcs *funcs; 1574562236bSHarry Wentland const struct resource_caps *res_cap; 1584562236bSHarry Wentland }; 1594562236bSHarry Wentland 16079b06f0cSHarry Wentland struct stream_resource { 161a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 1626b670fa9SHarry Wentland struct timing_generator *tg; 1638e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 164afaacef4SHarry Wentland struct audio *audio; 16510688217SHarry Wentland 16610688217SHarry Wentland struct pixel_clk_params pix_clk_params; 16796c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 16879b06f0cSHarry Wentland }; 16979b06f0cSHarry Wentland 17079b06f0cSHarry Wentland struct plane_resource { 1716702a9acSHarry Wentland struct scaler_data scl_data; 17286a66c4eSHarry Wentland 17386a66c4eSHarry Wentland struct mem_input *mi; 17486a66c4eSHarry Wentland struct input_pixel_processor *ipp; 17586a66c4eSHarry Wentland struct transform *xfm; 17679b06f0cSHarry Wentland }; 17779b06f0cSHarry Wentland 1784562236bSHarry Wentland struct pipe_ctx { 1793be5262eSHarry Wentland struct dc_plane_state *plane_state; 1800971c40eSHarry Wentland struct dc_stream_state *stream; 1814562236bSHarry Wentland 18279b06f0cSHarry Wentland struct plane_resource plane_res; 18379b06f0cSHarry Wentland struct stream_resource stream_res; 18479b06f0cSHarry Wentland 1854562236bSHarry Wentland struct display_clock *dis_clk; 1864562236bSHarry Wentland struct clock_source *clock_source; 1874562236bSHarry Wentland 1884562236bSHarry Wentland struct pll_settings pll_settings; 1894562236bSHarry Wentland 1904562236bSHarry Wentland uint8_t pipe_idx; 1914562236bSHarry Wentland 1924562236bSHarry Wentland struct pipe_ctx *top_pipe; 1934562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 194f0558542SDmytro Laktyushkin 195ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 196ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 197ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 198ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 199ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 200ff5ef992SAlex Deucher #endif 201391e20d8SDuke Du struct dwbc *dwbc; 2024562236bSHarry Wentland }; 2034562236bSHarry Wentland 2044562236bSHarry Wentland struct resource_context { 2054562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 2064562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 2074562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 2084562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 2094562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 2104562236bSHarry Wentland }; 2114562236bSHarry Wentland 2129037d802SDmytro Laktyushkin struct dce_bw_output { 2139037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 2149037d802SDmytro Laktyushkin bool cpup_state_change_enable; 2159037d802SDmytro Laktyushkin bool stutter_mode_enable; 2169037d802SDmytro Laktyushkin bool nbp_state_change_enable; 2179037d802SDmytro Laktyushkin bool all_displays_in_sync; 2189037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 2199037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 2209037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 2219037d802SDmytro Laktyushkin int sclk_khz; 2229037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 2239037d802SDmytro Laktyushkin int yclk_khz; 2249037d802SDmytro Laktyushkin int dispclk_khz; 2259037d802SDmytro Laktyushkin int blackout_recovery_time_us; 2269037d802SDmytro Laktyushkin }; 2279037d802SDmytro Laktyushkin 2289037d802SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 2299037d802SDmytro Laktyushkin struct dcn_bw_clocks { 2309037d802SDmytro Laktyushkin int dispclk_khz; 2319037d802SDmytro Laktyushkin bool dppclk_div; 2329037d802SDmytro Laktyushkin int dcfclk_khz; 2339037d802SDmytro Laktyushkin int dcfclk_deep_sleep_khz; 2349037d802SDmytro Laktyushkin int fclk_khz; 2359037d802SDmytro Laktyushkin int dram_ccm_us; 2369037d802SDmytro Laktyushkin int min_active_dram_ccm_us; 2379037d802SDmytro Laktyushkin }; 2389037d802SDmytro Laktyushkin 2399037d802SDmytro Laktyushkin struct dcn_bw_output { 2409037d802SDmytro Laktyushkin struct dcn_bw_clocks cur_clk; 2419037d802SDmytro Laktyushkin struct dcn_bw_clocks calc_clk; 2429037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 2439037d802SDmytro Laktyushkin }; 2449037d802SDmytro Laktyushkin #endif 2459037d802SDmytro Laktyushkin 2469037d802SDmytro Laktyushkin union bw_context { 2479037d802SDmytro Laktyushkin #ifdef CONFIG_DRM_AMD_DC_DCN1_0 2489037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 2499037d802SDmytro Laktyushkin #endif 2509037d802SDmytro Laktyushkin struct dce_bw_output dce; 2519037d802SDmytro Laktyushkin }; 2529037d802SDmytro Laktyushkin 2534562236bSHarry Wentland struct validate_context { 2540971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 255ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 256ab2541b6SAric Cyr uint8_t stream_count; 2574562236bSHarry Wentland 2584562236bSHarry Wentland struct resource_context res_ctx; 2594562236bSHarry Wentland 2604562236bSHarry Wentland /* The output from BW and WM calculations. */ 2619037d802SDmytro Laktyushkin union bw_context bw; 2629037d802SDmytro Laktyushkin 2635ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 2644562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 265ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 266ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 267ff5ef992SAlex Deucher #endif 2688a76708eSAndrey Grodzovsky 269e8cd2643SJerry Zuo atomic_t ref_count; 2704562236bSHarry Wentland }; 2714562236bSHarry Wentland 2724562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 273