14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 37ff5ef992SAlex Deucher #include "mpc.h" 38391e20d8SDuke Du #endif 39345429a6SHarry Wentland #include "dwb.h" 40345429a6SHarry Wentland #include "mcif_wb.h" 41d4caa72eSAnthony Koo #include "panel_cntl.h" 424562236bSHarry Wentland 434562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 444562236bSHarry Wentland 453be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 464562236bSHarry Wentland uint32_t controller_id); 474562236bSHarry Wentland 484562236bSHarry Wentland #include "grph_object_id.h" 494562236bSHarry Wentland #include "link_encoder.h" 504562236bSHarry Wentland #include "stream_encoder.h" 514562236bSHarry Wentland #include "clock_source.h" 524562236bSHarry Wentland #include "audio.h" 53a185048cSTony Cheng #include "dm_pp_smu.h" 54d462fcf5SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_HDCP 55d462fcf5SBhawanpreet Lakha #include "dm_cp_psp.h" 56d462fcf5SBhawanpreet Lakha #endif 574562236bSHarry Wentland 584562236bSHarry Wentland /************ link *****************/ 594562236bSHarry Wentland struct link_init_data { 60fb3466a4SBhawanpreet Lakha const struct dc *dc; 614562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 624562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 634562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 644562236bSHarry Wentland TODO: remove it when DC is complete. */ 654562236bSHarry Wentland }; 664562236bSHarry Wentland 67d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 68d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 694562236bSHarry Wentland 704562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 710971c40eSHarry Wentland const struct dc_stream_state *stream, 72d0778ebfSHarry Wentland struct dc_link *link, 734562236bSHarry Wentland const struct dc_crtc_timing *timing); 744562236bSHarry Wentland 75d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 764562236bSHarry Wentland 77ab8db3e1SAndrey Grodzovsky void core_link_enable_stream( 78ab8db3e1SAndrey Grodzovsky struct dc_state *state, 79ab8db3e1SAndrey Grodzovsky struct pipe_ctx *pipe_ctx); 804562236bSHarry Wentland 8157430404SSu Sung Chung void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 824562236bSHarry Wentland 8315e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 844562236bSHarry Wentland /********** DAL Core*********************/ 854562236bSHarry Wentland #include "transform.h" 86d94585a0SYue Hin Lau #include "dpp.h" 874562236bSHarry Wentland 884562236bSHarry Wentland struct resource_pool; 89608ac7bbSJerry Zuo struct dc_state; 904562236bSHarry Wentland struct resource_context; 91aa919167SBhawanpreet Lakha struct clk_bw_params; 924562236bSHarry Wentland 934562236bSHarry Wentland struct resource_funcs { 944562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 9566b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 96d4caa72eSAnthony Koo struct panel_cntl*(*panel_cntl_create)( 97d4caa72eSAnthony Koo const struct panel_cntl_init_data *panel_cntl_init_data); 984562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 994562236bSHarry Wentland const struct encoder_init_data *init); 10045209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 101fb3466a4SBhawanpreet Lakha struct dc *dc, 102afcd526bSJoshua Aberback struct dc_state *context, 103afcd526bSJoshua Aberback bool fast_validate); 1048e02c26aSJoshua Aberback void (*calculate_wm_and_dlg)( 105b3ff538cSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 106b3ff538cSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 107b3ff538cSDmytro Laktyushkin int pipe_cnt, 108b3ff538cSDmytro Laktyushkin int vlevel); 109ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 110ed07237cSIlya Bakoulin struct dc *dc, 1112f488884SAlvin Lee struct dc_state *context, 112ed07237cSIlya Bakoulin display_e2e_pipe_params_st *pipes); 113ed07237cSIlya Bakoulin 1141dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1151dc90497SAndrey Grodzovsky struct dc *dc, 116608ac7bbSJerry Zuo struct dc_state *context); 1171dc90497SAndrey Grodzovsky 1184562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 119608ac7bbSJerry Zuo struct dc_state *context, 120a2b8659dSTony Cheng const struct resource_pool *pool, 1210971c40eSHarry Wentland struct dc_stream_state *stream); 1221dc90497SAndrey Grodzovsky 1238e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1241dc90497SAndrey Grodzovsky 1251dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1261dc90497SAndrey Grodzovsky struct dc *dc, 127608ac7bbSJerry Zuo struct dc_state *new_ctx, 1281dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 129e56ae556SNikola Cornij 130e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 131e56ae556SNikola Cornij struct dc *dc, 132e56ae556SNikola Cornij struct dc_state *new_ctx, 133e56ae556SNikola Cornij struct dc_stream_state *stream); 1348d8c82b6SJoseph Gravenor enum dc_status (*patch_unknown_plane_state)( 13574eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 13674eac5f3SSu Sung Chung 13778cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 13878cc70b1SWesley Chalmers struct resource_context *res_ctx, 13978cc70b1SWesley Chalmers const struct resource_pool *pool, 14078cc70b1SWesley Chalmers struct dc_stream_state *stream); 141345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 142345429a6SHarry Wentland struct dc *dc, 143345429a6SHarry Wentland struct resource_context *res_ctx, 144345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 14578cc70b1SWesley Chalmers 146345429a6SHarry Wentland void (*set_mcif_arb_params)( 147345429a6SHarry Wentland struct dc *dc, 148345429a6SHarry Wentland struct dc_state *context, 149345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 150345429a6SHarry Wentland int pipe_cnt); 1511b2c7b2cSBhawanpreet Lakha void (*update_bw_bounding_box)( 1521b2c7b2cSBhawanpreet Lakha struct dc *dc, 1531b2c7b2cSBhawanpreet Lakha struct clk_bw_params *bw_params); 154*20f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 1555dba4991SBhawanpreet Lakha bool (*acquire_post_bldn_3dlut)( 1565dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1575dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1585dba4991SBhawanpreet Lakha int mpcc_id, 1595dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1605dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1615dba4991SBhawanpreet Lakha 1625dba4991SBhawanpreet Lakha bool (*release_post_bldn_3dlut)( 1635dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1645dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1655dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1665dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1675dba4991SBhawanpreet Lakha #endif 168b4f71c8cSAurabindo Pillai enum dc_status (*add_dsc_to_stream_resource)( 169b4f71c8cSAurabindo Pillai struct dc *dc, struct dc_state *state, 170b4f71c8cSAurabindo Pillai struct dc_stream_state *stream); 1714562236bSHarry Wentland }; 1724562236bSHarry Wentland 1734562236bSHarry Wentland struct audio_support{ 1744562236bSHarry Wentland bool dp_audio; 1754562236bSHarry Wentland bool hdmi_audio_on_dongle; 1764562236bSHarry Wentland bool hdmi_audio_native; 1774562236bSHarry Wentland }; 1784562236bSHarry Wentland 179f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 180f0e3db90SHarry Wentland 1814562236bSHarry Wentland struct resource_pool { 1824562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 1838feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 1844562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 1854562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 186d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 1874562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 1884562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 1894562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 190c9ef081dSYue Hin Lau struct hubbub *hubbub; 191cc408d72SDmytro Laktyushkin struct mpc *mpc; 1920f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 1931877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 194c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 195c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 196c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 1974562236bSHarry Wentland 198345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 199345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 200345429a6SHarry Wentland struct { 201345429a6SHarry Wentland unsigned int gsl_0:1; 202345429a6SHarry Wentland unsigned int gsl_1:1; 203345429a6SHarry Wentland unsigned int gsl_2:1; 204345429a6SHarry Wentland } gsl_groups; 205345429a6SHarry Wentland 20697bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 207345429a6SHarry Wentland 2084562236bSHarry Wentland unsigned int pipe_count; 2094562236bSHarry Wentland unsigned int underlay_pipe_index; 2104562236bSHarry Wentland unsigned int stream_enc_count; 211929c3aaaSEric Bernstein 212*20f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 2135dba4991SBhawanpreet Lakha struct dc_3dlut *mpc_lut[MAX_PIPES]; 2145dba4991SBhawanpreet Lakha struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 2155dba4991SBhawanpreet Lakha #endif 21633d7598dSJun Lei struct { 21733d7598dSJun Lei unsigned int xtalin_clock_inKhz; 21833d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 21933d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 22033d7598dSJun Lei } ref_clocks; 2213be1406aSYongqiang Sun unsigned int timing_generator_count; 222345429a6SHarry Wentland unsigned int mpcc_count; 2234562236bSHarry Wentland 224345429a6SHarry Wentland unsigned int writeback_pipe_count; 2254562236bSHarry Wentland /* 2264562236bSHarry Wentland * reserved clock source for DP 2274562236bSHarry Wentland */ 2284562236bSHarry Wentland struct clock_source *dp_clock_source; 2294562236bSHarry Wentland 2304562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 2314562236bSHarry Wentland unsigned int clk_src_count; 2324562236bSHarry Wentland 2337352193aSTai Man struct audio *audios[MAX_AUDIOS]; 2344562236bSHarry Wentland unsigned int audio_count; 2354562236bSHarry Wentland struct audio_support audio_support; 2364562236bSHarry Wentland 237ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 2384562236bSHarry Wentland struct irq_service *irqs; 2394562236bSHarry Wentland 2405e7773a2SAnthony Koo struct abm *abm; 2415e7773a2SAnthony Koo struct dmcu *dmcu; 2424c1a1335SWyatt Wood struct dmub_psr *psr; 2435e7773a2SAnthony Koo 244*20f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 245d99f1387SBhawanpreet Lakha struct abm *multiple_abms[MAX_PIPES]; 246d99f1387SBhawanpreet Lakha #endif 247d99f1387SBhawanpreet Lakha 2484562236bSHarry Wentland const struct resource_funcs *funcs; 2494562236bSHarry Wentland const struct resource_caps *res_cap; 250d9a07577SJun Lei 251d9a07577SJun Lei struct ddc_service *oem_device; 2524562236bSHarry Wentland }; 2534562236bSHarry Wentland 254f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 25569338c1fSDmytro Laktyushkin int dppclk_khz; 256799c5b9cSWesley Chalmers 257f553e681SDmytro Laktyushkin }; 258f553e681SDmytro Laktyushkin 25979b06f0cSHarry Wentland struct stream_resource { 260a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 26197bda032SHarry Wentland struct display_stream_compressor *dsc; 2626b670fa9SHarry Wentland struct timing_generator *tg; 2638e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 264afaacef4SHarry Wentland struct audio *audio; 26510688217SHarry Wentland 26610688217SHarry Wentland struct pixel_clk_params pix_clk_params; 26796c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 2689aef1a31SSivapiriyanKumarasamy 2699aef1a31SSivapiriyanKumarasamy struct abm *abm; 270345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 271345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 272345429a6SHarry Wentland */ 273345429a6SHarry Wentland uint8_t gsl_group; 27479b06f0cSHarry Wentland }; 27579b06f0cSHarry Wentland 27679b06f0cSHarry Wentland struct plane_resource { 2776702a9acSHarry Wentland struct scaler_data scl_data; 2788feabd03SYue Hin Lau struct hubp *hubp; 27986a66c4eSHarry Wentland struct mem_input *mi; 28086a66c4eSHarry Wentland struct input_pixel_processor *ipp; 28186a66c4eSHarry Wentland struct transform *xfm; 282d94585a0SYue Hin Lau struct dpp *dpp; 283e07f541fSYongqiang Sun uint8_t mpcc_inst; 284f553e681SDmytro Laktyushkin 285f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 28679b06f0cSHarry Wentland }; 28779b06f0cSHarry Wentland 28824c18794SDmytro Laktyushkin union pipe_update_flags { 28924c18794SDmytro Laktyushkin struct { 29024c18794SDmytro Laktyushkin uint32_t enable : 1; 29124c18794SDmytro Laktyushkin uint32_t disable : 1; 29224c18794SDmytro Laktyushkin uint32_t odm : 1; 29324c18794SDmytro Laktyushkin uint32_t global_sync : 1; 29424c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 29524c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 29624c18794SDmytro Laktyushkin uint32_t mpcc : 1; 29724c18794SDmytro Laktyushkin uint32_t dppclk : 1; 29824c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 29924c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 30024c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 30124c18794SDmytro Laktyushkin uint32_t scaler : 1; 30224c18794SDmytro Laktyushkin uint32_t viewport : 1; 303498563cfSJinZe.Xu uint32_t plane_changed : 1; 30424c18794SDmytro Laktyushkin } bits; 30524c18794SDmytro Laktyushkin uint32_t raw; 30624c18794SDmytro Laktyushkin }; 30724c18794SDmytro Laktyushkin 3084562236bSHarry Wentland struct pipe_ctx { 3093be5262eSHarry Wentland struct dc_plane_state *plane_state; 3100971c40eSHarry Wentland struct dc_stream_state *stream; 3114562236bSHarry Wentland 31279b06f0cSHarry Wentland struct plane_resource plane_res; 31379b06f0cSHarry Wentland struct stream_resource stream_res; 31479b06f0cSHarry Wentland 3154562236bSHarry Wentland struct clock_source *clock_source; 3164562236bSHarry Wentland 3174562236bSHarry Wentland struct pll_settings pll_settings; 3184562236bSHarry Wentland 3194562236bSHarry Wentland uint8_t pipe_idx; 3204562236bSHarry Wentland 3214562236bSHarry Wentland struct pipe_ctx *top_pipe; 3224562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 323b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 324b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 325f0558542SDmytro Laktyushkin 326b86a1aa3SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_DCN 327ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 328ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 329ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 330ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 331ff5ef992SAlex Deucher #endif 33224c18794SDmytro Laktyushkin union pipe_update_flags update_flags; 333345429a6SHarry Wentland struct dwbc *dwbc; 334345429a6SHarry Wentland struct mcif_wb *mcif_wb; 3354562236bSHarry Wentland }; 3364562236bSHarry Wentland 3374562236bSHarry Wentland struct resource_context { 3384562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 3394562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 3404562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 3414562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 3424562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 343345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 344*20f2ffe5SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 3455dba4991SBhawanpreet Lakha bool is_mpc_3dlut_acquired[MAX_PIPES]; 3465dba4991SBhawanpreet Lakha #endif 3474562236bSHarry Wentland }; 3484562236bSHarry Wentland 3499037d802SDmytro Laktyushkin struct dce_bw_output { 3509037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 3519037d802SDmytro Laktyushkin bool cpup_state_change_enable; 3529037d802SDmytro Laktyushkin bool stutter_mode_enable; 3539037d802SDmytro Laktyushkin bool nbp_state_change_enable; 3549037d802SDmytro Laktyushkin bool all_displays_in_sync; 3559037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 3569037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 357b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 3589037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 3599037d802SDmytro Laktyushkin int sclk_khz; 3609037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 3619037d802SDmytro Laktyushkin int yclk_khz; 3629037d802SDmytro Laktyushkin int dispclk_khz; 3639037d802SDmytro Laktyushkin int blackout_recovery_time_us; 3649037d802SDmytro Laktyushkin }; 3659037d802SDmytro Laktyushkin 366345429a6SHarry Wentland struct dcn_bw_writeback { 367345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 368345429a6SHarry Wentland }; 369345429a6SHarry Wentland 3709037d802SDmytro Laktyushkin struct dcn_bw_output { 371d578839cSDmytro Laktyushkin struct dc_clocks clk; 3729037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 373345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 3749037d802SDmytro Laktyushkin }; 3759037d802SDmytro Laktyushkin 376813d20dcSAidan Wood union bw_output { 3779037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 3789037d802SDmytro Laktyushkin struct dce_bw_output dce; 3799037d802SDmytro Laktyushkin }; 3809037d802SDmytro Laktyushkin 381813d20dcSAidan Wood struct bw_context { 382813d20dcSAidan Wood union bw_output bw; 383813d20dcSAidan Wood struct display_mode_lib dml; 384813d20dcSAidan Wood }; 3852119aa17SDavid Francis /** 3862119aa17SDavid Francis * struct dc_state - The full description of a state requested by a user 3872119aa17SDavid Francis * 3882119aa17SDavid Francis * @streams: Stream properties 3892119aa17SDavid Francis * @stream_status: The planes on a given stream 3902119aa17SDavid Francis * @res_ctx: Persistent state of resources 391813d20dcSAidan Wood * @bw_ctx: The output from bandwidth and watermark calculations and the DML 3922119aa17SDavid Francis * @pp_display_cfg: PowerPlay clocks and settings 3932119aa17SDavid Francis * @dcn_bw_vars: non-stack memory to support bandwidth calculations 3942119aa17SDavid Francis * 3952119aa17SDavid Francis */ 396608ac7bbSJerry Zuo struct dc_state { 3970971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 398ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 399ab2541b6SAric Cyr uint8_t stream_count; 4000825d965SEric Yang uint8_t stream_mask; 4014562236bSHarry Wentland 4024562236bSHarry Wentland struct resource_context res_ctx; 4034562236bSHarry Wentland 404813d20dcSAidan Wood struct bw_context bw_ctx; 4059037d802SDmytro Laktyushkin 4065ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 4074562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 408b86a1aa3SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_DCN 409ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 410ff5ef992SAlex Deucher #endif 4118a76708eSAndrey Grodzovsky 4120de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 413ab8db3e1SAndrey Grodzovsky 4148ee5702aSDave Airlie struct kref refcount; 4156b85151fSMartin Leung 4166b85151fSMartin Leung struct { 4176b85151fSMartin Leung unsigned int stutter_period_us; 4186b85151fSMartin Leung } perf_params; 4194562236bSHarry Wentland }; 4204562236bSHarry Wentland 4214562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 422