1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 /* 29 * Pre-requisites: headers required by header of this unit 30 */ 31 #include "include/gpio_types.h" 32 33 /* 34 * Header of this unit 35 */ 36 37 #include "hw_translate.h" 38 39 /* 40 * Post-requisites: headers required by this unit 41 */ 42 43 #include "dce80/hw_translate_dce80.h" 44 #include "dce110/hw_translate_dce110.h" 45 #include "dce120/hw_translate_dce120.h" 46 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 47 #include "dcn10/hw_translate_dcn10.h" 48 #endif 49 #include "dcn20/hw_translate_dcn20.h" 50 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 51 #include "dcn21/hw_translate_dcn21.h" 52 #endif 53 54 #include "diagnostics/hw_translate_diag.h" 55 56 /* 57 * This unit 58 */ 59 60 bool dal_hw_translate_init( 61 struct hw_translate *translate, 62 enum dce_version dce_version, 63 enum dce_environment dce_environment) 64 { 65 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { 66 dal_hw_translate_diag_fpga_init(translate); 67 return true; 68 } 69 70 switch (dce_version) { 71 case DCE_VERSION_8_0: 72 case DCE_VERSION_8_1: 73 case DCE_VERSION_8_3: 74 dal_hw_translate_dce80_init(translate); 75 return true; 76 case DCE_VERSION_10_0: 77 case DCE_VERSION_11_0: 78 case DCE_VERSION_11_2: 79 case DCE_VERSION_11_22: 80 dal_hw_translate_dce110_init(translate); 81 return true; 82 case DCE_VERSION_12_0: 83 case DCE_VERSION_12_1: 84 dal_hw_translate_dce120_init(translate); 85 return true; 86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 87 case DCN_VERSION_1_0: 88 case DCN_VERSION_1_01: 89 dal_hw_translate_dcn10_init(translate); 90 return true; 91 92 case DCN_VERSION_2_0: 93 dal_hw_translate_dcn20_init(translate); 94 return true; 95 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 96 case DCN_VERSION_2_1: 97 dal_hw_translate_dcn21_init(translate); 98 return true; 99 #endif 100 #endif 101 102 default: 103 BREAK_TO_DEBUGGER(); 104 return false; 105 } 106 } 107