1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dm_services.h" 29 30 #include "include/gpio_types.h" 31 #include "hw_gpio.h" 32 #include "hw_ddc.h" 33 34 #include "reg_helper.h" 35 #include "gpio_regs.h" 36 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 ddc->shifts->field_name, ddc->masks->field_name 41 42 #define CTX \ 43 ddc->base.base.ctx 44 #define REG(reg)\ 45 (ddc->regs->reg) 46 47 static void destruct( 48 struct hw_ddc *pin) 49 { 50 dal_hw_gpio_destruct(&pin->base); 51 } 52 53 static void destroy( 54 struct hw_gpio_pin **ptr) 55 { 56 struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr); 57 58 destruct(pin); 59 60 kfree(pin); 61 62 *ptr = NULL; 63 } 64 65 static enum gpio_result set_config( 66 struct hw_gpio_pin *ptr, 67 const struct gpio_config_data *config_data) 68 { 69 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); 70 struct hw_gpio *hw_gpio = NULL; 71 uint32_t regval; 72 uint32_t ddc_data_pd_en = 0; 73 uint32_t ddc_clk_pd_en = 0; 74 uint32_t aux_pad_mode = 0; 75 76 hw_gpio = &ddc->base; 77 78 if (hw_gpio == NULL) { 79 ASSERT_CRITICAL(false); 80 return GPIO_RESULT_NULL_HANDLE; 81 } 82 83 regval = REG_GET_3(gpio.MASK_reg, 84 DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en, 85 DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en, 86 AUX_PAD1_MODE, &aux_pad_mode); 87 88 switch (config_data->config.ddc.type) { 89 case GPIO_DDC_CONFIG_TYPE_MODE_I2C: 90 /* On plug-in, there is a transient level on the pad 91 * which must be discharged through the internal pull-down. 92 * Enable internal pull-down, 2.5msec discharge time 93 * is required for detection of AUX mode */ 94 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { 95 if (!ddc_data_pd_en || !ddc_clk_pd_en) { 96 97 REG_SET_2(gpio.MASK_reg, regval, 98 DC_GPIO_DDC1DATA_PD_EN, 1, 99 DC_GPIO_DDC1CLK_PD_EN, 1); 100 101 if (config_data->type == 102 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 103 msleep(3); 104 } 105 } else { 106 uint32_t reg2; 107 uint32_t sda_pd_dis = 0; 108 uint32_t scl_pd_dis = 0; 109 110 reg2 = REG_GET_2(gpio.MASK_reg, 111 DC_GPIO_SDA_PD_DIS, &sda_pd_dis, 112 DC_GPIO_SCL_PD_DIS, &scl_pd_dis); 113 114 if (sda_pd_dis) { 115 REG_SET(gpio.MASK_reg, regval, 116 DC_GPIO_SDA_PD_DIS, 0); 117 118 if (config_data->type == 119 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 120 msleep(3); 121 } 122 123 if (!scl_pd_dis) { 124 REG_SET(gpio.MASK_reg, regval, 125 DC_GPIO_SCL_PD_DIS, 1); 126 127 if (config_data->type == 128 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 129 msleep(3); 130 } 131 } 132 133 if (aux_pad_mode) { 134 /* let pins to get de-asserted 135 * before setting pad to I2C mode */ 136 if (config_data->config.ddc.data_en_bit_present || 137 config_data->config.ddc.clock_en_bit_present) 138 /* [anaumov] in DAL2, there was 139 * dc_service_delay_in_microseconds(2000); */ 140 msleep(2); 141 142 /* set the I2C pad mode */ 143 /* read the register again, 144 * some bits may have been changed */ 145 REG_UPDATE(gpio.MASK_reg, 146 AUX_PAD1_MODE, 0); 147 } 148 149 return GPIO_RESULT_OK; 150 case GPIO_DDC_CONFIG_TYPE_MODE_AUX: 151 /* set the AUX pad mode */ 152 if (!aux_pad_mode) { 153 REG_SET(gpio.MASK_reg, regval, 154 AUX_PAD1_MODE, 1); 155 } 156 157 return GPIO_RESULT_OK; 158 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: 159 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 160 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 161 REG_UPDATE_3(ddc_setup, 162 DC_I2C_DDC1_ENABLE, 1, 163 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 164 DC_I2C_DDC1_EDID_DETECT_MODE, 0); 165 return GPIO_RESULT_OK; 166 } 167 break; 168 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT: 169 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 170 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 171 REG_UPDATE_3(ddc_setup, 172 DC_I2C_DDC1_ENABLE, 1, 173 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 174 DC_I2C_DDC1_EDID_DETECT_MODE, 1); 175 return GPIO_RESULT_OK; 176 } 177 break; 178 case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING: 179 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 180 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 181 REG_UPDATE_2(ddc_setup, 182 DC_I2C_DDC1_ENABLE, 0, 183 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0); 184 return GPIO_RESULT_OK; 185 } 186 break; 187 } 188 189 BREAK_TO_DEBUGGER(); 190 191 return GPIO_RESULT_NON_SPECIFIC_ERROR; 192 } 193 194 static const struct hw_gpio_pin_funcs funcs = { 195 .destroy = destroy, 196 .open = dal_hw_gpio_open, 197 .get_value = dal_hw_gpio_get_value, 198 .set_value = dal_hw_gpio_set_value, 199 .set_config = set_config, 200 .change_mode = dal_hw_gpio_change_mode, 201 .close = dal_hw_gpio_close, 202 }; 203 204 static void construct( 205 struct hw_ddc *ddc, 206 enum gpio_id id, 207 uint32_t en, 208 struct dc_context *ctx) 209 { 210 dal_hw_gpio_construct(&ddc->base, id, en, ctx); 211 ddc->base.base.funcs = &funcs; 212 } 213 214 struct hw_gpio_pin *dal_hw_ddc_create( 215 struct dc_context *ctx, 216 enum gpio_id id, 217 uint32_t en) 218 { 219 struct hw_ddc *pin; 220 221 if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 222 ASSERT_CRITICAL(false); 223 return NULL; 224 } 225 226 pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); 227 if (!pin) { 228 ASSERT_CRITICAL(false); 229 return NULL; 230 } 231 232 construct(pin, id, en, ctx); 233 return &pin->base.base; 234 } 235