1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "include/gpio_types.h" 29 #include "hw_gpio.h" 30 #include "hw_ddc.h" 31 32 #include "reg_helper.h" 33 #include "gpio_regs.h" 34 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 ddc->shifts->field_name, ddc->masks->field_name 39 40 #define CTX \ 41 ddc->base.base.ctx 42 #define REG(reg)\ 43 (ddc->regs->reg) 44 45 static void destruct( 46 struct hw_ddc *pin) 47 { 48 dal_hw_gpio_destruct(&pin->base); 49 } 50 51 static void destroy( 52 struct hw_gpio_pin **ptr) 53 { 54 struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr); 55 56 destruct(pin); 57 58 kfree(pin); 59 60 *ptr = NULL; 61 } 62 63 static enum gpio_result set_config( 64 struct hw_gpio_pin *ptr, 65 const struct gpio_config_data *config_data) 66 { 67 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); 68 struct hw_gpio *hw_gpio = NULL; 69 uint32_t regval; 70 uint32_t ddc_data_pd_en = 0; 71 uint32_t ddc_clk_pd_en = 0; 72 uint32_t aux_pad_mode = 0; 73 74 hw_gpio = &ddc->base; 75 76 if (hw_gpio == NULL) { 77 ASSERT_CRITICAL(false); 78 return GPIO_RESULT_NULL_HANDLE; 79 } 80 81 regval = REG_GET_3(gpio.MASK_reg, 82 DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en, 83 DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en, 84 AUX_PAD1_MODE, &aux_pad_mode); 85 86 switch (config_data->config.ddc.type) { 87 case GPIO_DDC_CONFIG_TYPE_MODE_I2C: 88 /* On plug-in, there is a transient level on the pad 89 * which must be discharged through the internal pull-down. 90 * Enable internal pull-down, 2.5msec discharge time 91 * is required for detection of AUX mode */ 92 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { 93 if (!ddc_data_pd_en || !ddc_clk_pd_en) { 94 95 REG_SET_2(gpio.MASK_reg, regval, 96 DC_GPIO_DDC1DATA_PD_EN, 1, 97 DC_GPIO_DDC1CLK_PD_EN, 1); 98 99 if (config_data->type == 100 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 101 msleep(3); 102 } 103 } else { 104 uint32_t reg2; 105 uint32_t sda_pd_dis = 0; 106 uint32_t scl_pd_dis = 0; 107 108 reg2 = REG_GET_2(gpio.MASK_reg, 109 DC_GPIO_SDA_PD_DIS, &sda_pd_dis, 110 DC_GPIO_SCL_PD_DIS, &scl_pd_dis); 111 112 if (sda_pd_dis) { 113 REG_SET(gpio.MASK_reg, regval, 114 DC_GPIO_SDA_PD_DIS, 0); 115 116 if (config_data->type == 117 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 118 msleep(3); 119 } 120 121 if (!scl_pd_dis) { 122 REG_SET(gpio.MASK_reg, regval, 123 DC_GPIO_SCL_PD_DIS, 1); 124 125 if (config_data->type == 126 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 127 msleep(3); 128 } 129 } 130 131 if (aux_pad_mode) { 132 /* let pins to get de-asserted 133 * before setting pad to I2C mode */ 134 if (config_data->config.ddc.data_en_bit_present || 135 config_data->config.ddc.clock_en_bit_present) 136 /* [anaumov] in DAL2, there was 137 * dc_service_delay_in_microseconds(2000); */ 138 msleep(2); 139 140 /* set the I2C pad mode */ 141 /* read the register again, 142 * some bits may have been changed */ 143 REG_UPDATE(gpio.MASK_reg, 144 AUX_PAD1_MODE, 0); 145 } 146 147 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 148 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 149 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); 150 } 151 //set DC_IO_aux_rxsel = 2'b01 152 if (ddc->regs->phy_aux_cntl != 0) { 153 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); 154 } 155 #endif 156 return GPIO_RESULT_OK; 157 case GPIO_DDC_CONFIG_TYPE_MODE_AUX: 158 /* set the AUX pad mode */ 159 if (!aux_pad_mode) { 160 REG_SET(gpio.MASK_reg, regval, 161 AUX_PAD1_MODE, 1); 162 } 163 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 164 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 165 REG_UPDATE(dc_gpio_aux_ctrl_5, 166 DDC_PAD_I2CMODE, 0); 167 } 168 #endif 169 170 return GPIO_RESULT_OK; 171 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: 172 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 173 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 174 REG_UPDATE_3(ddc_setup, 175 DC_I2C_DDC1_ENABLE, 1, 176 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 177 DC_I2C_DDC1_EDID_DETECT_MODE, 0); 178 return GPIO_RESULT_OK; 179 } 180 break; 181 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT: 182 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 183 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 184 REG_UPDATE_3(ddc_setup, 185 DC_I2C_DDC1_ENABLE, 1, 186 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 187 DC_I2C_DDC1_EDID_DETECT_MODE, 1); 188 return GPIO_RESULT_OK; 189 } 190 break; 191 case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING: 192 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 193 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 194 REG_UPDATE_2(ddc_setup, 195 DC_I2C_DDC1_ENABLE, 0, 196 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0); 197 return GPIO_RESULT_OK; 198 } 199 break; 200 } 201 202 BREAK_TO_DEBUGGER(); 203 204 return GPIO_RESULT_NON_SPECIFIC_ERROR; 205 } 206 207 static const struct hw_gpio_pin_funcs funcs = { 208 .destroy = destroy, 209 .open = dal_hw_gpio_open, 210 .get_value = dal_hw_gpio_get_value, 211 .set_value = dal_hw_gpio_set_value, 212 .set_config = set_config, 213 .change_mode = dal_hw_gpio_change_mode, 214 .close = dal_hw_gpio_close, 215 }; 216 217 static void construct( 218 struct hw_ddc *ddc, 219 enum gpio_id id, 220 uint32_t en, 221 struct dc_context *ctx) 222 { 223 dal_hw_gpio_construct(&ddc->base, id, en, ctx); 224 ddc->base.base.funcs = &funcs; 225 } 226 227 struct hw_gpio_pin *dal_hw_ddc_create( 228 struct dc_context *ctx, 229 enum gpio_id id, 230 uint32_t en) 231 { 232 struct hw_ddc *pin; 233 234 if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 235 ASSERT_CRITICAL(false); 236 return NULL; 237 } 238 239 pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); 240 if (!pin) { 241 ASSERT_CRITICAL(false); 242 return NULL; 243 } 244 245 construct(pin, id, en, ctx); 246 return &pin->base.base; 247 } 248