1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "include/gpio_interface.h" 29 #include "include/gpio_types.h" 30 #include "hw_gpio.h" 31 #include "hw_ddc.h" 32 33 #include "reg_helper.h" 34 #include "gpio_regs.h" 35 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 ddc->shifts->field_name, ddc->masks->field_name 40 41 #define CTX \ 42 ddc->base.base.ctx 43 #define REG(reg)\ 44 (ddc->regs->reg) 45 46 struct gpio; 47 48 static void dal_hw_ddc_destruct( 49 struct hw_ddc *pin) 50 { 51 dal_hw_gpio_destruct(&pin->base); 52 } 53 54 static void dal_hw_ddc_destroy( 55 struct hw_gpio_pin **ptr) 56 { 57 struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr); 58 59 dal_hw_ddc_destruct(pin); 60 61 kfree(pin); 62 63 *ptr = NULL; 64 } 65 66 static enum gpio_result set_config( 67 struct hw_gpio_pin *ptr, 68 const struct gpio_config_data *config_data) 69 { 70 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); 71 struct hw_gpio *hw_gpio = NULL; 72 uint32_t regval; 73 uint32_t ddc_data_pd_en = 0; 74 uint32_t ddc_clk_pd_en = 0; 75 uint32_t aux_pad_mode = 0; 76 77 hw_gpio = &ddc->base; 78 79 if (hw_gpio == NULL) { 80 ASSERT_CRITICAL(false); 81 return GPIO_RESULT_NULL_HANDLE; 82 } 83 84 regval = REG_GET_3(gpio.MASK_reg, 85 DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en, 86 DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en, 87 AUX_PAD1_MODE, &aux_pad_mode); 88 89 switch (config_data->config.ddc.type) { 90 case GPIO_DDC_CONFIG_TYPE_MODE_I2C: 91 /* On plug-in, there is a transient level on the pad 92 * which must be discharged through the internal pull-down. 93 * Enable internal pull-down, 2.5msec discharge time 94 * is required for detection of AUX mode */ 95 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { 96 if (!ddc_data_pd_en || !ddc_clk_pd_en) { 97 98 REG_SET_2(gpio.MASK_reg, regval, 99 DC_GPIO_DDC1DATA_PD_EN, 1, 100 DC_GPIO_DDC1CLK_PD_EN, 1); 101 102 if (config_data->type == 103 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 104 msleep(3); 105 } 106 } else { 107 uint32_t sda_pd_dis = 0; 108 uint32_t scl_pd_dis = 0; 109 110 REG_GET_2(gpio.MASK_reg, 111 DC_GPIO_SDA_PD_DIS, &sda_pd_dis, 112 DC_GPIO_SCL_PD_DIS, &scl_pd_dis); 113 114 if (sda_pd_dis) { 115 REG_SET(gpio.MASK_reg, regval, 116 DC_GPIO_SDA_PD_DIS, 0); 117 118 if (config_data->type == 119 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 120 msleep(3); 121 } 122 123 if (!scl_pd_dis) { 124 REG_SET(gpio.MASK_reg, regval, 125 DC_GPIO_SCL_PD_DIS, 1); 126 127 if (config_data->type == 128 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 129 msleep(3); 130 } 131 } 132 133 if (aux_pad_mode) { 134 /* let pins to get de-asserted 135 * before setting pad to I2C mode */ 136 if (config_data->config.ddc.data_en_bit_present || 137 config_data->config.ddc.clock_en_bit_present) 138 /* [anaumov] in DAL2, there was 139 * dc_service_delay_in_microseconds(2000); */ 140 msleep(2); 141 142 /* set the I2C pad mode */ 143 /* read the register again, 144 * some bits may have been changed */ 145 REG_UPDATE(gpio.MASK_reg, 146 AUX_PAD1_MODE, 0); 147 } 148 149 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 150 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); 151 } 152 //set DC_IO_aux_rxsel = 2'b01 153 if (ddc->regs->phy_aux_cntl != 0) { 154 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); 155 } 156 return GPIO_RESULT_OK; 157 case GPIO_DDC_CONFIG_TYPE_MODE_AUX: 158 /* set the AUX pad mode */ 159 if (!aux_pad_mode) { 160 REG_SET(gpio.MASK_reg, regval, 161 AUX_PAD1_MODE, 1); 162 } 163 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 164 REG_UPDATE(dc_gpio_aux_ctrl_5, 165 DDC_PAD_I2CMODE, 0); 166 } 167 168 return GPIO_RESULT_OK; 169 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: 170 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 171 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 172 REG_UPDATE_3(ddc_setup, 173 DC_I2C_DDC1_ENABLE, 1, 174 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 175 DC_I2C_DDC1_EDID_DETECT_MODE, 0); 176 return GPIO_RESULT_OK; 177 } 178 break; 179 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT: 180 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 181 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 182 REG_UPDATE_3(ddc_setup, 183 DC_I2C_DDC1_ENABLE, 1, 184 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 185 DC_I2C_DDC1_EDID_DETECT_MODE, 1); 186 return GPIO_RESULT_OK; 187 } 188 break; 189 case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING: 190 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 191 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 192 REG_UPDATE_2(ddc_setup, 193 DC_I2C_DDC1_ENABLE, 0, 194 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0); 195 return GPIO_RESULT_OK; 196 } 197 break; 198 } 199 200 BREAK_TO_DEBUGGER(); 201 202 return GPIO_RESULT_NON_SPECIFIC_ERROR; 203 } 204 205 static const struct hw_gpio_pin_funcs funcs = { 206 .destroy = dal_hw_ddc_destroy, 207 .open = dal_hw_gpio_open, 208 .get_value = dal_hw_gpio_get_value, 209 .set_value = dal_hw_gpio_set_value, 210 .set_config = set_config, 211 .change_mode = dal_hw_gpio_change_mode, 212 .close = dal_hw_gpio_close, 213 }; 214 215 static void dal_hw_ddc_construct( 216 struct hw_ddc *ddc, 217 enum gpio_id id, 218 uint32_t en, 219 struct dc_context *ctx) 220 { 221 dal_hw_gpio_construct(&ddc->base, id, en, ctx); 222 ddc->base.base.funcs = &funcs; 223 } 224 225 void dal_hw_ddc_init( 226 struct hw_ddc **hw_ddc, 227 struct dc_context *ctx, 228 enum gpio_id id, 229 uint32_t en) 230 { 231 if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 232 ASSERT_CRITICAL(false); 233 *hw_ddc = NULL; 234 } 235 236 *hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); 237 if (!*hw_ddc) { 238 ASSERT_CRITICAL(false); 239 return; 240 } 241 242 dal_hw_ddc_construct(*hw_ddc, id, en, ctx); 243 } 244 245 struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio) 246 { 247 struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio); 248 249 return &hw_ddc->base.base; 250 } 251