1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "include/gpio_types.h" 27 #include "../hw_factory.h" 28 29 30 #include "../hw_gpio.h" 31 #include "../hw_ddc.h" 32 #include "../hw_hpd.h" 33 #include "../hw_generic.h" 34 35 #include "hw_factory_dcn32.h" 36 37 #include "dcn/dcn_3_2_0_offset.h" 38 #include "dcn/dcn_3_2_0_sh_mask.h" 39 40 #include "reg_helper.h" 41 #include "../hpd_regs.h" 42 43 #define DCN_BASE__INST0_SEG2 0x000034C0 44 45 /* begin ********************* 46 * macros to expend register list macro defined in HW object header file */ 47 48 /* DCN */ 49 #define block HPD 50 #define reg_num 0 51 52 #undef BASE_INNER 53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 54 55 #define BASE(seg) BASE_INNER(seg) 56 57 58 59 #define REG(reg_name)\ 60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name 61 62 #define SF_HPD(reg_name, field_name, post_fix)\ 63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 64 65 #define REGI(reg_name, block, id)\ 66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 67 reg ## block ## id ## _ ## reg_name 68 69 #define SF(reg_name, field_name, post_fix)\ 70 .field_name = reg_name ## __ ## field_name ## post_fix 71 72 /* macros to expend register list macro defined in HW object header file 73 * end *********************/ 74 75 76 77 #define hpd_regs(id) \ 78 {\ 79 HPD_REG_LIST(id)\ 80 } 81 82 static const struct hpd_registers hpd_regs[] = { 83 hpd_regs(0), 84 hpd_regs(1), 85 hpd_regs(2), 86 hpd_regs(3), 87 hpd_regs(4), 88 }; 89 90 static const struct hpd_sh_mask hpd_shift = { 91 HPD_MASK_SH_LIST(__SHIFT) 92 }; 93 94 static const struct hpd_sh_mask hpd_mask = { 95 HPD_MASK_SH_LIST(_MASK) 96 }; 97 98 #include "../ddc_regs.h" 99 100 /* set field name */ 101 #define SF_DDC(reg_name, field_name, post_fix)\ 102 .field_name = reg_name ## __ ## field_name ## post_fix 103 104 static const struct ddc_registers ddc_data_regs_dcn[] = { 105 ddc_data_regs_dcn2(1), 106 ddc_data_regs_dcn2(2), 107 ddc_data_regs_dcn2(3), 108 ddc_data_regs_dcn2(4), 109 ddc_data_regs_dcn2(5), 110 { 111 DDC_GPIO_VGA_REG_LIST(DATA), 112 .ddc_setup = 0, 113 .phy_aux_cntl = 0, 114 .dc_gpio_aux_ctrl_5 = 0 115 } 116 }; 117 118 static const struct ddc_registers ddc_clk_regs_dcn[] = { 119 ddc_clk_regs_dcn2(1), 120 ddc_clk_regs_dcn2(2), 121 ddc_clk_regs_dcn2(3), 122 ddc_clk_regs_dcn2(4), 123 ddc_clk_regs_dcn2(5), 124 { 125 DDC_GPIO_VGA_REG_LIST(CLK), 126 .ddc_setup = 0, 127 .phy_aux_cntl = 0, 128 .dc_gpio_aux_ctrl_5 = 0 129 } 130 }; 131 132 static const struct ddc_sh_mask ddc_shift[] = { 133 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), 134 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), 135 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), 136 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), 137 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), 138 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) 139 }; 140 141 static const struct ddc_sh_mask ddc_mask[] = { 142 DDC_MASK_SH_LIST_DCN2(_MASK, 1), 143 DDC_MASK_SH_LIST_DCN2(_MASK, 2), 144 DDC_MASK_SH_LIST_DCN2(_MASK, 3), 145 DDC_MASK_SH_LIST_DCN2(_MASK, 4), 146 DDC_MASK_SH_LIST_DCN2(_MASK, 5), 147 DDC_MASK_SH_LIST_DCN2(_MASK, 6) 148 }; 149 150 #include "../generic_regs.h" 151 152 /* set field name */ 153 #define SF_GENERIC(reg_name, field_name, post_fix)\ 154 .field_name = reg_name ## __ ## field_name ## post_fix 155 156 #define generic_regs(id) \ 157 {\ 158 GENERIC_REG_LIST(id)\ 159 } 160 161 static const struct generic_registers generic_regs[] = { 162 generic_regs(A), 163 generic_regs(B), 164 }; 165 166 static const struct generic_sh_mask generic_shift[] = { 167 GENERIC_MASK_SH_LIST(__SHIFT, A), 168 GENERIC_MASK_SH_LIST(__SHIFT, B), 169 }; 170 171 static const struct generic_sh_mask generic_mask[] = { 172 GENERIC_MASK_SH_LIST(_MASK, A), 173 GENERIC_MASK_SH_LIST(_MASK, B), 174 }; 175 176 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) 177 { 178 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); 179 180 generic->regs = &generic_regs[en]; 181 generic->shifts = &generic_shift[en]; 182 generic->masks = &generic_mask[en]; 183 generic->base.regs = &generic_regs[en].gpio; 184 } 185 186 static void define_ddc_registers( 187 struct hw_gpio_pin *pin, 188 uint32_t en) 189 { 190 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); 191 192 switch (pin->id) { 193 case GPIO_ID_DDC_DATA: 194 ddc->regs = &ddc_data_regs_dcn[en]; 195 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; 196 break; 197 case GPIO_ID_DDC_CLOCK: 198 ddc->regs = &ddc_clk_regs_dcn[en]; 199 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; 200 break; 201 default: 202 ASSERT_CRITICAL(false); 203 return; 204 } 205 206 ddc->shifts = &ddc_shift[en]; 207 ddc->masks = &ddc_mask[en]; 208 209 } 210 211 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) 212 { 213 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); 214 215 hpd->regs = &hpd_regs[en]; 216 hpd->shifts = &hpd_shift; 217 hpd->masks = &hpd_mask; 218 hpd->base.regs = &hpd_regs[en].gpio; 219 } 220 221 222 /* fucntion table */ 223 static const struct hw_factory_funcs funcs = { 224 .init_ddc_data = dal_hw_ddc_init, 225 .init_generic = dal_hw_generic_init, 226 .init_hpd = dal_hw_hpd_init, 227 .get_ddc_pin = dal_hw_ddc_get_pin, 228 .get_hpd_pin = dal_hw_hpd_get_pin, 229 .get_generic_pin = dal_hw_generic_get_pin, 230 .define_hpd_registers = define_hpd_registers, 231 .define_ddc_registers = define_ddc_registers, 232 .define_generic_registers = define_generic_registers 233 }; 234 /* 235 * dal_hw_factory_dcn32_init 236 * 237 * @brief 238 * Initialize HW factory function pointers and pin info 239 * 240 * @param 241 * struct hw_factory *factory - [out] struct of function pointers 242 */ 243 void dal_hw_factory_dcn32_init(struct hw_factory *factory) 244 { 245 factory->number_of_pins[GPIO_ID_DDC_DATA] = 6; 246 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6; 247 factory->number_of_pins[GPIO_ID_GENERIC] = 4; 248 factory->number_of_pins[GPIO_ID_HPD] = 5; 249 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; 250 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; 251 factory->number_of_pins[GPIO_ID_SYNC] = 0; 252 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ 253 254 factory->funcs = &funcs; 255 } 256