1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* 27 * Pre-requisites: headers required by header of this unit 28 */ 29 #include "hw_translate_dcn21.h" 30 31 #include "dm_services.h" 32 #include "include/gpio_types.h" 33 #include "../hw_translate.h" 34 35 #include "dcn/dcn_2_1_0_offset.h" 36 #include "dcn/dcn_2_1_0_sh_mask.h" 37 #include "renoir_ip_offset.h" 38 39 40 41 42 /* begin ********************* 43 * macros to expend register list macro defined in HW object header file */ 44 45 /* DCN */ 46 #define block HPD 47 #define reg_num 0 48 49 #undef BASE_INNER 50 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 51 52 #define BASE(seg) BASE_INNER(seg) 53 54 #undef REG 55 #define REG(reg_name)\ 56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 57 #define SF_HPD(reg_name, field_name, post_fix)\ 58 .field_name = reg_name ## __ ## field_name ## post_fix 59 60 /* macros to expend register list macro defined in HW object header file 61 * end *********************/ 62 63 64 static bool offset_to_id( 65 uint32_t offset, 66 uint32_t mask, 67 enum gpio_id *id, 68 uint32_t *en) 69 { 70 switch (offset) { 71 /* GENERIC */ 72 case REG(DC_GPIO_GENERIC_A): 73 *id = GPIO_ID_GENERIC; 74 switch (mask) { 75 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: 76 *en = GPIO_GENERIC_A; 77 return true; 78 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: 79 *en = GPIO_GENERIC_B; 80 return true; 81 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: 82 *en = GPIO_GENERIC_C; 83 return true; 84 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: 85 *en = GPIO_GENERIC_D; 86 return true; 87 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: 88 *en = GPIO_GENERIC_E; 89 return true; 90 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: 91 *en = GPIO_GENERIC_F; 92 return true; 93 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: 94 *en = GPIO_GENERIC_G; 95 return true; 96 default: 97 ASSERT_CRITICAL(false); 98 #ifdef PALLADIUM_SUPPORTED 99 *en = GPIO_DDC_LINE_DDC1; 100 return true; 101 #endif 102 return false; 103 } 104 break; 105 /* HPD */ 106 case REG(DC_GPIO_HPD_A): 107 *id = GPIO_ID_HPD; 108 switch (mask) { 109 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: 110 *en = GPIO_HPD_1; 111 return true; 112 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: 113 *en = GPIO_HPD_2; 114 return true; 115 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: 116 *en = GPIO_HPD_3; 117 return true; 118 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: 119 *en = GPIO_HPD_4; 120 return true; 121 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: 122 *en = GPIO_HPD_5; 123 return true; 124 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: 125 *en = GPIO_HPD_6; 126 return true; 127 default: 128 ASSERT_CRITICAL(false); 129 return false; 130 } 131 break; 132 /* REG(DC_GPIO_GENLK_MASK */ 133 case REG(DC_GPIO_GENLK_A): 134 *id = GPIO_ID_GSL; 135 switch (mask) { 136 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: 137 *en = GPIO_GSL_GENLOCK_CLOCK; 138 return true; 139 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: 140 *en = GPIO_GSL_GENLOCK_VSYNC; 141 return true; 142 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: 143 *en = GPIO_GSL_SWAPLOCK_A; 144 return true; 145 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: 146 *en = GPIO_GSL_SWAPLOCK_B; 147 return true; 148 default: 149 ASSERT_CRITICAL(false); 150 return false; 151 } 152 break; 153 /* DDC */ 154 /* we don't care about the GPIO_ID for DDC 155 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK 156 * directly in the create method */ 157 case REG(DC_GPIO_DDC1_A): 158 *en = GPIO_DDC_LINE_DDC1; 159 return true; 160 case REG(DC_GPIO_DDC2_A): 161 *en = GPIO_DDC_LINE_DDC2; 162 return true; 163 case REG(DC_GPIO_DDC3_A): 164 *en = GPIO_DDC_LINE_DDC3; 165 return true; 166 case REG(DC_GPIO_DDC4_A): 167 *en = GPIO_DDC_LINE_DDC4; 168 return true; 169 case REG(DC_GPIO_DDC5_A): 170 *en = GPIO_DDC_LINE_DDC5; 171 return true; 172 case REG(DC_GPIO_DDCVGA_A): 173 *en = GPIO_DDC_LINE_DDC_VGA; 174 return true; 175 176 // case REG(DC_GPIO_I2CPAD_A): not exit 177 // case REG(DC_GPIO_PWRSEQ_A): 178 // case REG(DC_GPIO_PAD_STRENGTH_1): 179 // case REG(DC_GPIO_PAD_STRENGTH_2): 180 // case REG(DC_GPIO_DEBUG): 181 /* UNEXPECTED */ 182 default: 183 // case REG(DC_GPIO_SYNCA_A): not exist 184 #ifdef PALLADIUM_SUPPORTED 185 *id = GPIO_ID_HPD; 186 *en = GPIO_DDC_LINE_DDC1; 187 return true; 188 #endif 189 ASSERT_CRITICAL(false); 190 return false; 191 } 192 } 193 194 static bool id_to_offset( 195 enum gpio_id id, 196 uint32_t en, 197 struct gpio_pin_info *info) 198 { 199 bool result = true; 200 201 switch (id) { 202 case GPIO_ID_DDC_DATA: 203 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK; 204 switch (en) { 205 case GPIO_DDC_LINE_DDC1: 206 info->offset = REG(DC_GPIO_DDC1_A); 207 break; 208 case GPIO_DDC_LINE_DDC2: 209 info->offset = REG(DC_GPIO_DDC2_A); 210 break; 211 case GPIO_DDC_LINE_DDC3: 212 info->offset = REG(DC_GPIO_DDC3_A); 213 break; 214 case GPIO_DDC_LINE_DDC4: 215 info->offset = REG(DC_GPIO_DDC4_A); 216 break; 217 case GPIO_DDC_LINE_DDC5: 218 info->offset = REG(DC_GPIO_DDC5_A); 219 break; 220 case GPIO_DDC_LINE_DDC_VGA: 221 info->offset = REG(DC_GPIO_DDCVGA_A); 222 break; 223 case GPIO_DDC_LINE_I2C_PAD: 224 default: 225 ASSERT_CRITICAL(false); 226 result = false; 227 } 228 break; 229 case GPIO_ID_DDC_CLOCK: 230 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK; 231 switch (en) { 232 case GPIO_DDC_LINE_DDC1: 233 info->offset = REG(DC_GPIO_DDC1_A); 234 break; 235 case GPIO_DDC_LINE_DDC2: 236 info->offset = REG(DC_GPIO_DDC2_A); 237 break; 238 case GPIO_DDC_LINE_DDC3: 239 info->offset = REG(DC_GPIO_DDC3_A); 240 break; 241 case GPIO_DDC_LINE_DDC4: 242 info->offset = REG(DC_GPIO_DDC4_A); 243 break; 244 case GPIO_DDC_LINE_DDC5: 245 info->offset = REG(DC_GPIO_DDC5_A); 246 break; 247 case GPIO_DDC_LINE_DDC_VGA: 248 info->offset = REG(DC_GPIO_DDCVGA_A); 249 break; 250 case GPIO_DDC_LINE_I2C_PAD: 251 default: 252 ASSERT_CRITICAL(false); 253 result = false; 254 } 255 break; 256 case GPIO_ID_GENERIC: 257 info->offset = REG(DC_GPIO_GENERIC_A); 258 switch (en) { 259 case GPIO_GENERIC_A: 260 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 261 break; 262 case GPIO_GENERIC_B: 263 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 264 break; 265 case GPIO_GENERIC_C: 266 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 267 break; 268 case GPIO_GENERIC_D: 269 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; 270 break; 271 case GPIO_GENERIC_E: 272 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; 273 break; 274 case GPIO_GENERIC_F: 275 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; 276 break; 277 case GPIO_GENERIC_G: 278 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; 279 break; 280 default: 281 ASSERT_CRITICAL(false); 282 result = false; 283 } 284 break; 285 case GPIO_ID_HPD: 286 info->offset = REG(DC_GPIO_HPD_A); 287 switch (en) { 288 case GPIO_HPD_1: 289 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; 290 break; 291 case GPIO_HPD_2: 292 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; 293 break; 294 case GPIO_HPD_3: 295 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; 296 break; 297 case GPIO_HPD_4: 298 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; 299 break; 300 case GPIO_HPD_5: 301 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; 302 break; 303 case GPIO_HPD_6: 304 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; 305 break; 306 default: 307 ASSERT_CRITICAL(false); 308 #ifdef PALLADIUM_SUPPORTED 309 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; 310 result = true; 311 #endif 312 result = false; 313 } 314 break; 315 case GPIO_ID_GSL: 316 switch (en) { 317 case GPIO_GSL_GENLOCK_CLOCK: 318 /*not implmented*/ 319 ASSERT_CRITICAL(false); 320 result = false; 321 break; 322 case GPIO_GSL_GENLOCK_VSYNC: 323 /*not implmented*/ 324 ASSERT_CRITICAL(false); 325 result = false; 326 break; 327 case GPIO_GSL_SWAPLOCK_A: 328 /*not implmented*/ 329 ASSERT_CRITICAL(false); 330 result = false; 331 break; 332 case GPIO_GSL_SWAPLOCK_B: 333 /*not implmented*/ 334 ASSERT_CRITICAL(false); 335 result = false; 336 337 break; 338 default: 339 ASSERT_CRITICAL(false); 340 result = false; 341 } 342 break; 343 case GPIO_ID_SYNC: 344 case GPIO_ID_VIP_PAD: 345 default: 346 ASSERT_CRITICAL(false); 347 result = false; 348 } 349 350 if (result) { 351 info->offset_y = info->offset + 2; 352 info->offset_en = info->offset + 1; 353 info->offset_mask = info->offset - 1; 354 355 info->mask_y = info->mask; 356 info->mask_en = info->mask; 357 info->mask_mask = info->mask; 358 } 359 360 return result; 361 } 362 363 /* function table */ 364 static const struct hw_translate_funcs funcs = { 365 .offset_to_id = offset_to_id, 366 .id_to_offset = id_to_offset, 367 }; 368 369 /* 370 * dal_hw_translate_dcn10_init 371 * 372 * @brief 373 * Initialize Hw translate function pointers. 374 * 375 * @param 376 * struct hw_translate *tr - [out] struct of function pointers 377 * 378 */ 379 void dal_hw_translate_dcn21_init(struct hw_translate *tr) 380 { 381 tr->funcs = &funcs; 382 } 383 384