1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef __DML2_DISPLAY_MODE_VBA_H__ 28 #define __DML2_DISPLAY_MODE_VBA_H__ 29 30 struct display_mode_lib; 31 32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib); 33 34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) 35 36 dml_get_attr_decl(clk_dcf_deepsleep); 37 dml_get_attr_decl(wm_urgent); 38 dml_get_attr_decl(wm_memory_trip); 39 dml_get_attr_decl(wm_writeback_urgent); 40 dml_get_attr_decl(wm_stutter_exit); 41 dml_get_attr_decl(wm_stutter_enter_exit); 42 dml_get_attr_decl(wm_z8_stutter_exit); 43 dml_get_attr_decl(wm_z8_stutter_enter_exit); 44 dml_get_attr_decl(stutter_efficiency_z8); 45 dml_get_attr_decl(stutter_num_bursts_z8); 46 dml_get_attr_decl(wm_dram_clock_change); 47 dml_get_attr_decl(wm_writeback_dram_clock_change); 48 dml_get_attr_decl(stutter_efficiency_no_vblank); 49 dml_get_attr_decl(stutter_efficiency); 50 dml_get_attr_decl(stutter_period); 51 dml_get_attr_decl(urgent_latency); 52 dml_get_attr_decl(urgent_extra_latency); 53 dml_get_attr_decl(nonurgent_latency); 54 dml_get_attr_decl(dram_clock_change_latency); 55 dml_get_attr_decl(dispclk_calculated); 56 dml_get_attr_decl(total_data_read_bw); 57 dml_get_attr_decl(return_bw); 58 dml_get_attr_decl(tcalc); 59 dml_get_attr_decl(fraction_of_urgent_bandwidth); 60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); 61 dml_get_attr_decl(cstate_max_cap_mode); 62 dml_get_attr_decl(comp_buffer_size_kbytes); 63 dml_get_attr_decl(pixel_chunk_size_in_kbyte); 64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte); 65 dml_get_attr_decl(meta_chunk_size_in_kbyte); 66 dml_get_attr_decl(min_pixel_chunk_size_in_byte); 67 dml_get_attr_decl(min_meta_chunk_size_in_byte); 68 dml_get_attr_decl(fclk_watermark); 69 dml_get_attr_decl(usr_retraining_watermark); 70 dml_get_attr_decl(comp_buffer_reserved_space_kbytes); 71 dml_get_attr_decl(comp_buffer_reserved_space_64bytes); 72 dml_get_attr_decl(comp_buffer_reserved_space_zs); 73 dml_get_attr_decl(unbounded_request_enabled); 74 75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) 76 77 dml_get_pipe_attr_decl(dsc_delay); 78 dml_get_pipe_attr_decl(dppclk_calculated); 79 dml_get_pipe_attr_decl(dscclk_calculated); 80 dml_get_pipe_attr_decl(min_ttu_vblank); 81 dml_get_pipe_attr_decl(min_ttu_vblank_in_us); 82 dml_get_pipe_attr_decl(vratio_prefetch_l); 83 dml_get_pipe_attr_decl(vratio_prefetch_c); 84 dml_get_pipe_attr_decl(dst_x_after_scaler); 85 dml_get_pipe_attr_decl(dst_y_after_scaler); 86 dml_get_pipe_attr_decl(dst_y_per_vm_vblank); 87 dml_get_pipe_attr_decl(dst_y_per_row_vblank); 88 dml_get_pipe_attr_decl(dst_y_prefetch); 89 dml_get_pipe_attr_decl(dst_y_per_vm_flip); 90 dml_get_pipe_attr_decl(dst_y_per_row_flip); 91 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l); 92 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c); 93 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l); 94 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c); 95 dml_get_pipe_attr_decl(dpte_row_height_linear_c); 96 dml_get_pipe_attr_decl(swath_height_l); 97 dml_get_pipe_attr_decl(swath_height_c); 98 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes); 99 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes); 100 dml_get_pipe_attr_decl(dpte_group_size_in_bytes); 101 dml_get_pipe_attr_decl(vm_group_size_in_bytes); 102 dml_get_pipe_attr_decl(det_buffer_size_kbytes); 103 dml_get_pipe_attr_decl(dpte_row_height_linear_l); 104 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us); 105 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us); 106 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us); 107 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us); 108 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us); 109 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us); 110 dml_get_pipe_attr_decl(pte_buffer_mode); 111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); 112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); 113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); 114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip); 115 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us); 116 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us); 117 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us); 118 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us); 119 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us); 120 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us); 121 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us); 122 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us); 123 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us); 124 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us); 125 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us); 126 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us); 127 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us); 128 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us); 129 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us); 130 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us); 131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us); 132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us); 133 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us); 134 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us); 135 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us); 136 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us); 137 138 dml_get_pipe_attr_decl(vstartup); 139 dml_get_pipe_attr_decl(vupdate_offset); 140 dml_get_pipe_attr_decl(vupdate_width); 141 dml_get_pipe_attr_decl(vready_offset); 142 dml_get_pipe_attr_decl(vready_at_or_after_vsync); 143 dml_get_pipe_attr_decl(min_dst_y_next_start); 144 dml_get_pipe_attr_decl(vstartup_calculated); 145 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall); 146 147 double get_total_immediate_flip_bytes( 148 struct display_mode_lib *mode_lib, 149 const display_e2e_pipe_params_st *pipes, 150 unsigned int num_pipes); 151 double get_total_immediate_flip_bw( 152 struct display_mode_lib *mode_lib, 153 const display_e2e_pipe_params_st *pipes, 154 unsigned int num_pipes); 155 double get_total_prefetch_bw( 156 struct display_mode_lib *mode_lib, 157 const display_e2e_pipe_params_st *pipes, 158 unsigned int num_pipes); 159 unsigned int dml_get_voltage_level( 160 struct display_mode_lib *mode_lib, 161 const display_e2e_pipe_params_st *pipes, 162 unsigned int num_pipes); 163 164 unsigned int get_total_surface_size_in_mall_bytes( 165 struct display_mode_lib *mode_lib, 166 const display_e2e_pipe_params_st *pipes, 167 unsigned int num_pipes); 168 169 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, 170 const display_e2e_pipe_params_st *pipes, 171 unsigned int num_pipes, 172 unsigned int pipe_idx); 173 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); 174 175 void Calculate256BBlockSizes( 176 enum source_format_class SourcePixelFormat, 177 enum dm_swizzle_mode SurfaceTiling, 178 unsigned int BytePerPixelY, 179 unsigned int BytePerPixelC, 180 unsigned int *BlockHeight256BytesY, 181 unsigned int *BlockHeight256BytesC, 182 unsigned int *BlockWidth256BytesY, 183 unsigned int *BlockWidth256BytesC); 184 185 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation { 186 unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX]; 187 double dummy_single_array[2][DC__NUM_DPP__MAX]; 188 unsigned int dummy_long_array[2][DC__NUM_DPP__MAX]; 189 double dummy_double_array[2][DC__NUM_DPP__MAX]; 190 bool dummy_boolean_array[DC__NUM_DPP__MAX]; 191 bool dummy_boolean; 192 bool dummy_boolean2; 193 enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX]; 194 DmlPipe SurfaceParameters[DC__NUM_DPP__MAX]; 195 bool dummy_boolean_array2[2][DC__NUM_DPP__MAX]; 196 unsigned int ReorderBytes; 197 unsigned int VMDataOnlyReturnBW; 198 double HostVMInefficiencyFactor; 199 }; 200 201 struct dml32_ModeSupportAndSystemConfigurationFull { 202 unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX]; 203 double dummy_double_array[2][DC__NUM_DPP__MAX]; 204 DmlPipe SurfParameters[DC__NUM_DPP__MAX]; 205 double dummy_single[5]; 206 double dummy_single2[5]; 207 SOCParametersList mSOCParameters; 208 unsigned int MaximumSwathWidthSupportLuma; 209 unsigned int MaximumSwathWidthSupportChroma; 210 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 211 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 212 double MaxTotalVActiveRDBandwidth; 213 bool dummy_boolean_array[2][DC__NUM_DPP__MAX]; 214 }; 215 216 struct dummy_vars { 217 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation 218 DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation; 219 struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull; 220 }; 221 222 struct vba_vars_st { 223 ip_params_st ip; 224 soc_bounding_box_st soc; 225 226 int maxMpcComb; 227 bool UseMaximumVStartup; 228 229 double WritebackDISPCLK; 230 double DPPCLKUsingSingleDPPLuma; 231 double DPPCLKUsingSingleDPPChroma; 232 double DISPCLKWithRamping; 233 double DISPCLKWithoutRamping; 234 double GlobalDPPCLK; 235 double DISPCLKWithRampingRoundedToDFSGranularity; 236 double DISPCLKWithoutRampingRoundedToDFSGranularity; 237 double MaxDispclkRoundedToDFSGranularity; 238 bool DCCEnabledAnyPlane; 239 double ReturnBandwidthToDCN; 240 unsigned int TotalActiveDPP; 241 unsigned int TotalDCCActiveDPP; 242 double UrgentRoundTripAndOutOfOrderLatency; 243 double StutterPeriod; 244 double FrameTimeForMinFullDETBufferingTime; 245 double AverageReadBandwidth; 246 double TotalRowReadBandwidth; 247 double PartOfBurstThatFitsInROB; 248 double StutterBurstTime; 249 unsigned int NextPrefetchMode; 250 double NextMaxVStartup; 251 double VBlankTime; 252 double SmallestVBlank; 253 enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only 254 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; 255 double EffectiveDETPlusLBLinesLuma; 256 double EffectiveDETPlusLBLinesChroma; 257 double UrgentLatencySupportUsLuma; 258 double UrgentLatencySupportUsChroma; 259 unsigned int DSCFormatFactor; 260 261 bool DummyPStateCheck; 262 bool DRAMClockChangeSupportsVActive; 263 bool PrefetchModeSupported; 264 bool PrefetchAndImmediateFlipSupported; 265 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only 266 double XFCRemoteSurfaceFlipDelay; 267 double TInitXFill; 268 double TslvChk; 269 double SrcActiveDrainRate; 270 bool ImmediateFlipSupported; 271 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only 272 273 bool PrefetchERROR; 274 275 unsigned int VStartupLines; 276 unsigned int ActiveDPPs; 277 unsigned int LBLatencyHidingSourceLinesY; 278 unsigned int LBLatencyHidingSourceLinesC; 279 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; 280 double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only 281 double MinActiveDRAMClockChangeMargin; 282 double InitFillLevel; 283 double FinalFillMargin; 284 double FinalFillLevel; 285 double RemainingFillLevel; 286 double TFinalxFill; 287 288 // 289 // SOC Bounding Box Parameters 290 // 291 double SRExitTime; 292 double SREnterPlusExitTime; 293 double UrgentLatencyPixelDataOnly; 294 double UrgentLatencyPixelMixedWithVMData; 295 double UrgentLatencyVMDataOnly; 296 double UrgentLatency; // max of the above three 297 double USRRetrainingLatency; 298 double SMNLatency; 299 double FCLKChangeLatency; 300 unsigned int MALLAllocatedForDCNFinal; 301 double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation; 302 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE; 303 double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE; 304 double WritebackLatency; 305 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support 306 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support 307 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support 308 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support 309 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support 310 double NumberOfChannels; 311 double DRAMChannelWidth; 312 double FabricDatapathToDCNDataReturn; 313 double ReturnBusWidth; 314 double Downspreading; 315 double DISPCLKDPPCLKDSCCLKDownSpreading; 316 double DISPCLKDPPCLKVCOSpeed; 317 double RoundTripPingLatencyCycles; 318 double UrgentOutOfOrderReturnPerChannel; 319 double UrgentOutOfOrderReturnPerChannelPixelDataOnly; 320 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData; 321 double UrgentOutOfOrderReturnPerChannelVMDataOnly; 322 unsigned int VMMPageSize; 323 double DRAMClockChangeLatency; 324 double XFCBusTransportTime; 325 bool UseUrgentBurstBandwidth; 326 double XFCXBUFLatencyTolerance; 327 328 // 329 // IP Parameters 330 // 331 unsigned int ROBBufferSizeInKByte; 332 unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX]; 333 double DETBufferSizeInTime; 334 unsigned int DPPOutputBufferPixels; 335 unsigned int OPPOutputBufferLines; 336 unsigned int PixelChunkSizeInKByte; 337 double ReturnBW; 338 bool GPUVMEnable; 339 bool HostVMEnable; 340 unsigned int GPUVMMaxPageTableLevels; 341 unsigned int HostVMMaxPageTableLevels; 342 unsigned int HostVMCachedPageTableLevels; 343 unsigned int OverrideGPUVMPageTableLevels; 344 unsigned int OverrideHostVMPageTableLevels; 345 unsigned int MetaChunkSize; 346 unsigned int MinMetaChunkSizeBytes; 347 unsigned int WritebackChunkSize; 348 bool ODMCapability; 349 unsigned int NumberOfDSC; 350 unsigned int LineBufferSize; 351 unsigned int MaxLineBufferLines; 352 unsigned int WritebackInterfaceLumaBufferSize; 353 unsigned int WritebackInterfaceChromaBufferSize; 354 unsigned int WritebackChromaLineBufferWidth; 355 enum writeback_config WritebackConfiguration; 356 double MaxDCHUBToPSCLThroughput; 357 double MaxPSCLToLBThroughput; 358 unsigned int PTEBufferSizeInRequestsLuma; 359 unsigned int PTEBufferSizeInRequestsChroma; 360 double DISPCLKRampingMargin; 361 unsigned int MaxInterDCNTileRepeaters; 362 bool XFCSupported; 363 double XFCSlvChunkSize; 364 double XFCFillBWOverhead; 365 double XFCFillConstant; 366 double XFCTSlvVupdateOffset; 367 double XFCTSlvVupdateWidth; 368 double XFCTSlvVreadyOffset; 369 double DPPCLKDelaySubtotal; 370 double DPPCLKDelaySCL; 371 double DPPCLKDelaySCLLBOnly; 372 double DPPCLKDelayCNVCFormater; 373 double DPPCLKDelayCNVCCursor; 374 double DISPCLKDelaySubtotal; 375 bool ProgressiveToInterlaceUnitInOPP; 376 unsigned int CompressedBufferSegmentSizeInkByteFinal; 377 unsigned int CompbufReservedSpace64B; 378 unsigned int CompbufReservedSpaceZs; 379 unsigned int LineBufferSizeFinal; 380 unsigned int MaximumPixelsPerLinePerDSCUnit; 381 unsigned int AlphaPixelChunkSizeInKByte; 382 double MinPixelChunkSizeBytes; 383 unsigned int DCCMetaBufferSizeBytes; 384 // Pipe/Plane Parameters 385 int VoltageLevel; 386 double FabricClock; 387 double DRAMSpeed; 388 double DISPCLK; 389 double SOCCLK; 390 double DCFCLK; 391 unsigned int MaxTotalDETInKByte; 392 unsigned int MinCompressedBufferSizeInKByte; 393 unsigned int NumberOfActiveSurfaces; 394 bool ViewportStationary[DC__NUM_DPP__MAX]; 395 unsigned int RefreshRate[DC__NUM_DPP__MAX]; 396 double OutputBPP[DC__NUM_DPP__MAX]; 397 unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX]; 398 bool SynchronizeTimingsFinal; 399 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 400 bool ForceOneRowForFrame[DC__NUM_DPP__MAX]; 401 unsigned int ViewportXStartY[DC__NUM_DPP__MAX]; 402 unsigned int ViewportXStartC[DC__NUM_DPP__MAX]; 403 enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX]; 404 bool DRRDisplay[DC__NUM_DPP__MAX]; 405 bool PteBufferMode[DC__NUM_DPP__MAX]; 406 enum dm_output_type OutputType[DC__NUM_DPP__MAX]; 407 enum dm_output_rate OutputRate[DC__NUM_DPP__MAX]; 408 409 unsigned int NumberOfActivePlanes; 410 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; 411 unsigned int ViewportWidth[DC__NUM_DPP__MAX]; 412 unsigned int ViewportHeight[DC__NUM_DPP__MAX]; 413 unsigned int ViewportYStartY[DC__NUM_DPP__MAX]; 414 unsigned int ViewportYStartC[DC__NUM_DPP__MAX]; 415 unsigned int PitchY[DC__NUM_DPP__MAX]; 416 unsigned int PitchC[DC__NUM_DPP__MAX]; 417 double HRatio[DC__NUM_DPP__MAX]; 418 double VRatio[DC__NUM_DPP__MAX]; 419 unsigned int htaps[DC__NUM_DPP__MAX]; 420 unsigned int vtaps[DC__NUM_DPP__MAX]; 421 unsigned int HTAPsChroma[DC__NUM_DPP__MAX]; 422 unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; 423 unsigned int HTotal[DC__NUM_DPP__MAX]; 424 unsigned int VTotal[DC__NUM_DPP__MAX]; 425 unsigned int VTotal_Max[DC__NUM_DPP__MAX]; 426 unsigned int VTotal_Min[DC__NUM_DPP__MAX]; 427 int DPPPerPlane[DC__NUM_DPP__MAX]; 428 double PixelClock[DC__NUM_DPP__MAX]; 429 double PixelClockBackEnd[DC__NUM_DPP__MAX]; 430 bool DCCEnable[DC__NUM_DPP__MAX]; 431 bool FECEnable[DC__NUM_DPP__MAX]; 432 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; 433 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; 434 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; 435 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX]; 436 bool WritebackEnable[DC__NUM_DPP__MAX]; 437 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX]; 438 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; 439 double WritebackDestinationHeight[DC__NUM_DPP__MAX]; 440 double WritebackSourceHeight[DC__NUM_DPP__MAX]; 441 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX]; 442 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX]; 443 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX]; 444 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX]; 445 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX]; 446 double WritebackHRatio[DC__NUM_DPP__MAX]; 447 double WritebackVRatio[DC__NUM_DPP__MAX]; 448 unsigned int HActive[DC__NUM_DPP__MAX]; 449 unsigned int VActive[DC__NUM_DPP__MAX]; 450 bool Interlace[DC__NUM_DPP__MAX]; 451 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; 452 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; 453 bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; 454 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; 455 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; 456 double DCCRate[DC__NUM_DPP__MAX]; 457 double AverageDCCCompressionRate; 458 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX]; 459 double OutputBpp[DC__NUM_DPP__MAX]; 460 bool DSCEnabled[DC__NUM_DPP__MAX]; 461 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 462 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 463 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 464 bool skip_dio_check[DC__NUM_DPP__MAX]; 465 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 466 bool SynchronizedVBlank; 467 unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; 468 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 469 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 470 bool XFCEnabled[DC__NUM_DPP__MAX]; 471 bool ScalerEnabled[DC__NUM_DPP__MAX]; 472 unsigned int VBlankNom[DC__NUM_DPP__MAX]; 473 bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment; 474 475 // Intermediates/Informational 476 bool ImmediateFlipSupport; 477 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX]; 478 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX]; 479 unsigned int SwathHeightY[DC__NUM_DPP__MAX]; 480 unsigned int SwathHeightC[DC__NUM_DPP__MAX]; 481 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; 482 double LastPixelOfLineExtraWatermark; 483 double TotalDataReadBandwidth; 484 unsigned int TotalActiveWriteback; 485 unsigned int EffectiveLBLatencyHidingSourceLinesLuma; 486 unsigned int EffectiveLBLatencyHidingSourceLinesChroma; 487 double BandwidthAvailableForImmediateFlip; 488 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2]; 489 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2]; 490 unsigned int MinPrefetchMode; 491 unsigned int MaxPrefetchMode; 492 bool AnyLinesForVMOrRowTooLarge; 493 double MaxVStartup; 494 bool IgnoreViewportPositioning; 495 bool ErrorResult[DC__NUM_DPP__MAX]; 496 // 497 // Calculated dml_ml->vba.Outputs 498 // 499 double DCFCLKDeepSleep; 500 double UrgentWatermark; 501 double UrgentExtraLatency; 502 double WritebackUrgentWatermark; 503 double StutterExitWatermark; 504 double StutterEnterPlusExitWatermark; 505 double DRAMClockChangeWatermark; 506 double WritebackDRAMClockChangeWatermark; 507 double StutterEfficiency; 508 double StutterEfficiencyNotIncludingVBlank; 509 double NonUrgentLatencyTolerance; 510 double MinActiveDRAMClockChangeLatencySupported; 511 double Z8StutterEfficiencyBestCase; 512 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 513 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 514 double StutterPeriodBestCase; 515 Watermarks Watermark; 516 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 517 unsigned int CompBufReservedSpaceKBytes; 518 unsigned int CompBufReservedSpace64B; 519 unsigned int CompBufReservedSpaceZs; 520 bool CompBufReservedSpaceNeedAdjustment; 521 522 // These are the clocks calcuated by the library but they are not actually 523 // used explicitly. They are fetched by tests and then possibly used. The 524 // ultimate values to use are the ones specified by the parameters to DML 525 double DISPCLK_calculated; 526 double DPPCLK_calculated[DC__NUM_DPP__MAX]; 527 528 bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX]; 529 530 bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX]; 531 bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX]; 532 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; 533 double VUpdateWidthPix[DC__NUM_DPP__MAX]; 534 double VReadyOffsetPix[DC__NUM_DPP__MAX]; 535 536 unsigned int TotImmediateFlipBytes; 537 double TCalc; 538 539 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX]; 540 unsigned int cache_num_pipes; 541 unsigned int pipe_plane[DC__NUM_DPP__MAX]; 542 543 /* vba mode support */ 544 /*inputs*/ 545 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp; 546 double MaxHSCLRatio; 547 double MaxVSCLRatio; 548 unsigned int MaxNumWriteback; 549 bool WritebackLumaAndChromaScalingSupported; 550 bool Cursor64BppSupport; 551 double DCFCLKPerState[DC__VOLTAGE_STATES]; 552 double DCFCLKState[DC__VOLTAGE_STATES][2]; 553 double FabricClockPerState[DC__VOLTAGE_STATES]; 554 double SOCCLKPerState[DC__VOLTAGE_STATES]; 555 double PHYCLKPerState[DC__VOLTAGE_STATES]; 556 double DTBCLKPerState[DC__VOLTAGE_STATES]; 557 double MaxDppclk[DC__VOLTAGE_STATES]; 558 double MaxDSCCLK[DC__VOLTAGE_STATES]; 559 double DRAMSpeedPerState[DC__VOLTAGE_STATES]; 560 double MaxDispclk[DC__VOLTAGE_STATES]; 561 int VoltageOverrideLevel; 562 double PHYCLKD32PerState[DC__VOLTAGE_STATES]; 563 564 /*outputs*/ 565 bool ScaleRatioAndTapsSupport; 566 bool SourceFormatPixelAndScanSupport; 567 double TotalBandwidthConsumedGBytePerSecond; 568 bool DCCEnabledInAnyPlane; 569 bool WritebackLatencySupport; 570 bool WritebackModeSupport; 571 bool Writeback10bpc420Supported; 572 bool BandwidthSupport[DC__VOLTAGE_STATES]; 573 unsigned int TotalNumberOfActiveWriteback; 574 double CriticalPoint; 575 double ReturnBWToDCNPerState; 576 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 577 bool prefetch_vm_bw_valid; 578 bool prefetch_row_bw_valid; 579 bool NumberOfOTGSupport; 580 bool NonsupportedDSCInputBPC; 581 bool WritebackScaleRatioAndTapsSupport; 582 bool CursorSupport; 583 bool PitchSupport; 584 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES]; 585 586 /* Mode Support Reason */ 587 bool P2IWith420; 588 bool DSCOnlyIfNecessaryWithBPP; 589 bool DSC422NativeNotSupported; 590 bool LinkRateDoesNotMatchDPVersion; 591 bool LinkRateForMultistreamNotIndicated; 592 bool BPPForMultistreamNotIndicated; 593 bool MultistreamWithHDMIOreDP; 594 bool MSOOrODMSplitWithNonDPLink; 595 bool NotEnoughLanesForMSO; 596 bool ViewportExceedsSurface; 597 598 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 599 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 600 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 601 bool InvalidCombinationOfMALLUseForPState; 602 603 enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX]; 604 double PrefetchLinesYThisState[DC__NUM_DPP__MAX]; 605 double PrefetchLinesCThisState[DC__NUM_DPP__MAX]; 606 double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX]; 607 double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX]; 608 double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX]; 609 double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX]; 610 double MetaRowBytesThisState[DC__NUM_DPP__MAX]; 611 bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 612 bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 613 bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX]; 614 bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX]; 615 616 unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 617 double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 618 unsigned int MicroTileHeightY[DC__NUM_DPP__MAX]; 619 unsigned int MicroTileHeightC[DC__NUM_DPP__MAX]; 620 unsigned int MicroTileWidthY[DC__NUM_DPP__MAX]; 621 unsigned int MicroTileWidthC[DC__NUM_DPP__MAX]; 622 bool ImmediateFlipRequiredFinal; 623 bool DCCProgrammingAssumesScanDirectionUnknownFinal; 624 bool EnoughWritebackUnits; 625 bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES]; 626 bool NumberOfDP2p0Support; 627 unsigned int MaxNumDP2p0Streams; 628 unsigned int MaxNumDP2p0Outputs; 629 enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 630 enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 631 double WritebackLineBufferLumaBufferSize; 632 double WritebackLineBufferChromaBufferSize; 633 double WritebackMinHSCLRatio; 634 double WritebackMinVSCLRatio; 635 double WritebackMaxHSCLRatio; 636 double WritebackMaxVSCLRatio; 637 double WritebackMaxHSCLTaps; 638 double WritebackMaxVSCLTaps; 639 unsigned int MaxNumDPP; 640 unsigned int MaxNumOTG; 641 double CursorBufferSize; 642 double CursorChunkSize; 643 unsigned int Mode; 644 double OutputLinkDPLanes[DC__NUM_DPP__MAX]; 645 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only 646 double ImmediateFlipBW[DC__NUM_DPP__MAX]; 647 double MaxMaxVStartup[DC__VOLTAGE_STATES][2]; 648 649 double WritebackLumaVExtra; 650 double WritebackChromaVExtra; 651 double WritebackRequiredDISPCLK; 652 double MaximumSwathWidthSupport; 653 double MaximumSwathWidthInDETBuffer; 654 double MaximumSwathWidthInLineBuffer; 655 double MaxDispclkRoundedDownToDFSGranularity; 656 double MaxDppclkRoundedDownToDFSGranularity; 657 double PlaneRequiredDISPCLKWithoutODMCombine; 658 double PlaneRequiredDISPCLKWithODMCombine; 659 double PlaneRequiredDISPCLK; 660 double TotalNumberOfActiveOTG; 661 double FECOverhead; 662 double EffectiveFECOverhead; 663 double Outbpp; 664 unsigned int OutbppDSC; 665 double TotalDSCUnitsRequired; 666 double bpp; 667 unsigned int slices; 668 double SwathWidthGranularityY; 669 double RoundedUpMaxSwathSizeBytesY; 670 double SwathWidthGranularityC; 671 double RoundedUpMaxSwathSizeBytesC; 672 double EffectiveDETLBLinesLuma; 673 double EffectiveDETLBLinesChroma; 674 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2]; 675 double PDEAndMetaPTEBytesPerFrameY; 676 double PDEAndMetaPTEBytesPerFrameC; 677 unsigned int MetaRowBytesY; 678 unsigned int MetaRowBytesC; 679 unsigned int DPTEBytesPerRowC; 680 unsigned int DPTEBytesPerRowY; 681 double ExtraLatency; 682 double TimeCalc; 683 double TWait; 684 double MaximumReadBandwidthWithPrefetch; 685 double MaximumReadBandwidthWithoutPrefetch; 686 double total_dcn_read_bw_with_flip; 687 double total_dcn_read_bw_with_flip_no_urgent_burst; 688 double FractionOfUrgentBandwidth; 689 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output 690 691 /* ms locals */ 692 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; 693 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 694 int NoOfDPPThisState[DC__NUM_DPP__MAX]; 695 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 696 double SwathWidthYThisState[DC__NUM_DPP__MAX]; 697 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 698 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; 699 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX]; 700 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 701 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 702 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 703 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 704 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 705 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX]; 706 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 707 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 708 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2]; 709 bool PrefetchSupported[DC__VOLTAGE_STATES][2]; 710 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2]; 711 double RequiredDISPCLK[DC__VOLTAGE_STATES][2]; 712 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2]; 713 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2]; 714 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2]; 715 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2]; 716 bool ModeSupport[DC__VOLTAGE_STATES][2]; 717 double ReturnBWPerState[DC__VOLTAGE_STATES][2]; 718 bool DIOSupport[DC__VOLTAGE_STATES]; 719 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES]; 720 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 721 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 722 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES]; 723 bool ROBSupport[DC__VOLTAGE_STATES][2]; 724 //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean 725 bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2]; 726 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; 727 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2]; 728 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2]; 729 double PrefetchBW[DC__NUM_DPP__MAX]; 730 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 731 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 732 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 733 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 734 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 735 unsigned int MaxNumSwY[DC__NUM_DPP__MAX]; 736 unsigned int MaxNumSwC[DC__NUM_DPP__MAX]; 737 double PrefillY[DC__NUM_DPP__MAX]; 738 double PrefillC[DC__NUM_DPP__MAX]; 739 double LineTimesForPrefetch[DC__NUM_DPP__MAX]; 740 double LinesForMetaPTE[DC__NUM_DPP__MAX]; 741 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX]; 742 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 743 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX]; 744 double BytePerPixelInDETY[DC__NUM_DPP__MAX]; 745 double BytePerPixelInDETC[DC__NUM_DPP__MAX]; 746 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 747 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 748 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 749 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 750 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 751 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2]; 752 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX]; 753 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX]; 754 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX]; 755 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX]; 756 double MaxSwathHeightY[DC__NUM_DPP__MAX]; 757 double MaxSwathHeightC[DC__NUM_DPP__MAX]; 758 double MinSwathHeightY[DC__NUM_DPP__MAX]; 759 double MinSwathHeightC[DC__NUM_DPP__MAX]; 760 double ReadBandwidthLuma[DC__NUM_DPP__MAX]; 761 double ReadBandwidthChroma[DC__NUM_DPP__MAX]; 762 double ReadBandwidth[DC__NUM_DPP__MAX]; 763 double WriteBandwidth[DC__NUM_DPP__MAX]; 764 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 765 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 766 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 767 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 768 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 769 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 770 double AlignedYPitch[DC__NUM_DPP__MAX]; 771 double AlignedCPitch[DC__NUM_DPP__MAX]; 772 double MaximumSwathWidth[DC__NUM_DPP__MAX]; 773 double cursor_bw[DC__NUM_DPP__MAX]; 774 double cursor_bw_pre[DC__NUM_DPP__MAX]; 775 double Tno_bw[DC__NUM_DPP__MAX]; 776 double prefetch_vmrow_bw[DC__NUM_DPP__MAX]; 777 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX]; 778 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX]; 779 double final_flip_bw[DC__NUM_DPP__MAX]; 780 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2]; 781 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 782 unsigned int vm_group_bytes[DC__NUM_DPP__MAX]; 783 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX]; 784 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; 785 unsigned int meta_req_height[DC__NUM_DPP__MAX]; 786 unsigned int meta_req_width[DC__NUM_DPP__MAX]; 787 unsigned int meta_row_height[DC__NUM_DPP__MAX]; 788 unsigned int meta_row_width[DC__NUM_DPP__MAX]; 789 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX]; 790 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX]; 791 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX]; 792 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX]; 793 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX]; 794 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX]; 795 double meta_row_bw[DC__NUM_DPP__MAX]; 796 double dpte_row_bw[DC__NUM_DPP__MAX]; 797 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM 798 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM 799 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX]; 800 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX]; 801 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2]; 802 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX]; 803 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX]; 804 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX]; 805 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX]; 806 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX]; 807 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX]; 808 809 810 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 811 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; 812 double MaximumSwathWidthInLineBufferLuma; 813 double MaximumSwathWidthInLineBufferChroma; 814 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; 815 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; 816 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; 817 double dummy1[DC__NUM_DPP__MAX]; 818 double dummy2[DC__NUM_DPP__MAX]; 819 unsigned int dummy3[DC__NUM_DPP__MAX]; 820 unsigned int dummy4[DC__NUM_DPP__MAX]; 821 double dummy5; 822 double dummy6; 823 double dummy7[DC__NUM_DPP__MAX]; 824 double dummy8[DC__NUM_DPP__MAX]; 825 double dummy13[DC__NUM_DPP__MAX]; 826 double dummy_double_array[2][DC__NUM_DPP__MAX]; 827 unsigned int dummyinteger3[DC__NUM_DPP__MAX]; 828 unsigned int dummyinteger4[DC__NUM_DPP__MAX]; 829 unsigned int dummyinteger5; 830 unsigned int dummyinteger6; 831 unsigned int dummyinteger7; 832 unsigned int dummyinteger8; 833 unsigned int dummyinteger9; 834 unsigned int dummyinteger10; 835 unsigned int dummyinteger11; 836 unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX]; 837 838 bool dummysinglestring; 839 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 840 double PlaneRequiredDISPCLKWithODMCombine2To1; 841 double PlaneRequiredDISPCLKWithODMCombine4To1; 842 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2]; 843 bool LinkDSCEnable; 844 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES]; 845 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX]; 846 double SwathWidthCThisState[DC__NUM_DPP__MAX]; 847 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 848 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; 849 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX]; 850 851 unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 852 unsigned int NotEnoughUrgentLatencyHidingPre; 853 int PTEBufferSizeInRequestsForLuma; 854 int PTEBufferSizeInRequestsForChroma; 855 856 // Missing from VBA 857 int dpte_group_bytes_chroma; 858 unsigned int vm_group_bytes_chroma; 859 double dst_x_after_scaler; 860 double dst_y_after_scaler; 861 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; 862 863 /* perf locals*/ 864 double PrefetchBandwidth[DC__NUM_DPP__MAX]; 865 double VInitPreFillY[DC__NUM_DPP__MAX]; 866 double VInitPreFillC[DC__NUM_DPP__MAX]; 867 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX]; 868 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX]; 869 unsigned int VStartup[DC__NUM_DPP__MAX]; 870 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 871 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 872 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; 873 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; 874 double VRatioPrefetchY[DC__NUM_DPP__MAX]; 875 double VRatioPrefetchC[DC__NUM_DPP__MAX]; 876 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; 877 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX]; 878 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX]; 879 double MinTTUVBlank[DC__NUM_DPP__MAX]; 880 double BytePerPixelDETY[DC__NUM_DPP__MAX]; 881 double BytePerPixelDETC[DC__NUM_DPP__MAX]; 882 double SwathWidthY[DC__NUM_DPP__MAX]; 883 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX]; 884 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX]; 885 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX]; 886 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX]; 887 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX]; 888 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 889 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 890 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 891 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 892 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX]; 893 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX]; 894 double MetaRowByte[DC__NUM_DPP__MAX]; 895 double PrefetchSourceLinesY[DC__NUM_DPP__MAX]; 896 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX]; 897 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX]; 898 double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; 899 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; 900 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; 901 double DSCCLK_calculated[DC__NUM_DPP__MAX]; 902 unsigned int DSCDelay[DC__NUM_DPP__MAX]; 903 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; 904 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 905 double DPPCLK[DC__NUM_DPP__MAX]; 906 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; 907 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; 908 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; 909 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; 910 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; 911 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; 912 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; 913 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; 914 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; 915 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; 916 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; 917 double XFCTransferDelay[DC__NUM_DPP__MAX]; 918 double XFCPrechargeDelay[DC__NUM_DPP__MAX]; 919 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; 920 double XFCPrefetchMargin[DC__NUM_DPP__MAX]; 921 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; 922 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; 923 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM 924 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM 925 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX]; 926 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX]; 927 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX]; 928 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX]; 929 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX]; 930 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX]; 931 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX]; 932 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX]; 933 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX]; 934 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX]; 935 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX]; 936 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX]; 937 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX]; 938 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX]; 939 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX]; 940 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX]; 941 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX]; 942 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX]; 943 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX]; 944 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX]; 945 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX]; 946 double TimePerVMGroupFlip[DC__NUM_DPP__MAX]; 947 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX]; 948 double TimePerVMRequestFlip[DC__NUM_DPP__MAX]; 949 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 950 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 951 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 952 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 953 double LinesToFinishSwathTransferStutterCriticalPlane; 954 unsigned int BytePerPixelYCriticalPlane; 955 double SwathWidthYCriticalPlane; 956 double LinesInDETY[DC__NUM_DPP__MAX]; 957 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; 958 959 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX]; 960 double SwathWidthC[DC__NUM_DPP__MAX]; 961 unsigned int BytePerPixelY[DC__NUM_DPP__MAX]; 962 unsigned int BytePerPixelC[DC__NUM_DPP__MAX]; 963 unsigned int dummyinteger1; 964 unsigned int dummyinteger2; 965 double FinalDRAMClockChangeLatency; 966 double Tdmdl_vm[DC__NUM_DPP__MAX]; 967 double Tdmdl[DC__NUM_DPP__MAX]; 968 double TSetup[DC__NUM_DPP__MAX]; 969 unsigned int ThisVStartup; 970 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX]; 971 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX]; 972 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX]; 973 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX]; 974 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; 975 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; 976 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; 977 double VStartupMargin; 978 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX]; 979 980 /* Missing from VBA */ 981 unsigned int MaximumMaxVStartupLines; 982 double FabricAndDRAMBandwidth; 983 double LinesInDETLuma; 984 double LinesInDETChroma; 985 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; 986 unsigned int LinesInDETC[DC__NUM_DPP__MAX]; 987 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; 988 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 989 double UrgentLatencySupportUs[DC__NUM_DPP__MAX]; 990 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES]; 991 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2]; 992 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 993 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 994 double qual_row_bw[DC__NUM_DPP__MAX]; 995 double prefetch_row_bw[DC__NUM_DPP__MAX]; 996 double prefetch_vm_bw[DC__NUM_DPP__MAX]; 997 998 double PTEGroupSize; 999 unsigned int PDEProcessingBufIn64KBReqs; 1000 1001 double MaxTotalVActiveRDBandwidth; 1002 bool DoUrgentLatencyAdjustment; 1003 double UrgentLatencyAdjustmentFabricClockComponent; 1004 double UrgentLatencyAdjustmentFabricClockReference; 1005 double MinUrgentLatencySupportUs; 1006 double MinFullDETBufferingTime; 1007 double AverageReadBandwidthGBytePerSecond; 1008 bool FirstMainPlane; 1009 1010 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; 1011 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; 1012 double HRatioChroma[DC__NUM_DPP__MAX]; 1013 double VRatioChroma[DC__NUM_DPP__MAX]; 1014 int WritebackSourceWidth[DC__NUM_DPP__MAX]; 1015 1016 bool ModeIsSupported; 1017 bool ODMCombine4To1Supported; 1018 1019 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; 1020 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; 1021 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; 1022 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; 1023 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; 1024 unsigned int WritebackVTaps[DC__NUM_DPP__MAX]; 1025 bool DSCEnable[DC__NUM_DPP__MAX]; 1026 1027 double DRAMClockChangeLatencyOverride; 1028 1029 double GPUVMMinPageSize; 1030 double HostVMMinPageSize; 1031 1032 bool MPCCombineEnable[DC__NUM_DPP__MAX]; 1033 unsigned int HostVMMaxNonCachedPageTableLevels; 1034 bool DynamicMetadataVMEnabled; 1035 double WritebackInterfaceBufferSize; 1036 double WritebackLineBufferSize; 1037 1038 double DCCRateLuma[DC__NUM_DPP__MAX]; 1039 double DCCRateChroma[DC__NUM_DPP__MAX]; 1040 1041 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; 1042 1043 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; 1044 bool NumberOfHDMIFRLSupport; 1045 unsigned int MaxNumHDMIFRLOutputs; 1046 int AudioSampleRate[DC__NUM_DPP__MAX]; 1047 int AudioSampleLayout[DC__NUM_DPP__MAX]; 1048 1049 int PercentMarginOverMinimumRequiredDCFCLK; 1050 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2]; 1051 enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX]; 1052 unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX]; 1053 unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; 1054 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; 1055 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 1056 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; 1057 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; 1058 double UrgLatency[DC__VOLTAGE_STATES]; 1059 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1060 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1061 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1062 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1063 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1064 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1065 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1066 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1067 unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1068 unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1069 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 1070 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1071 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1072 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1073 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1074 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2]; 1075 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2]; 1076 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2]; 1077 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2]; 1078 double WritebackDelayTime[DC__NUM_DPP__MAX]; 1079 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; 1080 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; 1081 unsigned int dummyinteger17; 1082 unsigned int dummyinteger18; 1083 unsigned int dummyinteger19; 1084 unsigned int dummyinteger20; 1085 unsigned int dummyinteger21; 1086 unsigned int dummyinteger22; 1087 unsigned int dummyinteger23; 1088 unsigned int dummyinteger24; 1089 unsigned int dummyinteger25; 1090 unsigned int dummyinteger26; 1091 unsigned int dummyinteger27; 1092 unsigned int dummyinteger28; 1093 unsigned int dummyinteger29; 1094 bool dummystring[DC__NUM_DPP__MAX]; 1095 double BPP; 1096 enum odm_combine_policy ODMCombinePolicy; 1097 bool UseMinimumRequiredDCFCLK; 1098 bool ClampMinDCFCLK; 1099 bool AllowDramClockChangeOneDisplayVactive; 1100 1101 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation; 1102 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency; 1103 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData; 1104 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly; 1105 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly; 1106 double SRExitZ8Time; 1107 double SREnterPlusExitZ8Time; 1108 double Z8StutterExitWatermark; 1109 double Z8StutterEnterPlusExitWatermark; 1110 double Z8StutterEfficiencyNotIncludingVBlank; 1111 double Z8StutterEfficiency; 1112 double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX]; 1113 double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX]; 1114 double UrgBurstFactorCursor[DC__NUM_DPP__MAX]; 1115 double UrgBurstFactorLuma[DC__NUM_DPP__MAX]; 1116 double UrgBurstFactorChroma[DC__NUM_DPP__MAX]; 1117 double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX]; 1118 double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX]; 1119 double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX]; 1120 bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 1121 bool LinkCapacitySupport[DC__NUM_DPP__MAX]; 1122 bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX]; 1123 unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX]; 1124 unsigned int VFrontPorch[DC__NUM_DPP__MAX]; 1125 int ConfigReturnBufferSizeInKByte; 1126 enum unbounded_requesting_policy UseUnboundedRequesting; 1127 int CompressedBufferSegmentSizeInkByte; 1128 int CompressedBufferSizeInkByte; 1129 int MetaFIFOSizeInKEntries; 1130 int ZeroSizeBufferEntries; 1131 int COMPBUF_RESERVED_SPACE_64B; 1132 int COMPBUF_RESERVED_SPACE_ZS; 1133 bool UnboundedRequestEnabled; 1134 bool DSC422NativeSupport; 1135 bool NoEnoughUrgentLatencyHiding; 1136 bool NoEnoughUrgentLatencyHidingPre; 1137 int NumberOfStutterBurstsPerFrame; 1138 int Z8NumberOfStutterBurstsPerFrame; 1139 unsigned int MaximumDSCBitsPerComponent; 1140 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; 1141 double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX]; 1142 double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX]; 1143 double SurfaceRequiredDISPCLKWithoutODMCombine; 1144 double SurfaceRequiredDISPCLK; 1145 double MinActiveFCLKChangeLatencySupported; 1146 int MinVoltageLevel; 1147 int MaxVoltageLevel; 1148 unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2]; 1149 unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2]; 1150 unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 1151 unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX]; 1152 unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX]; 1153 bool ExceededMALLSize; 1154 bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX]; 1155 unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX]; 1156 unsigned int CompressedBufferSizeInkByteThisState; 1157 enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2]; 1158 bool USRRetrainingSupport[DC__VOLTAGE_STATES][2]; 1159 enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX]; 1160 bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2]; 1161 bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX]; 1162 enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX]; 1163 bool UnboundedRequestEnabledThisState; 1164 bool DRAMClockChangeRequirementFinal; 1165 bool FCLKChangeRequirementFinal; 1166 bool USRRetrainingRequiredFinal; 1167 unsigned int DETSizeOverride[DC__NUM_DPP__MAX]; 1168 unsigned int nomDETInKByte; 1169 enum mpc_combine_affinity MPCCombineUse[DC__NUM_DPP__MAX]; 1170 bool MPCCombineMethodIncompatible; 1171 unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 1172 bool ExceededMultistreamSlots[DC__VOLTAGE_STATES]; 1173 enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX]; 1174 unsigned int OutputMultistreamId[DC__NUM_DPP__MAX]; 1175 bool OutputMultistreamEn[DC__NUM_DPP__MAX]; 1176 bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX]; 1177 double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX]; 1178 double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX]; 1179 bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32 1180 bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32 1181 bool NotEnoughDSCSlices[DC__VOLTAGE_STATES]; 1182 bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES]; 1183 bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; 1184 unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX]; 1185 unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX]; 1186 unsigned int BlockHeightY[DC__NUM_DPP__MAX]; 1187 unsigned int BlockHeightC[DC__NUM_DPP__MAX]; 1188 unsigned int BlockWidthY[DC__NUM_DPP__MAX]; 1189 unsigned int BlockWidthC[DC__NUM_DPP__MAX]; 1190 unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX]; 1191 bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2]; 1192 struct dummy_vars dummy_vars; 1193 }; 1194 1195 bool CalculateMinAndMaxPrefetchMode( 1196 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, 1197 unsigned int *MinPrefetchMode, 1198 unsigned int *MaxPrefetchMode); 1199 1200 double CalculateWriteBackDISPCLK( 1201 enum source_format_class WritebackPixelFormat, 1202 double PixelClock, 1203 double WritebackHRatio, 1204 double WritebackVRatio, 1205 unsigned int WritebackLumaHTaps, 1206 unsigned int WritebackLumaVTaps, 1207 unsigned int WritebackChromaHTaps, 1208 unsigned int WritebackChromaVTaps, 1209 double WritebackDestinationWidth, 1210 unsigned int HTotal, 1211 unsigned int WritebackChromaLineBufferWidth); 1212 1213 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ 1214