1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef __DML2_DISPLAY_MODE_VBA_H__ 28 #define __DML2_DISPLAY_MODE_VBA_H__ 29 30 struct display_mode_lib; 31 32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib); 33 34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) 35 36 dml_get_attr_decl(clk_dcf_deepsleep); 37 dml_get_attr_decl(wm_urgent); 38 dml_get_attr_decl(wm_memory_trip); 39 dml_get_attr_decl(wm_writeback_urgent); 40 dml_get_attr_decl(wm_stutter_exit); 41 dml_get_attr_decl(wm_stutter_enter_exit); 42 dml_get_attr_decl(wm_dram_clock_change); 43 dml_get_attr_decl(wm_writeback_dram_clock_change); 44 dml_get_attr_decl(stutter_efficiency_no_vblank); 45 dml_get_attr_decl(stutter_efficiency); 46 dml_get_attr_decl(stutter_period); 47 dml_get_attr_decl(urgent_latency); 48 dml_get_attr_decl(urgent_extra_latency); 49 dml_get_attr_decl(nonurgent_latency); 50 dml_get_attr_decl(dram_clock_change_latency); 51 dml_get_attr_decl(dispclk_calculated); 52 dml_get_attr_decl(total_data_read_bw); 53 dml_get_attr_decl(return_bw); 54 dml_get_attr_decl(tcalc); 55 dml_get_attr_decl(fraction_of_urgent_bandwidth); 56 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); 57 58 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) 59 60 dml_get_pipe_attr_decl(dsc_delay); 61 dml_get_pipe_attr_decl(dppclk_calculated); 62 dml_get_pipe_attr_decl(dscclk_calculated); 63 dml_get_pipe_attr_decl(min_ttu_vblank); 64 dml_get_pipe_attr_decl(min_ttu_vblank_in_us); 65 dml_get_pipe_attr_decl(vratio_prefetch_l); 66 dml_get_pipe_attr_decl(vratio_prefetch_c); 67 dml_get_pipe_attr_decl(dst_x_after_scaler); 68 dml_get_pipe_attr_decl(dst_y_after_scaler); 69 dml_get_pipe_attr_decl(dst_y_per_vm_vblank); 70 dml_get_pipe_attr_decl(dst_y_per_row_vblank); 71 dml_get_pipe_attr_decl(dst_y_prefetch); 72 dml_get_pipe_attr_decl(dst_y_per_vm_flip); 73 dml_get_pipe_attr_decl(dst_y_per_row_flip); 74 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); 75 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); 76 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); 77 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip); 78 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us); 79 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us); 80 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us); 81 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us); 82 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us); 83 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us); 84 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us); 85 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us); 86 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us); 87 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us); 88 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us); 89 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us); 90 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us); 91 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us); 92 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us); 93 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us); 94 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us); 95 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us); 96 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us); 97 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us); 98 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us); 99 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us); 100 101 dml_get_pipe_attr_decl(vstartup); 102 dml_get_pipe_attr_decl(vupdate_offset); 103 dml_get_pipe_attr_decl(vupdate_width); 104 dml_get_pipe_attr_decl(vready_offset); 105 106 double get_total_immediate_flip_bytes( 107 struct display_mode_lib *mode_lib, 108 const display_e2e_pipe_params_st *pipes, 109 unsigned int num_pipes); 110 double get_total_immediate_flip_bw( 111 struct display_mode_lib *mode_lib, 112 const display_e2e_pipe_params_st *pipes, 113 unsigned int num_pipes); 114 double get_total_prefetch_bw( 115 struct display_mode_lib *mode_lib, 116 const display_e2e_pipe_params_st *pipes, 117 unsigned int num_pipes); 118 unsigned int dml_get_voltage_level( 119 struct display_mode_lib *mode_lib, 120 const display_e2e_pipe_params_st *pipes, 121 unsigned int num_pipes); 122 123 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); 124 125 bool Calculate256BBlockSizes( 126 enum source_format_class SourcePixelFormat, 127 enum dm_swizzle_mode SurfaceTiling, 128 unsigned int BytePerPixelY, 129 unsigned int BytePerPixelC, 130 unsigned int *BlockHeight256BytesY, 131 unsigned int *BlockHeight256BytesC, 132 unsigned int *BlockWidth256BytesY, 133 unsigned int *BlockWidth256BytesC); 134 135 struct vba_vars_st { 136 ip_params_st ip; 137 soc_bounding_box_st soc; 138 139 int maxMpcComb; 140 bool UseMaximumVStartup; 141 142 double WritebackDISPCLK; 143 double DPPCLKUsingSingleDPPLuma; 144 double DPPCLKUsingSingleDPPChroma; 145 double DISPCLKWithRamping; 146 double DISPCLKWithoutRamping; 147 double GlobalDPPCLK; 148 double DISPCLKWithRampingRoundedToDFSGranularity; 149 double DISPCLKWithoutRampingRoundedToDFSGranularity; 150 double MaxDispclkRoundedToDFSGranularity; 151 bool DCCEnabledAnyPlane; 152 double ReturnBandwidthToDCN; 153 unsigned int TotalActiveDPP; 154 unsigned int TotalDCCActiveDPP; 155 double UrgentRoundTripAndOutOfOrderLatency; 156 double StutterPeriod; 157 double FrameTimeForMinFullDETBufferingTime; 158 double AverageReadBandwidth; 159 double TotalRowReadBandwidth; 160 double PartOfBurstThatFitsInROB; 161 double StutterBurstTime; 162 unsigned int NextPrefetchMode; 163 double NextMaxVStartup; 164 double VBlankTime; 165 double SmallestVBlank; 166 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; 167 double EffectiveDETPlusLBLinesLuma; 168 double EffectiveDETPlusLBLinesChroma; 169 double UrgentLatencySupportUsLuma; 170 double UrgentLatencySupportUsChroma; 171 unsigned int DSCFormatFactor; 172 173 bool DummyPStateCheck; 174 bool DRAMClockChangeSupportsVActive; 175 bool PrefetchModeSupported; 176 bool PrefetchAndImmediateFlipSupported; 177 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only 178 double XFCRemoteSurfaceFlipDelay; 179 double TInitXFill; 180 double TslvChk; 181 double SrcActiveDrainRate; 182 bool ImmediateFlipSupported; 183 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only 184 185 bool PrefetchERROR; 186 187 unsigned int VStartupLines; 188 unsigned int ActiveDPPs; 189 unsigned int LBLatencyHidingSourceLinesY; 190 unsigned int LBLatencyHidingSourceLinesC; 191 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; 192 double MinActiveDRAMClockChangeMargin; 193 double InitFillLevel; 194 double FinalFillMargin; 195 double FinalFillLevel; 196 double RemainingFillLevel; 197 double TFinalxFill; 198 199 // 200 // SOC Bounding Box Parameters 201 // 202 double SRExitTime; 203 double SREnterPlusExitTime; 204 double UrgentLatencyPixelDataOnly; 205 double UrgentLatencyPixelMixedWithVMData; 206 double UrgentLatencyVMDataOnly; 207 double UrgentLatency; // max of the above three 208 double WritebackLatency; 209 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support 210 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support 211 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support 212 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support 213 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support 214 double NumberOfChannels; 215 double DRAMChannelWidth; 216 double FabricDatapathToDCNDataReturn; 217 double ReturnBusWidth; 218 double Downspreading; 219 double DISPCLKDPPCLKDSCCLKDownSpreading; 220 double DISPCLKDPPCLKVCOSpeed; 221 double RoundTripPingLatencyCycles; 222 double UrgentOutOfOrderReturnPerChannel; 223 double UrgentOutOfOrderReturnPerChannelPixelDataOnly; 224 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData; 225 double UrgentOutOfOrderReturnPerChannelVMDataOnly; 226 unsigned int VMMPageSize; 227 double DRAMClockChangeLatency; 228 double XFCBusTransportTime; 229 bool UseUrgentBurstBandwidth; 230 double XFCXBUFLatencyTolerance; 231 232 // 233 // IP Parameters 234 // 235 unsigned int ROBBufferSizeInKByte; 236 double DETBufferSizeInKByte; 237 double DETBufferSizeInTime; 238 unsigned int DPPOutputBufferPixels; 239 unsigned int OPPOutputBufferLines; 240 unsigned int PixelChunkSizeInKByte; 241 double ReturnBW; 242 bool GPUVMEnable; 243 bool HostVMEnable; 244 unsigned int GPUVMMaxPageTableLevels; 245 unsigned int HostVMMaxPageTableLevels; 246 unsigned int HostVMCachedPageTableLevels; 247 unsigned int OverrideGPUVMPageTableLevels; 248 unsigned int OverrideHostVMPageTableLevels; 249 unsigned int MetaChunkSize; 250 unsigned int MinMetaChunkSizeBytes; 251 unsigned int WritebackChunkSize; 252 bool ODMCapability; 253 unsigned int NumberOfDSC; 254 unsigned int LineBufferSize; 255 unsigned int MaxLineBufferLines; 256 unsigned int WritebackInterfaceLumaBufferSize; 257 unsigned int WritebackInterfaceChromaBufferSize; 258 unsigned int WritebackChromaLineBufferWidth; 259 enum writeback_config WritebackConfiguration; 260 double MaxDCHUBToPSCLThroughput; 261 double MaxPSCLToLBThroughput; 262 unsigned int PTEBufferSizeInRequestsLuma; 263 unsigned int PTEBufferSizeInRequestsChroma; 264 double DISPCLKRampingMargin; 265 unsigned int MaxInterDCNTileRepeaters; 266 bool XFCSupported; 267 double XFCSlvChunkSize; 268 double XFCFillBWOverhead; 269 double XFCFillConstant; 270 double XFCTSlvVupdateOffset; 271 double XFCTSlvVupdateWidth; 272 double XFCTSlvVreadyOffset; 273 double DPPCLKDelaySubtotal; 274 double DPPCLKDelaySCL; 275 double DPPCLKDelaySCLLBOnly; 276 double DPPCLKDelayCNVCFormater; 277 double DPPCLKDelayCNVCCursor; 278 double DISPCLKDelaySubtotal; 279 bool ProgressiveToInterlaceUnitInOPP; 280 // Pipe/Plane Parameters 281 int VoltageLevel; 282 double FabricClock; 283 double DRAMSpeed; 284 double DISPCLK; 285 double SOCCLK; 286 double DCFCLK; 287 288 unsigned int NumberOfActivePlanes; 289 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; 290 unsigned int ViewportWidth[DC__NUM_DPP__MAX]; 291 unsigned int ViewportHeight[DC__NUM_DPP__MAX]; 292 unsigned int ViewportYStartY[DC__NUM_DPP__MAX]; 293 unsigned int ViewportYStartC[DC__NUM_DPP__MAX]; 294 unsigned int PitchY[DC__NUM_DPP__MAX]; 295 unsigned int PitchC[DC__NUM_DPP__MAX]; 296 double HRatio[DC__NUM_DPP__MAX]; 297 double VRatio[DC__NUM_DPP__MAX]; 298 unsigned int htaps[DC__NUM_DPP__MAX]; 299 unsigned int vtaps[DC__NUM_DPP__MAX]; 300 unsigned int HTAPsChroma[DC__NUM_DPP__MAX]; 301 unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; 302 unsigned int HTotal[DC__NUM_DPP__MAX]; 303 unsigned int VTotal[DC__NUM_DPP__MAX]; 304 unsigned int VTotal_Max[DC__NUM_DPP__MAX]; 305 unsigned int VTotal_Min[DC__NUM_DPP__MAX]; 306 int DPPPerPlane[DC__NUM_DPP__MAX]; 307 double PixelClock[DC__NUM_DPP__MAX]; 308 double PixelClockBackEnd[DC__NUM_DPP__MAX]; 309 bool DCCEnable[DC__NUM_DPP__MAX]; 310 bool FECEnable[DC__NUM_DPP__MAX]; 311 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; 312 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; 313 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; 314 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX]; 315 bool WritebackEnable[DC__NUM_DPP__MAX]; 316 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX]; 317 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; 318 double WritebackDestinationHeight[DC__NUM_DPP__MAX]; 319 double WritebackSourceHeight[DC__NUM_DPP__MAX]; 320 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX]; 321 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX]; 322 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX]; 323 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX]; 324 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX]; 325 double WritebackHRatio[DC__NUM_DPP__MAX]; 326 double WritebackVRatio[DC__NUM_DPP__MAX]; 327 unsigned int HActive[DC__NUM_DPP__MAX]; 328 unsigned int VActive[DC__NUM_DPP__MAX]; 329 bool Interlace[DC__NUM_DPP__MAX]; 330 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; 331 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; 332 bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; 333 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; 334 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; 335 double DCCRate[DC__NUM_DPP__MAX]; 336 double AverageDCCCompressionRate; 337 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX]; 338 double OutputBpp[DC__NUM_DPP__MAX]; 339 bool DSCEnabled[DC__NUM_DPP__MAX]; 340 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 341 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 342 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 343 bool skip_dio_check[DC__NUM_DPP__MAX]; 344 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 345 bool SynchronizedVBlank; 346 unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; 347 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 348 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 349 bool XFCEnabled[DC__NUM_DPP__MAX]; 350 bool ScalerEnabled[DC__NUM_DPP__MAX]; 351 352 // Intermediates/Informational 353 bool ImmediateFlipSupport; 354 double DETBufferSizeY[DC__NUM_DPP__MAX]; 355 double DETBufferSizeC[DC__NUM_DPP__MAX]; 356 unsigned int SwathHeightY[DC__NUM_DPP__MAX]; 357 unsigned int SwathHeightC[DC__NUM_DPP__MAX]; 358 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; 359 double LastPixelOfLineExtraWatermark; 360 double TotalDataReadBandwidth; 361 unsigned int TotalActiveWriteback; 362 unsigned int EffectiveLBLatencyHidingSourceLinesLuma; 363 unsigned int EffectiveLBLatencyHidingSourceLinesChroma; 364 double BandwidthAvailableForImmediateFlip; 365 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2]; 366 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2]; 367 unsigned int MinPrefetchMode; 368 unsigned int MaxPrefetchMode; 369 bool AnyLinesForVMOrRowTooLarge; 370 double MaxVStartup; 371 bool IgnoreViewportPositioning; 372 bool ErrorResult[DC__NUM_DPP__MAX]; 373 // 374 // Calculated dml_ml->vba.Outputs 375 // 376 double DCFCLKDeepSleep; 377 double UrgentWatermark; 378 double UrgentExtraLatency; 379 double WritebackUrgentWatermark; 380 double StutterExitWatermark; 381 double StutterEnterPlusExitWatermark; 382 double DRAMClockChangeWatermark; 383 double WritebackDRAMClockChangeWatermark; 384 double StutterEfficiency; 385 double StutterEfficiencyNotIncludingVBlank; 386 double NonUrgentLatencyTolerance; 387 double MinActiveDRAMClockChangeLatencySupported; 388 389 // These are the clocks calcuated by the library but they are not actually 390 // used explicitly. They are fetched by tests and then possibly used. The 391 // ultimate values to use are the ones specified by the parameters to DML 392 double DISPCLK_calculated; 393 double DPPCLK_calculated[DC__NUM_DPP__MAX]; 394 395 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; 396 double VUpdateWidthPix[DC__NUM_DPP__MAX]; 397 double VReadyOffsetPix[DC__NUM_DPP__MAX]; 398 399 unsigned int TotImmediateFlipBytes; 400 double TCalc; 401 402 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX]; 403 unsigned int cache_num_pipes; 404 unsigned int pipe_plane[DC__NUM_DPP__MAX]; 405 406 /* vba mode support */ 407 /*inputs*/ 408 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp; 409 double MaxHSCLRatio; 410 double MaxVSCLRatio; 411 unsigned int MaxNumWriteback; 412 bool WritebackLumaAndChromaScalingSupported; 413 bool Cursor64BppSupport; 414 double DCFCLKPerState[DC__VOLTAGE_STATES]; 415 double DCFCLKState[DC__VOLTAGE_STATES][2]; 416 double FabricClockPerState[DC__VOLTAGE_STATES]; 417 double SOCCLKPerState[DC__VOLTAGE_STATES]; 418 double PHYCLKPerState[DC__VOLTAGE_STATES]; 419 double DTBCLKPerState[DC__VOLTAGE_STATES]; 420 double MaxDppclk[DC__VOLTAGE_STATES]; 421 double MaxDSCCLK[DC__VOLTAGE_STATES]; 422 double DRAMSpeedPerState[DC__VOLTAGE_STATES]; 423 double MaxDispclk[DC__VOLTAGE_STATES]; 424 int VoltageOverrideLevel; 425 426 /*outputs*/ 427 bool ScaleRatioAndTapsSupport; 428 bool SourceFormatPixelAndScanSupport; 429 double TotalBandwidthConsumedGBytePerSecond; 430 bool DCCEnabledInAnyPlane; 431 bool WritebackLatencySupport; 432 bool WritebackModeSupport; 433 bool Writeback10bpc420Supported; 434 bool BandwidthSupport[DC__VOLTAGE_STATES]; 435 unsigned int TotalNumberOfActiveWriteback; 436 double CriticalPoint; 437 double ReturnBWToDCNPerState; 438 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 439 bool prefetch_vm_bw_valid; 440 bool prefetch_row_bw_valid; 441 bool NumberOfOTGSupport; 442 bool NonsupportedDSCInputBPC; 443 bool WritebackScaleRatioAndTapsSupport; 444 bool CursorSupport; 445 bool PitchSupport; 446 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES]; 447 448 double WritebackLineBufferLumaBufferSize; 449 double WritebackLineBufferChromaBufferSize; 450 double WritebackMinHSCLRatio; 451 double WritebackMinVSCLRatio; 452 double WritebackMaxHSCLRatio; 453 double WritebackMaxVSCLRatio; 454 double WritebackMaxHSCLTaps; 455 double WritebackMaxVSCLTaps; 456 unsigned int MaxNumDPP; 457 unsigned int MaxNumOTG; 458 double CursorBufferSize; 459 double CursorChunkSize; 460 unsigned int Mode; 461 double OutputLinkDPLanes[DC__NUM_DPP__MAX]; 462 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only 463 double ImmediateFlipBW[DC__NUM_DPP__MAX]; 464 double MaxMaxVStartup[DC__VOLTAGE_STATES][2]; 465 466 double WritebackLumaVExtra; 467 double WritebackChromaVExtra; 468 double WritebackRequiredDISPCLK; 469 double MaximumSwathWidthSupport; 470 double MaximumSwathWidthInDETBuffer; 471 double MaximumSwathWidthInLineBuffer; 472 double MaxDispclkRoundedDownToDFSGranularity; 473 double MaxDppclkRoundedDownToDFSGranularity; 474 double PlaneRequiredDISPCLKWithoutODMCombine; 475 double PlaneRequiredDISPCLKWithODMCombine; 476 double PlaneRequiredDISPCLK; 477 double TotalNumberOfActiveOTG; 478 double FECOverhead; 479 double EffectiveFECOverhead; 480 double Outbpp; 481 unsigned int OutbppDSC; 482 double TotalDSCUnitsRequired; 483 double bpp; 484 unsigned int slices; 485 double SwathWidthGranularityY; 486 double RoundedUpMaxSwathSizeBytesY; 487 double SwathWidthGranularityC; 488 double RoundedUpMaxSwathSizeBytesC; 489 double EffectiveDETLBLinesLuma; 490 double EffectiveDETLBLinesChroma; 491 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2]; 492 double PDEAndMetaPTEBytesPerFrameY; 493 double PDEAndMetaPTEBytesPerFrameC; 494 unsigned int MetaRowBytesY; 495 unsigned int MetaRowBytesC; 496 unsigned int DPTEBytesPerRowC; 497 unsigned int DPTEBytesPerRowY; 498 double ExtraLatency; 499 double TimeCalc; 500 double TWait; 501 double MaximumReadBandwidthWithPrefetch; 502 double MaximumReadBandwidthWithoutPrefetch; 503 double total_dcn_read_bw_with_flip; 504 double total_dcn_read_bw_with_flip_no_urgent_burst; 505 double FractionOfUrgentBandwidth; 506 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output 507 508 /* ms locals */ 509 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; 510 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 511 int NoOfDPPThisState[DC__NUM_DPP__MAX]; 512 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 513 double SwathWidthYThisState[DC__NUM_DPP__MAX]; 514 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 515 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; 516 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX]; 517 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 518 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 519 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 520 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 521 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 522 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX]; 523 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 524 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 525 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2]; 526 bool PrefetchSupported[DC__VOLTAGE_STATES][2]; 527 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2]; 528 double RequiredDISPCLK[DC__VOLTAGE_STATES][2]; 529 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2]; 530 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2]; 531 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2]; 532 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2]; 533 bool ModeSupport[DC__VOLTAGE_STATES][2]; 534 double ReturnBWPerState[DC__VOLTAGE_STATES][2]; 535 bool DIOSupport[DC__VOLTAGE_STATES]; 536 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES]; 537 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 538 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 539 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES]; 540 bool ROBSupport[DC__VOLTAGE_STATES][2]; 541 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; 542 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2]; 543 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2]; 544 double PrefetchBW[DC__NUM_DPP__MAX]; 545 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 546 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 547 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 548 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 549 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 550 unsigned int MaxNumSwY[DC__NUM_DPP__MAX]; 551 unsigned int MaxNumSwC[DC__NUM_DPP__MAX]; 552 double PrefillY[DC__NUM_DPP__MAX]; 553 double PrefillC[DC__NUM_DPP__MAX]; 554 double LineTimesForPrefetch[DC__NUM_DPP__MAX]; 555 double LinesForMetaPTE[DC__NUM_DPP__MAX]; 556 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX]; 557 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 558 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX]; 559 double BytePerPixelInDETY[DC__NUM_DPP__MAX]; 560 double BytePerPixelInDETC[DC__NUM_DPP__MAX]; 561 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 562 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 563 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 564 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 565 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 566 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2]; 567 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX]; 568 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX]; 569 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX]; 570 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX]; 571 double MaxSwathHeightY[DC__NUM_DPP__MAX]; 572 double MaxSwathHeightC[DC__NUM_DPP__MAX]; 573 double MinSwathHeightY[DC__NUM_DPP__MAX]; 574 double MinSwathHeightC[DC__NUM_DPP__MAX]; 575 double ReadBandwidthLuma[DC__NUM_DPP__MAX]; 576 double ReadBandwidthChroma[DC__NUM_DPP__MAX]; 577 double ReadBandwidth[DC__NUM_DPP__MAX]; 578 double WriteBandwidth[DC__NUM_DPP__MAX]; 579 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 580 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 581 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 582 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 583 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 584 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 585 double AlignedYPitch[DC__NUM_DPP__MAX]; 586 double AlignedCPitch[DC__NUM_DPP__MAX]; 587 double MaximumSwathWidth[DC__NUM_DPP__MAX]; 588 double cursor_bw[DC__NUM_DPP__MAX]; 589 double cursor_bw_pre[DC__NUM_DPP__MAX]; 590 double Tno_bw[DC__NUM_DPP__MAX]; 591 double prefetch_vmrow_bw[DC__NUM_DPP__MAX]; 592 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX]; 593 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX]; 594 double final_flip_bw[DC__NUM_DPP__MAX]; 595 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2]; 596 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 597 unsigned int vm_group_bytes[DC__NUM_DPP__MAX]; 598 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX]; 599 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; 600 unsigned int meta_req_height[DC__NUM_DPP__MAX]; 601 unsigned int meta_req_width[DC__NUM_DPP__MAX]; 602 unsigned int meta_row_height[DC__NUM_DPP__MAX]; 603 unsigned int meta_row_width[DC__NUM_DPP__MAX]; 604 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX]; 605 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX]; 606 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX]; 607 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX]; 608 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX]; 609 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX]; 610 double meta_row_bw[DC__NUM_DPP__MAX]; 611 double dpte_row_bw[DC__NUM_DPP__MAX]; 612 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM 613 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM 614 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX]; 615 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX]; 616 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2]; 617 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX]; 618 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX]; 619 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX]; 620 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX]; 621 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX]; 622 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX]; 623 624 625 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 626 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; 627 double MaximumSwathWidthInLineBufferLuma; 628 double MaximumSwathWidthInLineBufferChroma; 629 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; 630 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; 631 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; 632 double dummy1[DC__NUM_DPP__MAX]; 633 double dummy2[DC__NUM_DPP__MAX]; 634 double dummy3[DC__NUM_DPP__MAX]; 635 double dummy4[DC__NUM_DPP__MAX]; 636 double dummy5; 637 double dummy6; 638 double dummy7[DC__NUM_DPP__MAX]; 639 double dummy8[DC__NUM_DPP__MAX]; 640 double dummy13[DC__NUM_DPP__MAX]; 641 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX]; 642 double dummyinteger2ms[DC__NUM_DPP__MAX]; 643 unsigned int dummyinteger3[DC__NUM_DPP__MAX]; 644 unsigned int dummyinteger4[DC__NUM_DPP__MAX]; 645 unsigned int dummyinteger5; 646 unsigned int dummyinteger6; 647 unsigned int dummyinteger7; 648 unsigned int dummyinteger8; 649 unsigned int dummyinteger9; 650 unsigned int dummyinteger10; 651 unsigned int dummyinteger11; 652 unsigned int dummyinteger12; 653 unsigned int dummyinteger30; 654 unsigned int dummyinteger31; 655 unsigned int dummyinteger32; 656 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX]; 657 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; 658 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; 659 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; 660 bool dummysinglestring; 661 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 662 double PlaneRequiredDISPCLKWithODMCombine2To1; 663 double PlaneRequiredDISPCLKWithODMCombine4To1; 664 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2]; 665 bool LinkDSCEnable; 666 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES]; 667 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX]; 668 double SwathWidthCThisState[DC__NUM_DPP__MAX]; 669 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 670 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; 671 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX]; 672 673 unsigned int NotEnoughUrgentLatencyHiding; 674 unsigned int NotEnoughUrgentLatencyHidingPre; 675 int PTEBufferSizeInRequestsForLuma; 676 int PTEBufferSizeInRequestsForChroma; 677 678 // Missing from VBA 679 int dpte_group_bytes_chroma; 680 unsigned int vm_group_bytes_chroma; 681 double dst_x_after_scaler; 682 double dst_y_after_scaler; 683 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; 684 685 /* perf locals*/ 686 double PrefetchBandwidth[DC__NUM_DPP__MAX]; 687 double VInitPreFillY[DC__NUM_DPP__MAX]; 688 double VInitPreFillC[DC__NUM_DPP__MAX]; 689 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX]; 690 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX]; 691 unsigned int VStartup[DC__NUM_DPP__MAX]; 692 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 693 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 694 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; 695 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; 696 double VRatioPrefetchY[DC__NUM_DPP__MAX]; 697 double VRatioPrefetchC[DC__NUM_DPP__MAX]; 698 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; 699 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX]; 700 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX]; 701 double MinTTUVBlank[DC__NUM_DPP__MAX]; 702 double BytePerPixelDETY[DC__NUM_DPP__MAX]; 703 double BytePerPixelDETC[DC__NUM_DPP__MAX]; 704 double SwathWidthY[DC__NUM_DPP__MAX]; 705 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX]; 706 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX]; 707 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX]; 708 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX]; 709 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX]; 710 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 711 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 712 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 713 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 714 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX]; 715 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX]; 716 double MetaRowByte[DC__NUM_DPP__MAX]; 717 double PrefetchSourceLinesY[DC__NUM_DPP__MAX]; 718 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX]; 719 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX]; 720 double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; 721 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; 722 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; 723 double DSCCLK_calculated[DC__NUM_DPP__MAX]; 724 unsigned int DSCDelay[DC__NUM_DPP__MAX]; 725 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; 726 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 727 double DPPCLK[DC__NUM_DPP__MAX]; 728 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; 729 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; 730 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; 731 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; 732 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; 733 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; 734 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; 735 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; 736 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; 737 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; 738 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; 739 double XFCTransferDelay[DC__NUM_DPP__MAX]; 740 double XFCPrechargeDelay[DC__NUM_DPP__MAX]; 741 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; 742 double XFCPrefetchMargin[DC__NUM_DPP__MAX]; 743 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; 744 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; 745 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM 746 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM 747 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX]; 748 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX]; 749 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX]; 750 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX]; 751 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX]; 752 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX]; 753 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX]; 754 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX]; 755 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX]; 756 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX]; 757 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX]; 758 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX]; 759 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX]; 760 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX]; 761 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX]; 762 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX]; 763 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX]; 764 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX]; 765 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX]; 766 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX]; 767 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX]; 768 double TimePerVMGroupFlip[DC__NUM_DPP__MAX]; 769 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX]; 770 double TimePerVMRequestFlip[DC__NUM_DPP__MAX]; 771 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 772 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 773 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 774 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 775 double LinesToFinishSwathTransferStutterCriticalPlane; 776 unsigned int BytePerPixelYCriticalPlane; 777 double SwathWidthYCriticalPlane; 778 double LinesInDETY[DC__NUM_DPP__MAX]; 779 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; 780 781 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX]; 782 double SwathWidthC[DC__NUM_DPP__MAX]; 783 unsigned int BytePerPixelY[DC__NUM_DPP__MAX]; 784 unsigned int BytePerPixelC[DC__NUM_DPP__MAX]; 785 unsigned int dummyinteger1; 786 unsigned int dummyinteger2; 787 double FinalDRAMClockChangeLatency; 788 double Tdmdl_vm[DC__NUM_DPP__MAX]; 789 double Tdmdl[DC__NUM_DPP__MAX]; 790 double TSetup[DC__NUM_DPP__MAX]; 791 unsigned int ThisVStartup; 792 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX]; 793 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX]; 794 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX]; 795 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX]; 796 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; 797 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; 798 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; 799 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX]; 800 double VStartupMargin; 801 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX]; 802 803 /* Missing from VBA */ 804 unsigned int MaximumMaxVStartupLines; 805 double FabricAndDRAMBandwidth; 806 double LinesInDETLuma; 807 double LinesInDETChroma; 808 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; 809 unsigned int LinesInDETC[DC__NUM_DPP__MAX]; 810 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; 811 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 812 double UrgentLatencySupportUs[DC__NUM_DPP__MAX]; 813 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES]; 814 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2]; 815 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 816 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 817 double qual_row_bw[DC__NUM_DPP__MAX]; 818 double prefetch_row_bw[DC__NUM_DPP__MAX]; 819 double prefetch_vm_bw[DC__NUM_DPP__MAX]; 820 821 double PTEGroupSize; 822 unsigned int PDEProcessingBufIn64KBReqs; 823 824 double MaxTotalVActiveRDBandwidth; 825 bool DoUrgentLatencyAdjustment; 826 double UrgentLatencyAdjustmentFabricClockComponent; 827 double UrgentLatencyAdjustmentFabricClockReference; 828 double MinUrgentLatencySupportUs; 829 double MinFullDETBufferingTime; 830 double AverageReadBandwidthGBytePerSecond; 831 bool FirstMainPlane; 832 833 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; 834 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; 835 double HRatioChroma[DC__NUM_DPP__MAX]; 836 double VRatioChroma[DC__NUM_DPP__MAX]; 837 int WritebackSourceWidth[DC__NUM_DPP__MAX]; 838 839 bool ModeIsSupported; 840 bool ODMCombine4To1Supported; 841 842 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; 843 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; 844 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; 845 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; 846 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; 847 unsigned int WritebackVTaps[DC__NUM_DPP__MAX]; 848 bool DSCEnable[DC__NUM_DPP__MAX]; 849 850 double DRAMClockChangeLatencyOverride; 851 852 double GPUVMMinPageSize; 853 double HostVMMinPageSize; 854 855 bool MPCCombineEnable[DC__NUM_DPP__MAX]; 856 unsigned int HostVMMaxNonCachedPageTableLevels; 857 bool DynamicMetadataVMEnabled; 858 double WritebackInterfaceBufferSize; 859 double WritebackLineBufferSize; 860 861 double DCCRateLuma[DC__NUM_DPP__MAX]; 862 double DCCRateChroma[DC__NUM_DPP__MAX]; 863 864 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; 865 866 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; 867 bool NumberOfHDMIFRLSupport; 868 unsigned int MaxNumHDMIFRLOutputs; 869 int AudioSampleRate[DC__NUM_DPP__MAX]; 870 int AudioSampleLayout[DC__NUM_DPP__MAX]; 871 872 int PercentMarginOverMinimumRequiredDCFCLK; 873 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2]; 874 enum immediate_flip_requirement ImmediateFlipRequirement; 875 double DETBufferSizeYThisState[DC__NUM_DPP__MAX]; 876 double DETBufferSizeCThisState[DC__NUM_DPP__MAX]; 877 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; 878 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 879 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; 880 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; 881 double UrgLatency[DC__VOLTAGE_STATES]; 882 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 883 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 884 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 885 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 886 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 887 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 888 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 889 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 890 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 891 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 892 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 893 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 894 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 895 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 896 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 897 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2]; 898 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2]; 899 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2]; 900 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2]; 901 double WritebackDelayTime[DC__NUM_DPP__MAX]; 902 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; 903 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; 904 unsigned int dummyinteger15; 905 unsigned int dummyinteger16; 906 unsigned int dummyinteger17; 907 unsigned int dummyinteger18; 908 unsigned int dummyinteger19; 909 unsigned int dummyinteger20; 910 unsigned int dummyinteger21; 911 unsigned int dummyinteger22; 912 unsigned int dummyinteger23; 913 unsigned int dummyinteger24; 914 unsigned int dummyinteger25; 915 unsigned int dummyinteger26; 916 unsigned int dummyinteger27; 917 unsigned int dummyinteger28; 918 unsigned int dummyinteger29; 919 bool dummystring[DC__NUM_DPP__MAX]; 920 double BPP; 921 enum odm_combine_policy ODMCombinePolicy; 922 bool UseMinimumRequiredDCFCLK; 923 bool ClampMinDCFCLK; 924 bool AllowDramClockChangeOneDisplayVactive; 925 926 }; 927 928 bool CalculateMinAndMaxPrefetchMode( 929 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, 930 unsigned int *MinPrefetchMode, 931 unsigned int *MaxPrefetchMode); 932 933 double CalculateWriteBackDISPCLK( 934 enum source_format_class WritebackPixelFormat, 935 double PixelClock, 936 double WritebackHRatio, 937 double WritebackVRatio, 938 unsigned int WritebackLumaHTaps, 939 unsigned int WritebackLumaVTaps, 940 unsigned int WritebackChromaHTaps, 941 unsigned int WritebackChromaVTaps, 942 double WritebackDestinationWidth, 943 unsigned int HTotal, 944 unsigned int WritebackChromaLineBufferWidth); 945 946 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ 947