1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dc_features.h"
27 #include "display_mode_enums.h"
28 
29 /**
30  * DOC: overview
31  *
32  * Most of the DML code is automatically generated and tested via hardware
33  * description language. Usually, we use the reference _vcs_dpi in the code
34  * where VCS means "Verilog Compiled Simulator" and DPI stands for "Direct
35  * Programmer Interface". In other words, those structs can be used to
36  * interface with Verilog with other languages such as C.
37  */
38 
39 #ifndef __DISPLAY_MODE_STRUCTS_H__
40 #define __DISPLAY_MODE_STRUCTS_H__
41 
42 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
43 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
44 typedef struct _vcs_dpi_ip_params_st ip_params_st;
45 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
46 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
47 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
48 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
49 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
50 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
51 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
52 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
53 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
54 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
55 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
56 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
57 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
58 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
59 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
60 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
61 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
62 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
63 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
64 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
65 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
66 
67 typedef struct {
68 	double UrgentWatermark;
69 	double WritebackUrgentWatermark;
70 	double DRAMClockChangeWatermark;
71 	double FCLKChangeWatermark;
72 	double WritebackDRAMClockChangeWatermark;
73 	double WritebackFCLKChangeWatermark;
74 	double StutterExitWatermark;
75 	double StutterEnterPlusExitWatermark;
76 	double Z8StutterExitWatermark;
77 	double Z8StutterEnterPlusExitWatermark;
78 	double USRRetrainingWatermark;
79 } Watermarks;
80 
81 typedef struct {
82 	double UrgentLatency;
83 	double ExtraLatency;
84 	double WritebackLatency;
85 	double DRAMClockChangeLatency;
86 	double FCLKChangeLatency;
87 	double SRExitTime;
88 	double SREnterPlusExitTime;
89 	double SRExitZ8Time;
90 	double SREnterPlusExitZ8Time;
91 	double USRRetrainingLatencyPlusSMNLatency;
92 } Latencies;
93 
94 typedef struct {
95 	double Dppclk;
96 	double Dispclk;
97 	double PixelClock;
98 	double DCFClkDeepSleep;
99 	unsigned int DPPPerSurface;
100 	bool ScalerEnabled;
101 	enum dm_rotation_angle SourceRotation;
102 	unsigned int ViewportHeight;
103 	unsigned int ViewportHeightChroma;
104 	unsigned int BlockWidth256BytesY;
105 	unsigned int BlockHeight256BytesY;
106 	unsigned int BlockWidth256BytesC;
107 	unsigned int BlockHeight256BytesC;
108 	unsigned int BlockWidthY;
109 	unsigned int BlockHeightY;
110 	unsigned int BlockWidthC;
111 	unsigned int BlockHeightC;
112 	unsigned int InterlaceEnable;
113 	unsigned int NumberOfCursors;
114 	unsigned int VBlank;
115 	unsigned int HTotal;
116 	unsigned int HActive;
117 	bool DCCEnable;
118 	enum odm_combine_mode ODMMode;
119 	enum source_format_class SourcePixelFormat;
120 	enum dm_swizzle_mode SurfaceTiling;
121 	unsigned int BytePerPixelY;
122 	unsigned int BytePerPixelC;
123 	bool ProgressiveToInterlaceUnitInOPP;
124 	double VRatio;
125 	double VRatioChroma;
126 	unsigned int VTaps;
127 	unsigned int VTapsChroma;
128 	unsigned int PitchY;
129 	unsigned int DCCMetaPitchY;
130 	unsigned int PitchC;
131 	unsigned int DCCMetaPitchC;
132 	bool ViewportStationary;
133 	unsigned int ViewportXStart;
134 	unsigned int ViewportYStart;
135 	unsigned int ViewportXStartC;
136 	unsigned int ViewportYStartC;
137 	bool FORCE_ONE_ROW_FOR_FRAME;
138 	unsigned int SwathHeightY;
139 	unsigned int SwathHeightC;
140 } DmlPipe;
141 
142 typedef struct {
143 	double UrgentLatency;
144 	double ExtraLatency;
145 	double WritebackLatency;
146 	double DRAMClockChangeLatency;
147 	double FCLKChangeLatency;
148 	double SRExitTime;
149 	double SREnterPlusExitTime;
150 	double SRExitZ8Time;
151 	double SREnterPlusExitZ8Time;
152 	double USRRetrainingLatency;
153 	double SMNLatency;
154 } SOCParametersList;
155 
156 struct _vcs_dpi_voltage_scaling_st {
157 	int state;
158 	double dscclk_mhz;
159 	double dcfclk_mhz;
160 	double socclk_mhz;
161 	double phyclk_d18_mhz;
162 	double phyclk_d32_mhz;
163 	double dram_speed_mts;
164 	double fabricclk_mhz;
165 	double dispclk_mhz;
166 	double dram_bw_per_chan_gbps;
167 	double phyclk_mhz;
168 	double dppclk_mhz;
169 	double dtbclk_mhz;
170 };
171 
172 /**
173  * _vcs_dpi_soc_bounding_box_st: SOC definitions
174  *
175  * This struct maintains the SOC Bounding Box information for the ASIC; it
176  * defines things such as clock, voltage, performance, etc. Usually, we load
177  * these values from VBIOS; if something goes wrong, we use some hard-coded
178  * values, which will enable the ASIC to light up with limitations.
179  */
180 struct _vcs_dpi_soc_bounding_box_st {
181 	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
182 	/**
183 	 * @num_states: It represents the total of Display Power Management
184 	 * (DPM) supported by the specific ASIC.
185 	 */
186 	unsigned int num_states;
187 	double sr_exit_time_us;
188 	double sr_enter_plus_exit_time_us;
189 	double sr_exit_z8_time_us;
190 	double sr_enter_plus_exit_z8_time_us;
191 	double urgent_latency_us;
192 	double urgent_latency_pixel_data_only_us;
193 	double urgent_latency_pixel_mixed_with_vm_data_us;
194 	double urgent_latency_vm_data_only_us;
195 	double usr_retraining_latency_us;
196 	double smn_latency_us;
197 	double fclk_change_latency_us;
198 	double mall_allocated_for_dcn_mbytes;
199 	double pct_ideal_fabric_bw_after_urgent;
200 	double pct_ideal_dram_bw_after_urgent_strobe;
201 	double max_avg_fabric_bw_use_normal_percent;
202 	double max_avg_dram_bw_use_normal_strobe_percent;
203 	enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
204 	bool dram_clock_change_requirement_final;
205 	double writeback_latency_us;
206 	double ideal_dram_bw_after_urgent_percent;
207 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
208 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
209 	double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
210 	double pct_ideal_sdp_bw_after_urgent;
211 	double max_avg_sdp_bw_use_normal_percent;
212 	double max_avg_dram_bw_use_normal_percent;
213 	unsigned int max_request_size_bytes;
214 	double downspread_percent;
215 	double dram_page_open_time_ns;
216 	double dram_rw_turnaround_time_ns;
217 	double dram_return_buffer_per_channel_bytes;
218 	double dram_channel_width_bytes;
219 	double fabric_datapath_to_dcn_data_return_bytes;
220 	double dcn_downspread_percent;
221 	double dispclk_dppclk_vco_speed_mhz;
222 	double dfs_vco_period_ps;
223 	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
224 	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
225 	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
226 	unsigned int round_trip_ping_latency_dcfclk_cycles;
227 	unsigned int urgent_out_of_order_return_per_channel_bytes;
228 	unsigned int channel_interleave_bytes;
229 	unsigned int num_banks;
230 	unsigned int num_chans;
231 	unsigned int vmm_page_size_bytes;
232 	unsigned int hostvm_min_page_size_bytes;
233 	unsigned int gpuvm_min_page_size_bytes;
234 	double dram_clock_change_latency_us;
235 	double dummy_pstate_latency_us;
236 	double writeback_dram_clock_change_latency_us;
237 	unsigned int return_bus_width_bytes;
238 	unsigned int voltage_override;
239 	double xfc_bus_transport_time_us;
240 	double xfc_xbuf_latency_tolerance_us;
241 	int use_urgent_burst_bw;
242 	double min_dcfclk;
243 	bool do_urgent_latency_adjustment;
244 	double urgent_latency_adjustment_fabric_clock_component_us;
245 	double urgent_latency_adjustment_fabric_clock_reference_mhz;
246 	bool disable_dram_clock_change_vactive_support;
247 	bool allow_dram_clock_one_display_vactive;
248 	enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
249 	double max_vratio_pre;
250 };
251 
252 /**
253  * @_vcs_dpi_ip_params_st: IP configuraion for DCN blocks
254  *
255  * In this struct you can find the DCN configuration associated to the specific
256  * ASIC. For example, here we can save how many DPPs the ASIC is using and it
257  * is available.
258  *
259  */
260 struct _vcs_dpi_ip_params_st {
261 	bool use_min_dcfclk;
262 	bool clamp_min_dcfclk;
263 	bool gpuvm_enable;
264 	bool hostvm_enable;
265 	bool dsc422_native_support;
266 	unsigned int gpuvm_max_page_table_levels;
267 	unsigned int hostvm_max_page_table_levels;
268 	unsigned int hostvm_cached_page_table_levels;
269 	unsigned int pte_group_size_bytes;
270 	unsigned int max_inter_dcn_tile_repeaters;
271 	unsigned int num_dsc;
272 	unsigned int odm_capable;
273 	unsigned int rob_buffer_size_kbytes;
274 	unsigned int det_buffer_size_kbytes;
275 	unsigned int min_comp_buffer_size_kbytes;
276 	unsigned int dpte_buffer_size_in_pte_reqs_luma;
277 	unsigned int dpte_buffer_size_in_pte_reqs_chroma;
278 	unsigned int pde_proc_buffer_size_64k_reqs;
279 	unsigned int dpp_output_buffer_pixels;
280 	unsigned int opp_output_buffer_lines;
281 	unsigned int pixel_chunk_size_kbytes;
282 	unsigned int alpha_pixel_chunk_size_kbytes;
283 	unsigned int min_pixel_chunk_size_bytes;
284 	unsigned int dcc_meta_buffer_size_bytes;
285 	unsigned char pte_enable;
286 	unsigned int pte_chunk_size_kbytes;
287 	unsigned int meta_chunk_size_kbytes;
288 	unsigned int min_meta_chunk_size_bytes;
289 	unsigned int writeback_chunk_size_kbytes;
290 	unsigned int line_buffer_size_bits;
291 	unsigned int max_line_buffer_lines;
292 	unsigned int writeback_luma_buffer_size_kbytes;
293 	unsigned int writeback_chroma_buffer_size_kbytes;
294 	unsigned int writeback_chroma_line_buffer_width_pixels;
295 
296 	unsigned int writeback_interface_buffer_size_kbytes;
297 	unsigned int writeback_line_buffer_buffer_size;
298 
299 	unsigned int writeback_10bpc420_supported;
300 	double writeback_max_hscl_ratio;
301 	double writeback_max_vscl_ratio;
302 	double writeback_min_hscl_ratio;
303 	double writeback_min_vscl_ratio;
304 	unsigned int maximum_dsc_bits_per_component;
305 	unsigned int maximum_pixels_per_line_per_dsc_unit;
306 	unsigned int writeback_max_hscl_taps;
307 	unsigned int writeback_max_vscl_taps;
308 	unsigned int writeback_line_buffer_luma_buffer_size;
309 	unsigned int writeback_line_buffer_chroma_buffer_size;
310 
311 	unsigned int max_page_table_levels;
312 	/**
313 	 * @max_num_dpp: Maximum number of DPP supported in the target ASIC.
314 	 */
315 	unsigned int max_num_dpp;
316 	unsigned int max_num_otg;
317 	unsigned int cursor_chunk_size;
318 	unsigned int cursor_buffer_size;
319 	unsigned int max_num_wb;
320 	unsigned int max_dchub_pscl_bw_pix_per_clk;
321 	unsigned int max_pscl_lb_bw_pix_per_clk;
322 	unsigned int max_lb_vscl_bw_pix_per_clk;
323 	unsigned int max_vscl_hscl_bw_pix_per_clk;
324 	double max_hscl_ratio;
325 	double max_vscl_ratio;
326 	unsigned int hscl_mults;
327 	unsigned int vscl_mults;
328 	unsigned int max_hscl_taps;
329 	unsigned int max_vscl_taps;
330 	unsigned int xfc_supported;
331 	unsigned int ptoi_supported;
332 	unsigned int gfx7_compat_tiling_supported;
333 
334 	bool odm_combine_4to1_supported;
335 	bool dynamic_metadata_vm_enabled;
336 	unsigned int max_num_hdmi_frl_outputs;
337 
338 	unsigned int xfc_fill_constant_bytes;
339 	double dispclk_ramp_margin_percent;
340 	double xfc_fill_bw_overhead_percent;
341 	double underscan_factor;
342 	unsigned int min_vblank_lines;
343 	unsigned int dppclk_delay_subtotal;
344 	unsigned int dispclk_delay_subtotal;
345 	double dcfclk_cstate_latency;
346 	unsigned int dppclk_delay_scl;
347 	unsigned int dppclk_delay_scl_lb_only;
348 	unsigned int dppclk_delay_cnvc_formatter;
349 	unsigned int dppclk_delay_cnvc_cursor;
350 	unsigned int is_line_buffer_bpp_fixed;
351 	unsigned int line_buffer_fixed_bpp;
352 	unsigned int dcc_supported;
353 	unsigned int config_return_buffer_size_in_kbytes;
354 	unsigned int compressed_buffer_segment_size_in_kbytes;
355 	unsigned int meta_fifo_size_in_kentries;
356 	unsigned int zero_size_buffer_entries;
357 	unsigned int compbuf_reserved_space_64b;
358 	unsigned int compbuf_reserved_space_zs;
359 
360 	unsigned int IsLineBufferBppFixed;
361 	unsigned int LineBufferFixedBpp;
362 	unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
363 	unsigned int bug_forcing_LC_req_same_size_fixed;
364 	unsigned int number_of_cursors;
365 	unsigned int max_num_dp2p0_outputs;
366 	unsigned int max_num_dp2p0_streams;
367 	unsigned int VBlankNomDefaultUS;
368 
369 	/* DM workarounds */
370 	double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
371 	double min_prefetch_in_strobe_us;
372 };
373 
374 struct _vcs_dpi_display_xfc_params_st {
375 	double xfc_tslv_vready_offset_us;
376 	double xfc_tslv_vupdate_width_us;
377 	double xfc_tslv_vupdate_offset_us;
378 	int xfc_slv_chunk_size_bytes;
379 };
380 
381 struct _vcs_dpi_display_pipe_source_params_st {
382 	int source_format;
383 	double dcc_fraction_of_zs_req_luma;
384 	double dcc_fraction_of_zs_req_chroma;
385 	unsigned char dcc;
386 	unsigned int dcc_rate;
387 	unsigned int dcc_rate_chroma;
388 	unsigned char dcc_use_global;
389 	unsigned char vm;
390 	bool unbounded_req_mode;
391 	bool gpuvm;    // gpuvm enabled
392 	bool hostvm;    // hostvm enabled
393 	bool gpuvm_levels_force_en;
394 	unsigned int gpuvm_levels_force;
395 	bool hostvm_levels_force_en;
396 	unsigned int hostvm_levels_force;
397 	int source_scan;
398 	int source_rotation; // new in dml32
399 	unsigned int det_size_override; // use to populate DETSizeOverride in vba struct
400 	int sw_mode;
401 	int macro_tile_size;
402 	unsigned int surface_width_y;
403 	unsigned int surface_height_y;
404 	unsigned int surface_width_c;
405 	unsigned int surface_height_c;
406 	unsigned int viewport_width;
407 	unsigned int viewport_height;
408 	unsigned int viewport_y_y;
409 	unsigned int viewport_y_c;
410 	unsigned int viewport_width_c;
411 	unsigned int viewport_height_c;
412 	unsigned int viewport_width_max;
413 	unsigned int viewport_height_max;
414 	unsigned int viewport_x_y;
415 	unsigned int viewport_x_c;
416 	bool viewport_stationary;
417 	unsigned int dcc_rate_luma;
418 	unsigned int gpuvm_min_page_size_kbytes;
419 	unsigned int use_mall_for_pstate_change;
420 	unsigned int use_mall_for_static_screen;
421 	bool force_one_row_for_frame;
422 	bool pte_buffer_mode;
423 	unsigned int data_pitch;
424 	unsigned int data_pitch_c;
425 	unsigned int meta_pitch;
426 	unsigned int meta_pitch_c;
427 	unsigned int cur0_src_width;
428 	int cur0_bpp;
429 	unsigned int cur1_src_width;
430 	int cur1_bpp;
431 	int num_cursors;
432 	unsigned char is_hsplit;
433 	unsigned char dynamic_metadata_enable;
434 	unsigned int dynamic_metadata_lines_before_active;
435 	unsigned int dynamic_metadata_xmit_bytes;
436 	unsigned int hsplit_grp;
437 	unsigned char xfc_enable;
438 	unsigned char xfc_slave;
439 	unsigned char immediate_flip;
440 	struct _vcs_dpi_display_xfc_params_st xfc_params;
441 	//for vstartuplines calculation freesync
442 	unsigned char v_total_min;
443 	unsigned char v_total_max;
444 };
445 struct writeback_st {
446 	int wb_src_height;
447 	int wb_src_width;
448 	int wb_dst_width;
449 	int wb_dst_height;
450 	int wb_pixel_format;
451 	int wb_htaps_luma;
452 	int wb_vtaps_luma;
453 	int wb_htaps_chroma;
454 	int wb_vtaps_chroma;
455 	unsigned int wb_htaps;
456 	unsigned int wb_vtaps;
457 	double wb_hratio;
458 	double wb_vratio;
459 };
460 
461 struct display_audio_params_st {
462 	unsigned int   audio_sample_rate_khz;
463 	int    		   audio_sample_layout;
464 };
465 
466 struct _vcs_dpi_display_output_params_st {
467 	int dp_lanes;
468 	double output_bpp;
469 	unsigned int dsc_input_bpc;
470 	int dsc_enable;
471 	int wb_enable;
472 	int num_active_wb;
473 	int output_type;
474 	int is_virtual;
475 	int output_format;
476 	int dsc_slices;
477 	int max_audio_sample_rate;
478 	struct writeback_st wb;
479 	struct display_audio_params_st audio;
480 	unsigned int output_bpc;
481 	int dp_rate;
482 	unsigned int dp_multistream_id;
483 	bool dp_multistream_en;
484 };
485 
486 struct _vcs_dpi_scaler_ratio_depth_st {
487 	double hscl_ratio;
488 	double vscl_ratio;
489 	double hscl_ratio_c;
490 	double vscl_ratio_c;
491 	double vinit;
492 	double vinit_c;
493 	double vinit_bot;
494 	double vinit_bot_c;
495 	int lb_depth;
496 	int scl_enable;
497 };
498 
499 struct _vcs_dpi_scaler_taps_st {
500 	unsigned int htaps;
501 	unsigned int vtaps;
502 	unsigned int htaps_c;
503 	unsigned int vtaps_c;
504 };
505 
506 struct _vcs_dpi_display_pipe_dest_params_st {
507 	unsigned int recout_width;
508 	unsigned int recout_height;
509 	unsigned int full_recout_width;
510 	unsigned int full_recout_height;
511 	unsigned int hblank_start;
512 	unsigned int hblank_end;
513 	unsigned int vblank_start;
514 	unsigned int vblank_end;
515 	unsigned int htotal;
516 	unsigned int vtotal;
517 	unsigned int vfront_porch;
518 	unsigned int vblank_nom;
519 	unsigned int vactive;
520 	unsigned int hactive;
521 	unsigned int vstartup_start;
522 	unsigned int vupdate_offset;
523 	unsigned int vupdate_width;
524 	unsigned int vready_offset;
525 	unsigned char interlaced;
526 	double pixel_rate_mhz;
527 	unsigned char synchronized_vblank_all_planes;
528 	unsigned char otg_inst;
529 	unsigned int odm_combine;
530 	unsigned char use_maximum_vstartup;
531 	unsigned int vtotal_max;
532 	unsigned int vtotal_min;
533 	unsigned int refresh_rate;
534 	bool synchronize_timings;
535 	unsigned int odm_combine_policy;
536 	bool drr_display;
537 };
538 
539 struct _vcs_dpi_display_pipe_params_st {
540 	display_pipe_source_params_st src;
541 	display_pipe_dest_params_st dest;
542 	scaler_ratio_depth_st scale_ratio_depth;
543 	scaler_taps_st scale_taps;
544 };
545 
546 struct _vcs_dpi_display_clocks_and_cfg_st {
547 	int voltage;
548 	double dppclk_mhz;
549 	double refclk_mhz;
550 	double dispclk_mhz;
551 	double dcfclk_mhz;
552 	double socclk_mhz;
553 };
554 
555 struct _vcs_dpi_display_e2e_pipe_params_st {
556 	display_pipe_params_st pipe;
557 	display_output_params_st dout;
558 	display_clocks_and_cfg_st clks_cfg;
559 };
560 
561 struct _vcs_dpi_display_data_rq_misc_params_st {
562 	unsigned int full_swath_bytes;
563 	unsigned int stored_swath_bytes;
564 	unsigned int blk256_height;
565 	unsigned int blk256_width;
566 	unsigned int req_height;
567 	unsigned int req_width;
568 };
569 
570 struct _vcs_dpi_display_data_rq_sizing_params_st {
571 	unsigned int chunk_bytes;
572 	unsigned int min_chunk_bytes;
573 	unsigned int meta_chunk_bytes;
574 	unsigned int min_meta_chunk_bytes;
575 	unsigned int mpte_group_bytes;
576 	unsigned int dpte_group_bytes;
577 };
578 
579 struct _vcs_dpi_display_data_rq_dlg_params_st {
580 	unsigned int swath_width_ub;
581 	unsigned int swath_height;
582 	unsigned int req_per_swath_ub;
583 	unsigned int meta_pte_bytes_per_frame_ub;
584 	unsigned int dpte_req_per_row_ub;
585 	unsigned int dpte_groups_per_row_ub;
586 	unsigned int dpte_row_height;
587 	unsigned int dpte_bytes_per_row_ub;
588 	unsigned int meta_chunks_per_row_ub;
589 	unsigned int meta_req_per_row_ub;
590 	unsigned int meta_row_height;
591 	unsigned int meta_bytes_per_row_ub;
592 };
593 
594 struct _vcs_dpi_display_rq_dlg_params_st {
595 	display_data_rq_dlg_params_st rq_l;
596 	display_data_rq_dlg_params_st rq_c;
597 };
598 
599 struct _vcs_dpi_display_rq_sizing_params_st {
600 	display_data_rq_sizing_params_st rq_l;
601 	display_data_rq_sizing_params_st rq_c;
602 };
603 
604 struct _vcs_dpi_display_rq_misc_params_st {
605 	display_data_rq_misc_params_st rq_l;
606 	display_data_rq_misc_params_st rq_c;
607 };
608 
609 struct _vcs_dpi_display_rq_params_st {
610 	unsigned char yuv420;
611 	unsigned char yuv420_10bpc;
612 	unsigned char rgbe_alpha;
613 	display_rq_misc_params_st misc;
614 	display_rq_sizing_params_st sizing;
615 	display_rq_dlg_params_st dlg;
616 };
617 
618 struct _vcs_dpi_display_dlg_regs_st {
619 	unsigned int refcyc_h_blank_end;
620 	unsigned int dlg_vblank_end;
621 	unsigned int min_dst_y_next_start;
622 	unsigned int optimized_min_dst_y_next_start;
623 	unsigned int optimized_min_dst_y_next_start_us;
624 	unsigned int refcyc_per_htotal;
625 	unsigned int refcyc_x_after_scaler;
626 	unsigned int dst_y_after_scaler;
627 	unsigned int dst_y_prefetch;
628 	unsigned int dst_y_per_vm_vblank;
629 	unsigned int dst_y_per_row_vblank;
630 	unsigned int dst_y_per_vm_flip;
631 	unsigned int dst_y_per_row_flip;
632 	unsigned int ref_freq_to_pix_freq;
633 	unsigned int vratio_prefetch;
634 	unsigned int vratio_prefetch_c;
635 	unsigned int refcyc_per_pte_group_vblank_l;
636 	unsigned int refcyc_per_pte_group_vblank_c;
637 	unsigned int refcyc_per_meta_chunk_vblank_l;
638 	unsigned int refcyc_per_meta_chunk_vblank_c;
639 	unsigned int refcyc_per_pte_group_flip_l;
640 	unsigned int refcyc_per_pte_group_flip_c;
641 	unsigned int refcyc_per_meta_chunk_flip_l;
642 	unsigned int refcyc_per_meta_chunk_flip_c;
643 	unsigned int dst_y_per_pte_row_nom_l;
644 	unsigned int dst_y_per_pte_row_nom_c;
645 	unsigned int refcyc_per_pte_group_nom_l;
646 	unsigned int refcyc_per_pte_group_nom_c;
647 	unsigned int dst_y_per_meta_row_nom_l;
648 	unsigned int dst_y_per_meta_row_nom_c;
649 	unsigned int refcyc_per_meta_chunk_nom_l;
650 	unsigned int refcyc_per_meta_chunk_nom_c;
651 	unsigned int refcyc_per_line_delivery_pre_l;
652 	unsigned int refcyc_per_line_delivery_pre_c;
653 	unsigned int refcyc_per_line_delivery_l;
654 	unsigned int refcyc_per_line_delivery_c;
655 	unsigned int chunk_hdl_adjust_cur0;
656 	unsigned int chunk_hdl_adjust_cur1;
657 	unsigned int vready_after_vcount0;
658 	unsigned int dst_y_offset_cur0;
659 	unsigned int dst_y_offset_cur1;
660 	unsigned int xfc_reg_transfer_delay;
661 	unsigned int xfc_reg_precharge_delay;
662 	unsigned int xfc_reg_remote_surface_flip_latency;
663 	unsigned int xfc_reg_prefetch_margin;
664 	unsigned int dst_y_delta_drq_limit;
665 	unsigned int refcyc_per_vm_group_vblank;
666 	unsigned int refcyc_per_vm_group_flip;
667 	unsigned int refcyc_per_vm_req_vblank;
668 	unsigned int refcyc_per_vm_req_flip;
669 	unsigned int refcyc_per_vm_dmdata;
670 	unsigned int dmdata_dl_delta;
671 };
672 
673 struct _vcs_dpi_display_ttu_regs_st {
674 	unsigned int qos_level_low_wm;
675 	unsigned int qos_level_high_wm;
676 	unsigned int min_ttu_vblank;
677 	unsigned int qos_level_flip;
678 	unsigned int refcyc_per_req_delivery_l;
679 	unsigned int refcyc_per_req_delivery_c;
680 	unsigned int refcyc_per_req_delivery_cur0;
681 	unsigned int refcyc_per_req_delivery_cur1;
682 	unsigned int refcyc_per_req_delivery_pre_l;
683 	unsigned int refcyc_per_req_delivery_pre_c;
684 	unsigned int refcyc_per_req_delivery_pre_cur0;
685 	unsigned int refcyc_per_req_delivery_pre_cur1;
686 	unsigned int qos_level_fixed_l;
687 	unsigned int qos_level_fixed_c;
688 	unsigned int qos_level_fixed_cur0;
689 	unsigned int qos_level_fixed_cur1;
690 	unsigned int qos_ramp_disable_l;
691 	unsigned int qos_ramp_disable_c;
692 	unsigned int qos_ramp_disable_cur0;
693 	unsigned int qos_ramp_disable_cur1;
694 };
695 
696 struct _vcs_dpi_display_data_rq_regs_st {
697 	unsigned int chunk_size;
698 	unsigned int min_chunk_size;
699 	unsigned int meta_chunk_size;
700 	unsigned int min_meta_chunk_size;
701 	unsigned int dpte_group_size;
702 	unsigned int mpte_group_size;
703 	unsigned int swath_height;
704 	unsigned int pte_row_height_linear;
705 };
706 
707 struct _vcs_dpi_display_rq_regs_st {
708 	display_data_rq_regs_st rq_regs_l;
709 	display_data_rq_regs_st rq_regs_c;
710 	unsigned int drq_expansion_mode;
711 	unsigned int prq_expansion_mode;
712 	unsigned int mrq_expansion_mode;
713 	unsigned int crq_expansion_mode;
714 	unsigned int plane1_base_address;
715 	unsigned int aperture_low_addr;   // bits [47:18]
716 	unsigned int aperture_high_addr;  // bits [47:18]
717 };
718 
719 struct _vcs_dpi_display_dlg_sys_params_st {
720 	double t_mclk_wm_us;
721 	double t_urg_wm_us;
722 	double t_sr_wm_us;
723 	double t_extra_us;
724 	double mem_trip_us;
725 	double deepsleep_dcfclk_mhz;
726 	double total_flip_bw;
727 	unsigned int total_flip_bytes;
728 };
729 
730 struct _vcs_dpi_display_arb_params_st {
731 	int max_req_outstanding;
732 	int min_req_outstanding;
733 	int sat_level_us;
734 	int hvm_min_req_outstand_commit_threshold;
735 	int hvm_max_qos_commit_threshold;
736 	int compbuf_reserved_space_kbytes;
737 };
738 
739 #endif /*__DISPLAY_MODE_STRUCTS_H__*/
740