1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef __DISPLAY_MODE_ENUMS_H__
26 #define __DISPLAY_MODE_ENUMS_H__
27 
28 enum output_encoder_class {
29 	dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
30 };
31 enum output_format_class {
32 	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
33 };
34 enum source_format_class {
35 	dm_444_16 = 0,
36 	dm_444_32 = 1,
37 	dm_444_64 = 2,
38 	dm_420_8 = 3,
39 	dm_420_10 = 4,
40 	dm_420_12 = 5,
41 	dm_422_8 = 6,
42 	dm_422_10 = 7,
43 	dm_444_8 = 8,
44 	dm_mono_8 = dm_444_8,
45 	dm_mono_16 = dm_444_16,
46 	dm_rgbe = 9,
47 	dm_rgbe_alpha = 10,
48 };
49 enum output_bpc_class {
50 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
51 };
52 enum scan_direction_class {
53 	dm_horz = 0, dm_vert = 1
54 };
55 enum dm_swizzle_mode {
56 	dm_sw_linear = 0,
57 	dm_sw_256b_s = 1,
58 	dm_sw_256b_d = 2,
59 	dm_sw_SPARE_0 = 3,
60 	dm_sw_SPARE_1 = 4,
61 	dm_sw_4kb_s = 5,
62 	dm_sw_4kb_d = 6,
63 	dm_sw_SPARE_2 = 7,
64 	dm_sw_SPARE_3 = 8,
65 	dm_sw_64kb_s = 9,
66 	dm_sw_64kb_d = 10,
67 	dm_sw_SPARE_4 = 11,
68 	dm_sw_SPARE_5 = 12,
69 	dm_sw_var_s = 13,
70 	dm_sw_var_d = 14,
71 	dm_sw_SPARE_6 = 15,
72 	dm_sw_SPARE_7 = 16,
73 	dm_sw_64kb_s_t = 17,
74 	dm_sw_64kb_d_t = 18,
75 	dm_sw_SPARE_10 = 19,
76 	dm_sw_SPARE_11 = 20,
77 	dm_sw_4kb_s_x = 21,
78 	dm_sw_4kb_d_x = 22,
79 	dm_sw_SPARE_12 = 23,
80 	dm_sw_SPARE_13 = 24,
81 	dm_sw_64kb_s_x = 25,
82 	dm_sw_64kb_d_x = 26,
83 	dm_sw_64kb_r_x = 27,
84 	dm_sw_SPARE_15 = 28,
85 	dm_sw_var_s_x = 29,
86 	dm_sw_var_d_x = 30,
87 	dm_sw_var_r_x = 31,
88 	dm_sw_gfx7_2d_thin_l_vp,
89 	dm_sw_gfx7_2d_thin_gl,
90 };
91 enum lb_depth {
92 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
93 	dm_lb_19 = 5
94 };
95 enum voltage_state {
96 	dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
97 };
98 enum source_macro_tile_size {
99 	dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
100 };
101 enum cursor_bpp {
102 	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
103 };
104 enum clock_change_support {
105 	dm_dram_clock_change_uninitialized = 0,
106 	dm_dram_clock_change_vactive,
107 	dm_dram_clock_change_vblank,
108 	dm_dram_clock_change_unsupported
109 };
110 
111 enum output_standard {
112 	dm_std_uninitialized = 0,
113 	dm_std_cvtr2,
114 	dm_std_cvt
115 };
116 
117 enum mpc_combine_affinity {
118 	dm_mpc_always_when_possible,
119 	dm_mpc_reduce_voltage,
120 	dm_mpc_reduce_voltage_and_clocks,
121 	dm_mpc_never
122 };
123 
124 enum RequestType {
125 	REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
126 };
127 
128 enum self_refresh_affinity {
129 	dm_try_to_allow_self_refresh_and_mclk_switch,
130 	dm_allow_self_refresh_and_mclk_switch,
131 	dm_allow_self_refresh,
132 	dm_neither_self_refresh_nor_mclk_switch
133 };
134 
135 enum dm_validation_status {
136 	DML_VALIDATION_OK,
137 	DML_FAIL_SCALE_RATIO_TAP,
138 	DML_FAIL_SOURCE_PIXEL_FORMAT,
139 	DML_FAIL_VIEWPORT_SIZE,
140 	DML_FAIL_TOTAL_V_ACTIVE_BW,
141 	DML_FAIL_DIO_SUPPORT,
142 	DML_FAIL_NOT_ENOUGH_DSC,
143 	DML_FAIL_DSC_CLK_REQUIRED,
144 	DML_FAIL_DSC_VALIDATION_FAILURE,
145 	DML_FAIL_URGENT_LATENCY,
146 	DML_FAIL_REORDERING_BUFFER,
147 	DML_FAIL_DISPCLK_DPPCLK,
148 	DML_FAIL_TOTAL_AVAILABLE_PIPES,
149 	DML_FAIL_NUM_OTG,
150 	DML_FAIL_WRITEBACK_MODE,
151 	DML_FAIL_WRITEBACK_LATENCY,
152 	DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
153 	DML_FAIL_CURSOR_SUPPORT,
154 	DML_FAIL_PITCH_SUPPORT,
155 	DML_FAIL_PTE_BUFFER_SIZE,
156 	DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
157 	DML_FAIL_DSC_INPUT_BPC,
158 	DML_FAIL_PREFETCH_SUPPORT,
159 	DML_FAIL_V_RATIO_PREFETCH,
160 };
161 
162 enum writeback_config {
163 	dm_normal,
164 	dm_whole_buffer_for_single_stream_no_interleave,
165 	dm_whole_buffer_for_single_stream_interleave,
166 };
167 
168 enum odm_combine_mode {
169 	dm_odm_combine_mode_disabled,
170 	dm_odm_combine_mode_2to1,
171 	dm_odm_combine_mode_4to1,
172 };
173 
174 enum odm_combine_policy {
175 	dm_odm_combine_policy_dal,
176 	dm_odm_combine_policy_none,
177 	dm_odm_combine_policy_2to1,
178 	dm_odm_combine_policy_4to1,
179 };
180 
181 enum immediate_flip_requirement {
182 	dm_immediate_flip_not_required,
183 	dm_immediate_flip_required,
184 };
185 
186 enum unbounded_requesting_policy {
187 	dm_unbounded_requesting,
188 	dm_unbounded_requesting_edp_only,
189 	dm_unbounded_requesting_disable
190 };
191 
192 #endif
193