1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "clk_mgr.h" 28 #include "resource.h" 29 #include "dcn321_fpu.h" 30 #include "dcn32/dcn32_resource.h" 31 #include "dcn321/dcn321_resource.h" 32 #include "dml/dcn32/display_mode_vba_util_32.h" 33 34 #define DCN3_2_DEFAULT_DET_SIZE 256 35 36 struct _vcs_dpi_ip_params_st dcn3_21_ip = { 37 .gpuvm_enable = 0, 38 .gpuvm_max_page_table_levels = 4, 39 .hostvm_enable = 0, 40 .rob_buffer_size_kbytes = 128, 41 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 42 .config_return_buffer_size_in_kbytes = 1280, 43 .compressed_buffer_segment_size_in_kbytes = 64, 44 .meta_fifo_size_in_kentries = 22, 45 .zero_size_buffer_entries = 512, 46 .compbuf_reserved_space_64b = 256, 47 .compbuf_reserved_space_zs = 64, 48 .dpp_output_buffer_pixels = 2560, 49 .opp_output_buffer_lines = 1, 50 .pixel_chunk_size_kbytes = 8, 51 .alpha_pixel_chunk_size_kbytes = 4, 52 .min_pixel_chunk_size_bytes = 1024, 53 .dcc_meta_buffer_size_bytes = 6272, 54 .meta_chunk_size_kbytes = 2, 55 .min_meta_chunk_size_bytes = 256, 56 .writeback_chunk_size_kbytes = 8, 57 .ptoi_supported = false, 58 .num_dsc = 4, 59 .maximum_dsc_bits_per_component = 12, 60 .maximum_pixels_per_line_per_dsc_unit = 6016, 61 .dsc422_native_support = true, 62 .is_line_buffer_bpp_fixed = true, 63 .line_buffer_fixed_bpp = 57, 64 .line_buffer_size_bits = 1171920, 65 .max_line_buffer_lines = 32, 66 .writeback_interface_buffer_size_kbytes = 90, 67 .max_num_dpp = 4, 68 .max_num_otg = 4, 69 .max_num_hdmi_frl_outputs = 1, 70 .max_num_wb = 1, 71 .max_dchub_pscl_bw_pix_per_clk = 4, 72 .max_pscl_lb_bw_pix_per_clk = 2, 73 .max_lb_vscl_bw_pix_per_clk = 4, 74 .max_vscl_hscl_bw_pix_per_clk = 4, 75 .max_hscl_ratio = 6, 76 .max_vscl_ratio = 6, 77 .max_hscl_taps = 8, 78 .max_vscl_taps = 8, 79 .dpte_buffer_size_in_pte_reqs_luma = 64, 80 .dpte_buffer_size_in_pte_reqs_chroma = 34, 81 .dispclk_ramp_margin_percent = 1, 82 .max_inter_dcn_tile_repeaters = 8, 83 .cursor_buffer_size = 16, 84 .cursor_chunk_size = 2, 85 .writeback_line_buffer_buffer_size = 0, 86 .writeback_min_hscl_ratio = 1, 87 .writeback_min_vscl_ratio = 1, 88 .writeback_max_hscl_ratio = 1, 89 .writeback_max_vscl_ratio = 1, 90 .writeback_max_hscl_taps = 1, 91 .writeback_max_vscl_taps = 1, 92 .dppclk_delay_subtotal = 47, 93 .dppclk_delay_scl = 50, 94 .dppclk_delay_scl_lb_only = 16, 95 .dppclk_delay_cnvc_formatter = 28, 96 .dppclk_delay_cnvc_cursor = 6, 97 .dispclk_delay_subtotal = 125, 98 .dynamic_metadata_vm_enabled = false, 99 .odm_combine_4to1_supported = false, 100 .dcc_supported = true, 101 .max_num_dp2p0_outputs = 2, 102 .max_num_dp2p0_streams = 4, 103 }; 104 105 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 106 .clock_limits = { 107 { 108 .state = 0, 109 .dcfclk_mhz = 1434.0, 110 .fabricclk_mhz = 2250.0, 111 .dispclk_mhz = 1720.0, 112 .dppclk_mhz = 1720.0, 113 .phyclk_mhz = 810.0, 114 .phyclk_d18_mhz = 667.0, 115 .phyclk_d32_mhz = 313.0, 116 .socclk_mhz = 1200.0, 117 .dscclk_mhz = 573.333, 118 .dram_speed_mts = 16000.0, 119 .dtbclk_mhz = 1564.0, 120 }, 121 }, 122 .num_states = 1, 123 .sr_exit_time_us = 19.95, 124 .sr_enter_plus_exit_time_us = 24.36, 125 .sr_exit_z8_time_us = 285.0, 126 .sr_enter_plus_exit_z8_time_us = 320, 127 .writeback_latency_us = 12.0, 128 .round_trip_ping_latency_dcfclk_cycles = 207, 129 .urgent_latency_pixel_data_only_us = 4, 130 .urgent_latency_pixel_mixed_with_vm_data_us = 4, 131 .urgent_latency_vm_data_only_us = 4, 132 .fclk_change_latency_us = 7, 133 .usr_retraining_latency_us = 0, 134 .smn_latency_us = 0, 135 .mall_allocated_for_dcn_mbytes = 32, 136 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 137 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 138 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 139 .pct_ideal_sdp_bw_after_urgent = 90.0, 140 .pct_ideal_fabric_bw_after_urgent = 67.0, 141 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 142 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 143 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 144 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 145 .max_avg_sdp_bw_use_normal_percent = 80.0, 146 .max_avg_fabric_bw_use_normal_percent = 60.0, 147 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 148 .max_avg_dram_bw_use_normal_percent = 15.0, 149 .num_chans = 8, 150 .dram_channel_width_bytes = 2, 151 .fabric_datapath_to_dcn_data_return_bytes = 64, 152 .return_bus_width_bytes = 64, 153 .downspread_percent = 0.38, 154 .dcn_downspread_percent = 0.5, 155 .dram_clock_change_latency_us = 400, 156 .dispclk_dppclk_vco_speed_mhz = 4300.0, 157 .do_urgent_latency_adjustment = true, 158 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 159 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, 160 }; 161 162 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 163 { 164 if (entry->dcfclk_mhz > 0) { 165 float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 166 167 entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * 169 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 170 } else if (entry->fabricclk_mhz > 0) { 171 float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 172 173 entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * 175 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 176 } else if (entry->dram_speed_mts > 0) { 177 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * 178 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 179 180 entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 181 entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 182 } 183 } 184 185 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 186 { 187 float memory_bw_kbytes_sec; 188 float fabric_bw_kbytes_sec; 189 float sdp_bw_kbytes_sec; 190 float limiting_bw_kbytes_sec; 191 192 memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * 193 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 194 195 fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 196 197 sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 198 199 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 200 201 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 202 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 203 204 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 205 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 206 207 return limiting_bw_kbytes_sec; 208 } 209 210 void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 211 unsigned int *num_entries, 212 struct _vcs_dpi_voltage_scaling_st *entry) 213 { 214 int i = 0; 215 int index = 0; 216 float net_bw_of_new_state = 0; 217 218 dc_assert_fp_enabled(); 219 220 get_optimal_ntuple(entry); 221 222 if (*num_entries == 0) { 223 table[0] = *entry; 224 (*num_entries)++; 225 } else { 226 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 227 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 228 index++; 229 if (index >= *num_entries) 230 break; 231 } 232 233 for (i = *num_entries; i > index; i--) 234 table[i] = table[i - 1]; 235 236 table[index] = *entry; 237 (*num_entries)++; 238 } 239 } 240 241 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 242 unsigned int index) 243 { 244 int i; 245 246 if (*num_entries == 0) 247 return; 248 249 for (i = index; i < *num_entries - 1; i++) { 250 table[i] = table[i + 1]; 251 } 252 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 253 } 254 255 static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 256 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 257 { 258 int i, j; 259 struct _vcs_dpi_voltage_scaling_st entry = {0}; 260 261 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 262 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 263 264 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 265 266 static const unsigned int num_dcfclk_stas = 5; 267 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 268 269 unsigned int num_uclk_dpms = 0; 270 unsigned int num_fclk_dpms = 0; 271 unsigned int num_dcfclk_dpms = 0; 272 273 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 274 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 275 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 276 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 277 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 278 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 279 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 280 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 281 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 282 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 283 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 284 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 285 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 286 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 287 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 288 289 if (bw_params->clk_table.entries[i].memclk_mhz > 0) 290 num_uclk_dpms++; 291 if (bw_params->clk_table.entries[i].fclk_mhz > 0) 292 num_fclk_dpms++; 293 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 294 num_dcfclk_dpms++; 295 } 296 297 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) 298 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; 299 300 if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 301 return -1; 302 303 if (max_dppclk_mhz == 0) 304 max_dppclk_mhz = max_dispclk_mhz; 305 306 if (max_fclk_mhz == 0) 307 max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; 308 309 if (max_phyclk_mhz == 0) 310 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 311 312 *num_entries = 0; 313 entry.dispclk_mhz = max_dispclk_mhz; 314 entry.dscclk_mhz = max_dispclk_mhz / 3; 315 entry.dppclk_mhz = max_dppclk_mhz; 316 entry.dtbclk_mhz = max_dtbclk_mhz; 317 entry.phyclk_mhz = max_phyclk_mhz; 318 entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 319 entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 320 321 // Insert all the DCFCLK STAs 322 for (i = 0; i < num_dcfclk_stas; i++) { 323 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 324 entry.fabricclk_mhz = 0; 325 entry.dram_speed_mts = 0; 326 327 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 328 } 329 330 // Insert the max DCFCLK 331 entry.dcfclk_mhz = max_dcfclk_mhz; 332 entry.fabricclk_mhz = 0; 333 entry.dram_speed_mts = 0; 334 335 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 336 337 // Insert the UCLK DPMS 338 for (i = 0; i < num_uclk_dpms; i++) { 339 entry.dcfclk_mhz = 0; 340 entry.fabricclk_mhz = 0; 341 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 342 343 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 344 } 345 346 // If FCLK is coarse grained, insert individual DPMs. 347 if (num_fclk_dpms > 2) { 348 for (i = 0; i < num_fclk_dpms; i++) { 349 entry.dcfclk_mhz = 0; 350 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 351 entry.dram_speed_mts = 0; 352 353 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 354 } 355 } 356 // If FCLK fine grained, only insert max 357 else { 358 entry.dcfclk_mhz = 0; 359 entry.fabricclk_mhz = max_fclk_mhz; 360 entry.dram_speed_mts = 0; 361 362 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 363 } 364 365 // At this point, the table contains all "points of interest" based on 366 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 367 // ratios (by derate, are exact). 368 369 // Remove states that require higher clocks than are supported 370 for (i = *num_entries - 1; i >= 0 ; i--) { 371 if (table[i].dcfclk_mhz > max_dcfclk_mhz || 372 table[i].fabricclk_mhz > max_fclk_mhz || 373 table[i].dram_speed_mts > max_uclk_mhz * 16) 374 remove_entry_from_table_at_index(table, num_entries, i); 375 } 376 377 // At this point, the table only contains supported points of interest 378 // it could be used as is, but some states may be redundant due to 379 // coarse grained nature of some clocks, so we want to round up to 380 // coarse grained DPMs and remove duplicates. 381 382 // Round up UCLKs 383 for (i = *num_entries - 1; i >= 0 ; i--) { 384 for (j = 0; j < num_uclk_dpms; j++) { 385 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 386 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 387 break; 388 } 389 } 390 } 391 392 // If FCLK is coarse grained, round up to next DPMs 393 if (num_fclk_dpms > 2) { 394 for (i = *num_entries - 1; i >= 0 ; i--) { 395 for (j = 0; j < num_fclk_dpms; j++) { 396 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 397 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 398 break; 399 } 400 } 401 } 402 } 403 // Otherwise, round up to minimum. 404 else { 405 for (i = *num_entries - 1; i >= 0 ; i--) { 406 if (table[i].fabricclk_mhz < min_fclk_mhz) { 407 table[i].fabricclk_mhz = min_fclk_mhz; 408 } 409 } 410 } 411 412 // Round DCFCLKs up to minimum 413 for (i = *num_entries - 1; i >= 0 ; i--) { 414 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 415 table[i].dcfclk_mhz = min_dcfclk_mhz; 416 } 417 } 418 419 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 420 i = 0; 421 while (i < *num_entries - 1) { 422 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 423 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 424 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 425 remove_entry_from_table_at_index(table, num_entries, i + 1); 426 else 427 i++; 428 } 429 430 // Fix up the state indicies 431 for (i = *num_entries - 1; i >= 0 ; i--) { 432 table[i].state = i; 433 } 434 435 return 0; 436 } 437 438 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 439 unsigned int *optimal_dcfclk, 440 unsigned int *optimal_fclk) 441 { 442 double bw_from_dram, bw_from_dram1, bw_from_dram2; 443 444 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * 445 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); 446 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * 447 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); 448 449 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 450 451 if (optimal_fclk) 452 *optimal_fclk = bw_from_dram / 453 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 454 455 if (optimal_dcfclk) 456 *optimal_dcfclk = bw_from_dram / 457 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 458 } 459 460 /** dcn321_update_bw_bounding_box 461 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet 462 * with actual values as per dGPU SKU: 463 * -with passed few options from dc->config 464 * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) 465 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes 466 * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU 467 * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) 468 * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different 469 * clocks (which might differ for certain dGPU SKU of the same ASIC) 470 */ 471 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 472 { 473 dc_assert_fp_enabled(); 474 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 475 /* Overrides from dc->config options */ 476 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 477 478 /* Override from passed dc->bb_overrides if available*/ 479 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 480 && dc->bb_overrides.sr_exit_time_ns) { 481 dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 482 } 483 484 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) 485 != dc->bb_overrides.sr_enter_plus_exit_time_ns 486 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 487 dcn3_21_soc.sr_enter_plus_exit_time_us = 488 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 489 } 490 491 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 492 && dc->bb_overrides.urgent_latency_ns) { 493 dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 494 dcn3_21_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 495 } 496 497 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) 498 != dc->bb_overrides.dram_clock_change_latency_ns 499 && dc->bb_overrides.dram_clock_change_latency_ns) { 500 dcn3_21_soc.dram_clock_change_latency_us = 501 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 502 } 503 504 if ((int)(dcn3_21_soc.fclk_change_latency_us * 1000) 505 != dc->bb_overrides.fclk_clock_change_latency_ns 506 && dc->bb_overrides.fclk_clock_change_latency_ns) { 507 dcn3_21_soc.fclk_change_latency_us = 508 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 509 } 510 511 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) 512 != dc->bb_overrides.dummy_clock_change_latency_ns 513 && dc->bb_overrides.dummy_clock_change_latency_ns) { 514 dcn3_21_soc.dummy_pstate_latency_us = 515 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 516 } 517 518 /* Override from VBIOS if VBIOS bb_info available */ 519 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 520 struct bp_soc_bb_info bb_info = {0}; 521 522 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 523 if (bb_info.dram_clock_change_latency_100ns > 0) 524 dcn3_21_soc.dram_clock_change_latency_us = 525 bb_info.dram_clock_change_latency_100ns * 10; 526 527 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 528 dcn3_21_soc.sr_enter_plus_exit_time_us = 529 bb_info.dram_sr_enter_exit_latency_100ns * 10; 530 531 if (bb_info.dram_sr_exit_latency_100ns > 0) 532 dcn3_21_soc.sr_exit_time_us = 533 bb_info.dram_sr_exit_latency_100ns * 10; 534 } 535 } 536 537 /* Override from VBIOS for num_chan */ 538 if (dc->ctx->dc_bios->vram_info.num_chans) { 539 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 540 dcn3_21_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc, 541 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); 542 } 543 544 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 545 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 546 } 547 548 /* DML DSC delay factor workaround */ 549 dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 550 551 dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 552 553 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 554 dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 555 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 556 557 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 558 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 559 if (dc->debug.use_legacy_soc_bb_mechanism) { 560 unsigned int i = 0, j = 0, num_states = 0; 561 562 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 563 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 564 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 565 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 566 567 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; 568 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 569 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 570 571 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 572 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 573 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 574 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 575 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 576 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 577 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 578 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 579 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 580 } 581 if (!max_dcfclk_mhz) 582 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; 583 if (!max_dispclk_mhz) 584 max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; 585 if (!max_dppclk_mhz) 586 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; 587 if (!max_phyclk_mhz) 588 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 589 590 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 591 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 592 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 593 num_dcfclk_sta_targets++; 594 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 595 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 596 for (i = 0; i < num_dcfclk_sta_targets; i++) { 597 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 598 dcfclk_sta_targets[i] = max_dcfclk_mhz; 599 break; 600 } 601 } 602 // Update size of array since we "removed" duplicates 603 num_dcfclk_sta_targets = i + 1; 604 } 605 606 num_uclk_states = bw_params->clk_table.num_entries; 607 608 // Calculate optimal dcfclk for each uclk 609 for (i = 0; i < num_uclk_states; i++) { 610 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 611 &optimal_dcfclk_for_uclk[i], NULL); 612 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 613 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 614 } 615 } 616 617 // Calculate optimal uclk for each dcfclk sta target 618 for (i = 0; i < num_dcfclk_sta_targets; i++) { 619 for (j = 0; j < num_uclk_states; j++) { 620 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 621 optimal_uclk_for_dcfclk_sta_targets[i] = 622 bw_params->clk_table.entries[j].memclk_mhz * 16; 623 break; 624 } 625 } 626 } 627 628 i = 0; 629 j = 0; 630 // create the final dcfclk and uclk table 631 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 632 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 633 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 634 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 635 } else { 636 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 637 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 638 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 639 } else { 640 j = num_uclk_states; 641 } 642 } 643 } 644 645 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 646 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 647 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 648 } 649 650 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 651 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 652 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 653 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 654 } 655 656 dcn3_21_soc.num_states = num_states; 657 for (i = 0; i < dcn3_21_soc.num_states; i++) { 658 dcn3_21_soc.clock_limits[i].state = i; 659 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 660 dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 661 662 /* Fill all states with max values of all these clocks */ 663 dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 664 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 665 dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 666 dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 667 668 /* Populate from bw_params for DTBCLK, SOCCLK */ 669 if (i > 0) { 670 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 671 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; 672 } else { 673 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 674 } 675 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 676 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 677 } 678 679 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 680 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; 681 else 682 dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 683 684 if (!dram_speed_mts[i] && i > 0) 685 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; 686 else 687 dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 688 689 /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ 690 /* PHYCLK_D18, PHYCLK_D32 */ 691 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 692 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 693 } 694 } else { 695 build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states); 696 } 697 698 /* Re-init DML with updated bb */ 699 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 700 if (dc->current_state) 701 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 702 } 703 } 704 705