1197485c6SRodrigo Siqueira // SPDX-License-Identifier: MIT 2197485c6SRodrigo Siqueira /* 3197485c6SRodrigo Siqueira * Copyright 2022 Advanced Micro Devices, Inc. 4197485c6SRodrigo Siqueira * 5197485c6SRodrigo Siqueira * Permission is hereby granted, free of charge, to any person obtaining a 6197485c6SRodrigo Siqueira * copy of this software and associated documentation files (the "Software"), 7197485c6SRodrigo Siqueira * to deal in the Software without restriction, including without limitation 8197485c6SRodrigo Siqueira * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9197485c6SRodrigo Siqueira * and/or sell copies of the Software, and to permit persons to whom the 10197485c6SRodrigo Siqueira * Software is furnished to do so, subject to the following conditions: 11197485c6SRodrigo Siqueira * 12197485c6SRodrigo Siqueira * The above copyright notice and this permission notice shall be included in 13197485c6SRodrigo Siqueira * all copies or substantial portions of the Software. 14197485c6SRodrigo Siqueira * 15197485c6SRodrigo Siqueira * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16197485c6SRodrigo Siqueira * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17197485c6SRodrigo Siqueira * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18197485c6SRodrigo Siqueira * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19197485c6SRodrigo Siqueira * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20197485c6SRodrigo Siqueira * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21197485c6SRodrigo Siqueira * OTHER DEALINGS IN THE SOFTWARE. 22197485c6SRodrigo Siqueira * 23197485c6SRodrigo Siqueira * Authors: AMD 24197485c6SRodrigo Siqueira * 25197485c6SRodrigo Siqueira */ 26197485c6SRodrigo Siqueira 27352b25a7SRodrigo Siqueira #include "clk_mgr.h" 28197485c6SRodrigo Siqueira #include "resource.h" 29197485c6SRodrigo Siqueira #include "dcn321_fpu.h" 30197485c6SRodrigo Siqueira #include "dcn32/dcn32_resource.h" 31197485c6SRodrigo Siqueira #include "dcn321/dcn321_resource.h" 32197485c6SRodrigo Siqueira 33197485c6SRodrigo Siqueira #define DCN3_2_DEFAULT_DET_SIZE 256 34197485c6SRodrigo Siqueira 35197485c6SRodrigo Siqueira struct _vcs_dpi_ip_params_st dcn3_21_ip = { 36197485c6SRodrigo Siqueira .gpuvm_enable = 0, 37197485c6SRodrigo Siqueira .gpuvm_max_page_table_levels = 4, 38197485c6SRodrigo Siqueira .hostvm_enable = 0, 39197485c6SRodrigo Siqueira .rob_buffer_size_kbytes = 128, 40197485c6SRodrigo Siqueira .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 41197485c6SRodrigo Siqueira .config_return_buffer_size_in_kbytes = 1280, 42197485c6SRodrigo Siqueira .compressed_buffer_segment_size_in_kbytes = 64, 43197485c6SRodrigo Siqueira .meta_fifo_size_in_kentries = 22, 44197485c6SRodrigo Siqueira .zero_size_buffer_entries = 512, 45197485c6SRodrigo Siqueira .compbuf_reserved_space_64b = 256, 46197485c6SRodrigo Siqueira .compbuf_reserved_space_zs = 64, 47197485c6SRodrigo Siqueira .dpp_output_buffer_pixels = 2560, 48197485c6SRodrigo Siqueira .opp_output_buffer_lines = 1, 49197485c6SRodrigo Siqueira .pixel_chunk_size_kbytes = 8, 50197485c6SRodrigo Siqueira .alpha_pixel_chunk_size_kbytes = 4, 51197485c6SRodrigo Siqueira .min_pixel_chunk_size_bytes = 1024, 52197485c6SRodrigo Siqueira .dcc_meta_buffer_size_bytes = 6272, 53197485c6SRodrigo Siqueira .meta_chunk_size_kbytes = 2, 54197485c6SRodrigo Siqueira .min_meta_chunk_size_bytes = 256, 55197485c6SRodrigo Siqueira .writeback_chunk_size_kbytes = 8, 56197485c6SRodrigo Siqueira .ptoi_supported = false, 57197485c6SRodrigo Siqueira .num_dsc = 4, 58197485c6SRodrigo Siqueira .maximum_dsc_bits_per_component = 12, 59197485c6SRodrigo Siqueira .maximum_pixels_per_line_per_dsc_unit = 6016, 60197485c6SRodrigo Siqueira .dsc422_native_support = true, 61197485c6SRodrigo Siqueira .is_line_buffer_bpp_fixed = true, 62197485c6SRodrigo Siqueira .line_buffer_fixed_bpp = 57, 63197485c6SRodrigo Siqueira .line_buffer_size_bits = 1171920, 64197485c6SRodrigo Siqueira .max_line_buffer_lines = 32, 65197485c6SRodrigo Siqueira .writeback_interface_buffer_size_kbytes = 90, 66197485c6SRodrigo Siqueira .max_num_dpp = 4, 67197485c6SRodrigo Siqueira .max_num_otg = 4, 68197485c6SRodrigo Siqueira .max_num_hdmi_frl_outputs = 1, 69197485c6SRodrigo Siqueira .max_num_wb = 1, 70197485c6SRodrigo Siqueira .max_dchub_pscl_bw_pix_per_clk = 4, 71197485c6SRodrigo Siqueira .max_pscl_lb_bw_pix_per_clk = 2, 72197485c6SRodrigo Siqueira .max_lb_vscl_bw_pix_per_clk = 4, 73197485c6SRodrigo Siqueira .max_vscl_hscl_bw_pix_per_clk = 4, 74197485c6SRodrigo Siqueira .max_hscl_ratio = 6, 75197485c6SRodrigo Siqueira .max_vscl_ratio = 6, 76197485c6SRodrigo Siqueira .max_hscl_taps = 8, 77197485c6SRodrigo Siqueira .max_vscl_taps = 8, 78197485c6SRodrigo Siqueira .dpte_buffer_size_in_pte_reqs_luma = 64, 79197485c6SRodrigo Siqueira .dpte_buffer_size_in_pte_reqs_chroma = 34, 80197485c6SRodrigo Siqueira .dispclk_ramp_margin_percent = 1, 81197485c6SRodrigo Siqueira .max_inter_dcn_tile_repeaters = 8, 82197485c6SRodrigo Siqueira .cursor_buffer_size = 16, 83197485c6SRodrigo Siqueira .cursor_chunk_size = 2, 84197485c6SRodrigo Siqueira .writeback_line_buffer_buffer_size = 0, 85197485c6SRodrigo Siqueira .writeback_min_hscl_ratio = 1, 86197485c6SRodrigo Siqueira .writeback_min_vscl_ratio = 1, 87197485c6SRodrigo Siqueira .writeback_max_hscl_ratio = 1, 88197485c6SRodrigo Siqueira .writeback_max_vscl_ratio = 1, 89197485c6SRodrigo Siqueira .writeback_max_hscl_taps = 1, 90197485c6SRodrigo Siqueira .writeback_max_vscl_taps = 1, 91197485c6SRodrigo Siqueira .dppclk_delay_subtotal = 47, 92197485c6SRodrigo Siqueira .dppclk_delay_scl = 50, 93197485c6SRodrigo Siqueira .dppclk_delay_scl_lb_only = 16, 94197485c6SRodrigo Siqueira .dppclk_delay_cnvc_formatter = 28, 95197485c6SRodrigo Siqueira .dppclk_delay_cnvc_cursor = 6, 96197485c6SRodrigo Siqueira .dispclk_delay_subtotal = 125, 97197485c6SRodrigo Siqueira .dynamic_metadata_vm_enabled = false, 98197485c6SRodrigo Siqueira .odm_combine_4to1_supported = false, 99197485c6SRodrigo Siqueira .dcc_supported = true, 100197485c6SRodrigo Siqueira .max_num_dp2p0_outputs = 2, 101197485c6SRodrigo Siqueira .max_num_dp2p0_streams = 4, 102197485c6SRodrigo Siqueira }; 103197485c6SRodrigo Siqueira 104197485c6SRodrigo Siqueira struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 105197485c6SRodrigo Siqueira .clock_limits = { 106197485c6SRodrigo Siqueira { 107197485c6SRodrigo Siqueira .state = 0, 108197485c6SRodrigo Siqueira .dcfclk_mhz = 1564.0, 109197485c6SRodrigo Siqueira .fabricclk_mhz = 400.0, 110197485c6SRodrigo Siqueira .dispclk_mhz = 2150.0, 111197485c6SRodrigo Siqueira .dppclk_mhz = 2150.0, 112197485c6SRodrigo Siqueira .phyclk_mhz = 810.0, 113197485c6SRodrigo Siqueira .phyclk_d18_mhz = 667.0, 114197485c6SRodrigo Siqueira .phyclk_d32_mhz = 625.0, 115197485c6SRodrigo Siqueira .socclk_mhz = 1200.0, 116197485c6SRodrigo Siqueira .dscclk_mhz = 716.667, 117197485c6SRodrigo Siqueira .dram_speed_mts = 1600.0, 118197485c6SRodrigo Siqueira .dtbclk_mhz = 1564.0, 119197485c6SRodrigo Siqueira }, 120197485c6SRodrigo Siqueira }, 121197485c6SRodrigo Siqueira .num_states = 1, 122*493af96dSAlvin Lee .sr_exit_time_us = 12.36, 123*493af96dSAlvin Lee .sr_enter_plus_exit_time_us = 16.72, 124197485c6SRodrigo Siqueira .sr_exit_z8_time_us = 285.0, 125197485c6SRodrigo Siqueira .sr_enter_plus_exit_z8_time_us = 320, 126197485c6SRodrigo Siqueira .writeback_latency_us = 12.0, 127197485c6SRodrigo Siqueira .round_trip_ping_latency_dcfclk_cycles = 263, 128197485c6SRodrigo Siqueira .urgent_latency_pixel_data_only_us = 4.0, 129197485c6SRodrigo Siqueira .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 130197485c6SRodrigo Siqueira .urgent_latency_vm_data_only_us = 4.0, 131197485c6SRodrigo Siqueira .fclk_change_latency_us = 20, 132197485c6SRodrigo Siqueira .usr_retraining_latency_us = 2, 133197485c6SRodrigo Siqueira .smn_latency_us = 2, 134197485c6SRodrigo Siqueira .mall_allocated_for_dcn_mbytes = 64, 135197485c6SRodrigo Siqueira .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 136197485c6SRodrigo Siqueira .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 137197485c6SRodrigo Siqueira .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 138197485c6SRodrigo Siqueira .pct_ideal_sdp_bw_after_urgent = 100.0, 139197485c6SRodrigo Siqueira .pct_ideal_fabric_bw_after_urgent = 67.0, 140197485c6SRodrigo Siqueira .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 141197485c6SRodrigo Siqueira .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 142197485c6SRodrigo Siqueira .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 143197485c6SRodrigo Siqueira .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 144197485c6SRodrigo Siqueira .max_avg_sdp_bw_use_normal_percent = 80.0, 145197485c6SRodrigo Siqueira .max_avg_fabric_bw_use_normal_percent = 60.0, 146197485c6SRodrigo Siqueira .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 147197485c6SRodrigo Siqueira .max_avg_dram_bw_use_normal_percent = 15.0, 148197485c6SRodrigo Siqueira .num_chans = 8, 149197485c6SRodrigo Siqueira .dram_channel_width_bytes = 2, 150197485c6SRodrigo Siqueira .fabric_datapath_to_dcn_data_return_bytes = 64, 151197485c6SRodrigo Siqueira .return_bus_width_bytes = 64, 152197485c6SRodrigo Siqueira .downspread_percent = 0.38, 153197485c6SRodrigo Siqueira .dcn_downspread_percent = 0.5, 154197485c6SRodrigo Siqueira .dram_clock_change_latency_us = 400, 155197485c6SRodrigo Siqueira .dispclk_dppclk_vco_speed_mhz = 4300.0, 156197485c6SRodrigo Siqueira .do_urgent_latency_adjustment = true, 157197485c6SRodrigo Siqueira .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 158197485c6SRodrigo Siqueira .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 159197485c6SRodrigo Siqueira }; 160197485c6SRodrigo Siqueira 161197485c6SRodrigo Siqueira static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 162197485c6SRodrigo Siqueira { 163197485c6SRodrigo Siqueira if (entry->dcfclk_mhz > 0) { 164197485c6SRodrigo Siqueira float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 165197485c6SRodrigo Siqueira 166197485c6SRodrigo Siqueira entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 167197485c6SRodrigo Siqueira entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * 168197485c6SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 169197485c6SRodrigo Siqueira } else if (entry->fabricclk_mhz > 0) { 170197485c6SRodrigo Siqueira float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 171197485c6SRodrigo Siqueira 172197485c6SRodrigo Siqueira entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 173197485c6SRodrigo Siqueira entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * 174197485c6SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 175197485c6SRodrigo Siqueira } else if (entry->dram_speed_mts > 0) { 176197485c6SRodrigo Siqueira float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * 177197485c6SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 178197485c6SRodrigo Siqueira 179197485c6SRodrigo Siqueira entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 180197485c6SRodrigo Siqueira entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 181197485c6SRodrigo Siqueira } 182197485c6SRodrigo Siqueira } 183197485c6SRodrigo Siqueira 184197485c6SRodrigo Siqueira static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 185197485c6SRodrigo Siqueira { 186197485c6SRodrigo Siqueira float memory_bw_kbytes_sec; 187197485c6SRodrigo Siqueira float fabric_bw_kbytes_sec; 188197485c6SRodrigo Siqueira float sdp_bw_kbytes_sec; 189197485c6SRodrigo Siqueira float limiting_bw_kbytes_sec; 190197485c6SRodrigo Siqueira 191197485c6SRodrigo Siqueira memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * 192197485c6SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 193197485c6SRodrigo Siqueira 194197485c6SRodrigo Siqueira fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 195197485c6SRodrigo Siqueira 196197485c6SRodrigo Siqueira sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 197197485c6SRodrigo Siqueira 198197485c6SRodrigo Siqueira limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 199197485c6SRodrigo Siqueira 200197485c6SRodrigo Siqueira if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 201197485c6SRodrigo Siqueira limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 202197485c6SRodrigo Siqueira 203197485c6SRodrigo Siqueira if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 204197485c6SRodrigo Siqueira limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 205197485c6SRodrigo Siqueira 206197485c6SRodrigo Siqueira return limiting_bw_kbytes_sec; 207197485c6SRodrigo Siqueira } 208197485c6SRodrigo Siqueira 209197485c6SRodrigo Siqueira void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 210197485c6SRodrigo Siqueira unsigned int *num_entries, 211197485c6SRodrigo Siqueira struct _vcs_dpi_voltage_scaling_st *entry) 212197485c6SRodrigo Siqueira { 213197485c6SRodrigo Siqueira int i = 0; 214197485c6SRodrigo Siqueira int index = 0; 215197485c6SRodrigo Siqueira float net_bw_of_new_state = 0; 216197485c6SRodrigo Siqueira 217197485c6SRodrigo Siqueira dc_assert_fp_enabled(); 218197485c6SRodrigo Siqueira 219197485c6SRodrigo Siqueira get_optimal_ntuple(entry); 220197485c6SRodrigo Siqueira 221197485c6SRodrigo Siqueira if (*num_entries == 0) { 222197485c6SRodrigo Siqueira table[0] = *entry; 223197485c6SRodrigo Siqueira (*num_entries)++; 224197485c6SRodrigo Siqueira } else { 225197485c6SRodrigo Siqueira net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 226197485c6SRodrigo Siqueira while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 227197485c6SRodrigo Siqueira index++; 228197485c6SRodrigo Siqueira if (index >= *num_entries) 229197485c6SRodrigo Siqueira break; 230197485c6SRodrigo Siqueira } 231197485c6SRodrigo Siqueira 232197485c6SRodrigo Siqueira for (i = *num_entries; i > index; i--) 233197485c6SRodrigo Siqueira table[i] = table[i - 1]; 234197485c6SRodrigo Siqueira 235197485c6SRodrigo Siqueira table[index] = *entry; 236197485c6SRodrigo Siqueira (*num_entries)++; 237197485c6SRodrigo Siqueira } 238197485c6SRodrigo Siqueira } 239197485c6SRodrigo Siqueira 240352b25a7SRodrigo Siqueira static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 241352b25a7SRodrigo Siqueira unsigned int index) 242352b25a7SRodrigo Siqueira { 243352b25a7SRodrigo Siqueira int i; 244352b25a7SRodrigo Siqueira 245352b25a7SRodrigo Siqueira if (*num_entries == 0) 246352b25a7SRodrigo Siqueira return; 247352b25a7SRodrigo Siqueira 248352b25a7SRodrigo Siqueira for (i = index; i < *num_entries - 1; i++) { 249352b25a7SRodrigo Siqueira table[i] = table[i + 1]; 250352b25a7SRodrigo Siqueira } 251352b25a7SRodrigo Siqueira memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 252352b25a7SRodrigo Siqueira } 253352b25a7SRodrigo Siqueira 254352b25a7SRodrigo Siqueira static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 255352b25a7SRodrigo Siqueira struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 256352b25a7SRodrigo Siqueira { 257352b25a7SRodrigo Siqueira int i, j; 258352b25a7SRodrigo Siqueira struct _vcs_dpi_voltage_scaling_st entry = {0}; 259352b25a7SRodrigo Siqueira 260352b25a7SRodrigo Siqueira unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 261352b25a7SRodrigo Siqueira max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 262352b25a7SRodrigo Siqueira 263352b25a7SRodrigo Siqueira unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 264352b25a7SRodrigo Siqueira 265352b25a7SRodrigo Siqueira static const unsigned int num_dcfclk_stas = 5; 266352b25a7SRodrigo Siqueira unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 267352b25a7SRodrigo Siqueira 268352b25a7SRodrigo Siqueira unsigned int num_uclk_dpms = 0; 269352b25a7SRodrigo Siqueira unsigned int num_fclk_dpms = 0; 270352b25a7SRodrigo Siqueira unsigned int num_dcfclk_dpms = 0; 271352b25a7SRodrigo Siqueira 272352b25a7SRodrigo Siqueira for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 273352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 274352b25a7SRodrigo Siqueira max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 275352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 276352b25a7SRodrigo Siqueira max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 277352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 278352b25a7SRodrigo Siqueira max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 279352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 280352b25a7SRodrigo Siqueira max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 281352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 282352b25a7SRodrigo Siqueira max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 283352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 284352b25a7SRodrigo Siqueira max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 285352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 286352b25a7SRodrigo Siqueira max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 287352b25a7SRodrigo Siqueira 288352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].memclk_mhz > 0) 289352b25a7SRodrigo Siqueira num_uclk_dpms++; 290352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].fclk_mhz > 0) 291352b25a7SRodrigo Siqueira num_fclk_dpms++; 292352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 293352b25a7SRodrigo Siqueira num_dcfclk_dpms++; 294352b25a7SRodrigo Siqueira } 295352b25a7SRodrigo Siqueira 296352b25a7SRodrigo Siqueira if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 297352b25a7SRodrigo Siqueira return -1; 298352b25a7SRodrigo Siqueira 299352b25a7SRodrigo Siqueira if (max_dppclk_mhz == 0) 300352b25a7SRodrigo Siqueira max_dppclk_mhz = max_dispclk_mhz; 301352b25a7SRodrigo Siqueira 302352b25a7SRodrigo Siqueira if (max_fclk_mhz == 0) 303352b25a7SRodrigo Siqueira max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; 304352b25a7SRodrigo Siqueira 305352b25a7SRodrigo Siqueira if (max_phyclk_mhz == 0) 306352b25a7SRodrigo Siqueira max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 307352b25a7SRodrigo Siqueira 308352b25a7SRodrigo Siqueira *num_entries = 0; 309352b25a7SRodrigo Siqueira entry.dispclk_mhz = max_dispclk_mhz; 310352b25a7SRodrigo Siqueira entry.dscclk_mhz = max_dispclk_mhz / 3; 311352b25a7SRodrigo Siqueira entry.dppclk_mhz = max_dppclk_mhz; 312352b25a7SRodrigo Siqueira entry.dtbclk_mhz = max_dtbclk_mhz; 313352b25a7SRodrigo Siqueira entry.phyclk_mhz = max_phyclk_mhz; 314352b25a7SRodrigo Siqueira entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 315352b25a7SRodrigo Siqueira entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 316352b25a7SRodrigo Siqueira 317352b25a7SRodrigo Siqueira // Insert all the DCFCLK STAs 318352b25a7SRodrigo Siqueira for (i = 0; i < num_dcfclk_stas; i++) { 319352b25a7SRodrigo Siqueira entry.dcfclk_mhz = dcfclk_sta_targets[i]; 320352b25a7SRodrigo Siqueira entry.fabricclk_mhz = 0; 321352b25a7SRodrigo Siqueira entry.dram_speed_mts = 0; 322352b25a7SRodrigo Siqueira 323352b25a7SRodrigo Siqueira dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 324352b25a7SRodrigo Siqueira } 325352b25a7SRodrigo Siqueira 326352b25a7SRodrigo Siqueira // Insert the max DCFCLK 327352b25a7SRodrigo Siqueira entry.dcfclk_mhz = max_dcfclk_mhz; 328352b25a7SRodrigo Siqueira entry.fabricclk_mhz = 0; 329352b25a7SRodrigo Siqueira entry.dram_speed_mts = 0; 330352b25a7SRodrigo Siqueira 331352b25a7SRodrigo Siqueira dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 332352b25a7SRodrigo Siqueira 333352b25a7SRodrigo Siqueira // Insert the UCLK DPMS 334352b25a7SRodrigo Siqueira for (i = 0; i < num_uclk_dpms; i++) { 335352b25a7SRodrigo Siqueira entry.dcfclk_mhz = 0; 336352b25a7SRodrigo Siqueira entry.fabricclk_mhz = 0; 337352b25a7SRodrigo Siqueira entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 338352b25a7SRodrigo Siqueira 339352b25a7SRodrigo Siqueira dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 340352b25a7SRodrigo Siqueira } 341352b25a7SRodrigo Siqueira 342352b25a7SRodrigo Siqueira // If FCLK is coarse grained, insert individual DPMs. 343352b25a7SRodrigo Siqueira if (num_fclk_dpms > 2) { 344352b25a7SRodrigo Siqueira for (i = 0; i < num_fclk_dpms; i++) { 345352b25a7SRodrigo Siqueira entry.dcfclk_mhz = 0; 346352b25a7SRodrigo Siqueira entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 347352b25a7SRodrigo Siqueira entry.dram_speed_mts = 0; 348352b25a7SRodrigo Siqueira 349352b25a7SRodrigo Siqueira dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 350352b25a7SRodrigo Siqueira } 351352b25a7SRodrigo Siqueira } 352352b25a7SRodrigo Siqueira // If FCLK fine grained, only insert max 353352b25a7SRodrigo Siqueira else { 354352b25a7SRodrigo Siqueira entry.dcfclk_mhz = 0; 355352b25a7SRodrigo Siqueira entry.fabricclk_mhz = max_fclk_mhz; 356352b25a7SRodrigo Siqueira entry.dram_speed_mts = 0; 357352b25a7SRodrigo Siqueira 358352b25a7SRodrigo Siqueira dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 359352b25a7SRodrigo Siqueira } 360352b25a7SRodrigo Siqueira 361352b25a7SRodrigo Siqueira // At this point, the table contains all "points of interest" based on 362352b25a7SRodrigo Siqueira // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 363352b25a7SRodrigo Siqueira // ratios (by derate, are exact). 364352b25a7SRodrigo Siqueira 365352b25a7SRodrigo Siqueira // Remove states that require higher clocks than are supported 366352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 367352b25a7SRodrigo Siqueira if (table[i].dcfclk_mhz > max_dcfclk_mhz || 368352b25a7SRodrigo Siqueira table[i].fabricclk_mhz > max_fclk_mhz || 369352b25a7SRodrigo Siqueira table[i].dram_speed_mts > max_uclk_mhz * 16) 370352b25a7SRodrigo Siqueira remove_entry_from_table_at_index(table, num_entries, i); 371352b25a7SRodrigo Siqueira } 372352b25a7SRodrigo Siqueira 373352b25a7SRodrigo Siqueira // At this point, the table only contains supported points of interest 374352b25a7SRodrigo Siqueira // it could be used as is, but some states may be redundant due to 375352b25a7SRodrigo Siqueira // coarse grained nature of some clocks, so we want to round up to 376352b25a7SRodrigo Siqueira // coarse grained DPMs and remove duplicates. 377352b25a7SRodrigo Siqueira 378352b25a7SRodrigo Siqueira // Round up UCLKs 379352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 380352b25a7SRodrigo Siqueira for (j = 0; j < num_uclk_dpms; j++) { 381352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 382352b25a7SRodrigo Siqueira table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 383352b25a7SRodrigo Siqueira break; 384352b25a7SRodrigo Siqueira } 385352b25a7SRodrigo Siqueira } 386352b25a7SRodrigo Siqueira } 387352b25a7SRodrigo Siqueira 388352b25a7SRodrigo Siqueira // If FCLK is coarse grained, round up to next DPMs 389352b25a7SRodrigo Siqueira if (num_fclk_dpms > 2) { 390352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 391352b25a7SRodrigo Siqueira for (j = 0; j < num_fclk_dpms; j++) { 392352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 393352b25a7SRodrigo Siqueira table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 394352b25a7SRodrigo Siqueira break; 395352b25a7SRodrigo Siqueira } 396352b25a7SRodrigo Siqueira } 397352b25a7SRodrigo Siqueira } 398352b25a7SRodrigo Siqueira } 399352b25a7SRodrigo Siqueira // Otherwise, round up to minimum. 400352b25a7SRodrigo Siqueira else { 401352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 402352b25a7SRodrigo Siqueira if (table[i].fabricclk_mhz < min_fclk_mhz) { 403352b25a7SRodrigo Siqueira table[i].fabricclk_mhz = min_fclk_mhz; 404352b25a7SRodrigo Siqueira break; 405352b25a7SRodrigo Siqueira } 406352b25a7SRodrigo Siqueira } 407352b25a7SRodrigo Siqueira } 408352b25a7SRodrigo Siqueira 409352b25a7SRodrigo Siqueira // Round DCFCLKs up to minimum 410352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 411352b25a7SRodrigo Siqueira if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 412352b25a7SRodrigo Siqueira table[i].dcfclk_mhz = min_dcfclk_mhz; 413352b25a7SRodrigo Siqueira break; 414352b25a7SRodrigo Siqueira } 415352b25a7SRodrigo Siqueira } 416352b25a7SRodrigo Siqueira 417352b25a7SRodrigo Siqueira // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 418352b25a7SRodrigo Siqueira i = 0; 419352b25a7SRodrigo Siqueira while (i < *num_entries - 1) { 420352b25a7SRodrigo Siqueira if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 421352b25a7SRodrigo Siqueira table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 422352b25a7SRodrigo Siqueira table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 423352b25a7SRodrigo Siqueira remove_entry_from_table_at_index(table, num_entries, i + 1); 424352b25a7SRodrigo Siqueira else 425352b25a7SRodrigo Siqueira i++; 426352b25a7SRodrigo Siqueira } 427352b25a7SRodrigo Siqueira 428352b25a7SRodrigo Siqueira // Fix up the state indicies 429352b25a7SRodrigo Siqueira for (i = *num_entries - 1; i >= 0 ; i--) { 430352b25a7SRodrigo Siqueira table[i].state = i; 431352b25a7SRodrigo Siqueira } 432352b25a7SRodrigo Siqueira 433352b25a7SRodrigo Siqueira return 0; 434352b25a7SRodrigo Siqueira } 435352b25a7SRodrigo Siqueira 436352b25a7SRodrigo Siqueira static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 437352b25a7SRodrigo Siqueira unsigned int *optimal_dcfclk, 438352b25a7SRodrigo Siqueira unsigned int *optimal_fclk) 439352b25a7SRodrigo Siqueira { 440352b25a7SRodrigo Siqueira double bw_from_dram, bw_from_dram1, bw_from_dram2; 441352b25a7SRodrigo Siqueira 442352b25a7SRodrigo Siqueira bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * 443352b25a7SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); 444352b25a7SRodrigo Siqueira bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * 445352b25a7SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); 446352b25a7SRodrigo Siqueira 447352b25a7SRodrigo Siqueira bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 448352b25a7SRodrigo Siqueira 449352b25a7SRodrigo Siqueira if (optimal_fclk) 450352b25a7SRodrigo Siqueira *optimal_fclk = bw_from_dram / 451352b25a7SRodrigo Siqueira (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 452352b25a7SRodrigo Siqueira 453352b25a7SRodrigo Siqueira if (optimal_dcfclk) 454352b25a7SRodrigo Siqueira *optimal_dcfclk = bw_from_dram / 455352b25a7SRodrigo Siqueira (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 456352b25a7SRodrigo Siqueira } 457352b25a7SRodrigo Siqueira 458352b25a7SRodrigo Siqueira /** dcn321_update_bw_bounding_box 459352b25a7SRodrigo Siqueira * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet 460352b25a7SRodrigo Siqueira * with actual values as per dGPU SKU: 461352b25a7SRodrigo Siqueira * -with passed few options from dc->config 462352b25a7SRodrigo Siqueira * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) 463352b25a7SRodrigo Siqueira * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes 464352b25a7SRodrigo Siqueira * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU 465352b25a7SRodrigo Siqueira * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) 466352b25a7SRodrigo Siqueira * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different 467352b25a7SRodrigo Siqueira * clocks (which might differ for certain dGPU SKU of the same ASIC) 468352b25a7SRodrigo Siqueira */ 469352b25a7SRodrigo Siqueira void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 470352b25a7SRodrigo Siqueira { 471352b25a7SRodrigo Siqueira dc_assert_fp_enabled(); 472352b25a7SRodrigo Siqueira if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 473352b25a7SRodrigo Siqueira /* Overrides from dc->config options */ 474352b25a7SRodrigo Siqueira dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 475352b25a7SRodrigo Siqueira 476352b25a7SRodrigo Siqueira /* Override from passed dc->bb_overrides if available*/ 477352b25a7SRodrigo Siqueira if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 478352b25a7SRodrigo Siqueira && dc->bb_overrides.sr_exit_time_ns) { 479352b25a7SRodrigo Siqueira dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 480352b25a7SRodrigo Siqueira } 481352b25a7SRodrigo Siqueira 482352b25a7SRodrigo Siqueira if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) 483352b25a7SRodrigo Siqueira != dc->bb_overrides.sr_enter_plus_exit_time_ns 484352b25a7SRodrigo Siqueira && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 485352b25a7SRodrigo Siqueira dcn3_21_soc.sr_enter_plus_exit_time_us = 486352b25a7SRodrigo Siqueira dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 487352b25a7SRodrigo Siqueira } 488352b25a7SRodrigo Siqueira 489352b25a7SRodrigo Siqueira if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 490352b25a7SRodrigo Siqueira && dc->bb_overrides.urgent_latency_ns) { 491352b25a7SRodrigo Siqueira dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 492352b25a7SRodrigo Siqueira } 493352b25a7SRodrigo Siqueira 494352b25a7SRodrigo Siqueira if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) 495352b25a7SRodrigo Siqueira != dc->bb_overrides.dram_clock_change_latency_ns 496352b25a7SRodrigo Siqueira && dc->bb_overrides.dram_clock_change_latency_ns) { 497352b25a7SRodrigo Siqueira dcn3_21_soc.dram_clock_change_latency_us = 498352b25a7SRodrigo Siqueira dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 499352b25a7SRodrigo Siqueira } 500352b25a7SRodrigo Siqueira 501352b25a7SRodrigo Siqueira if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) 502352b25a7SRodrigo Siqueira != dc->bb_overrides.dummy_clock_change_latency_ns 503352b25a7SRodrigo Siqueira && dc->bb_overrides.dummy_clock_change_latency_ns) { 504352b25a7SRodrigo Siqueira dcn3_21_soc.dummy_pstate_latency_us = 505352b25a7SRodrigo Siqueira dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 506352b25a7SRodrigo Siqueira } 507352b25a7SRodrigo Siqueira 508352b25a7SRodrigo Siqueira /* Override from VBIOS if VBIOS bb_info available */ 509352b25a7SRodrigo Siqueira if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 510352b25a7SRodrigo Siqueira struct bp_soc_bb_info bb_info = {0}; 511352b25a7SRodrigo Siqueira 512352b25a7SRodrigo Siqueira if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 513352b25a7SRodrigo Siqueira if (bb_info.dram_clock_change_latency_100ns > 0) 514352b25a7SRodrigo Siqueira dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 515352b25a7SRodrigo Siqueira 516352b25a7SRodrigo Siqueira if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 517352b25a7SRodrigo Siqueira dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 518352b25a7SRodrigo Siqueira 519352b25a7SRodrigo Siqueira if (bb_info.dram_sr_exit_latency_100ns > 0) 520352b25a7SRodrigo Siqueira dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 521352b25a7SRodrigo Siqueira } 522352b25a7SRodrigo Siqueira } 523352b25a7SRodrigo Siqueira 524352b25a7SRodrigo Siqueira /* Override from VBIOS for num_chan */ 525352b25a7SRodrigo Siqueira if (dc->ctx->dc_bios->vram_info.num_chans) 526352b25a7SRodrigo Siqueira dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 527352b25a7SRodrigo Siqueira 528352b25a7SRodrigo Siqueira if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 529352b25a7SRodrigo Siqueira dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 530352b25a7SRodrigo Siqueira 531352b25a7SRodrigo Siqueira } 532352b25a7SRodrigo Siqueira 533352b25a7SRodrigo Siqueira /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 534352b25a7SRodrigo Siqueira dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 535352b25a7SRodrigo Siqueira dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 536352b25a7SRodrigo Siqueira 537352b25a7SRodrigo Siqueira /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 538352b25a7SRodrigo Siqueira if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 539352b25a7SRodrigo Siqueira if (dc->debug.use_legacy_soc_bb_mechanism) { 540352b25a7SRodrigo Siqueira unsigned int i = 0, j = 0, num_states = 0; 541352b25a7SRodrigo Siqueira 542352b25a7SRodrigo Siqueira unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 543352b25a7SRodrigo Siqueira unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 544352b25a7SRodrigo Siqueira unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 545352b25a7SRodrigo Siqueira unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 546352b25a7SRodrigo Siqueira 547352b25a7SRodrigo Siqueira unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; 548352b25a7SRodrigo Siqueira unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 549352b25a7SRodrigo Siqueira unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 550352b25a7SRodrigo Siqueira 551352b25a7SRodrigo Siqueira for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 552352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 553352b25a7SRodrigo Siqueira max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 554352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 555352b25a7SRodrigo Siqueira max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 556352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 557352b25a7SRodrigo Siqueira max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 558352b25a7SRodrigo Siqueira if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 559352b25a7SRodrigo Siqueira max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 560352b25a7SRodrigo Siqueira } 561352b25a7SRodrigo Siqueira if (!max_dcfclk_mhz) 562352b25a7SRodrigo Siqueira max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; 563352b25a7SRodrigo Siqueira if (!max_dispclk_mhz) 564352b25a7SRodrigo Siqueira max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; 565352b25a7SRodrigo Siqueira if (!max_dppclk_mhz) 566352b25a7SRodrigo Siqueira max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; 567352b25a7SRodrigo Siqueira if (!max_phyclk_mhz) 568352b25a7SRodrigo Siqueira max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 569352b25a7SRodrigo Siqueira 570352b25a7SRodrigo Siqueira if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 571352b25a7SRodrigo Siqueira // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 572352b25a7SRodrigo Siqueira dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 573352b25a7SRodrigo Siqueira num_dcfclk_sta_targets++; 574352b25a7SRodrigo Siqueira } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 575352b25a7SRodrigo Siqueira // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 576352b25a7SRodrigo Siqueira for (i = 0; i < num_dcfclk_sta_targets; i++) { 577352b25a7SRodrigo Siqueira if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 578352b25a7SRodrigo Siqueira dcfclk_sta_targets[i] = max_dcfclk_mhz; 579352b25a7SRodrigo Siqueira break; 580352b25a7SRodrigo Siqueira } 581352b25a7SRodrigo Siqueira } 582352b25a7SRodrigo Siqueira // Update size of array since we "removed" duplicates 583352b25a7SRodrigo Siqueira num_dcfclk_sta_targets = i + 1; 584352b25a7SRodrigo Siqueira } 585352b25a7SRodrigo Siqueira 586352b25a7SRodrigo Siqueira num_uclk_states = bw_params->clk_table.num_entries; 587352b25a7SRodrigo Siqueira 588352b25a7SRodrigo Siqueira // Calculate optimal dcfclk for each uclk 589352b25a7SRodrigo Siqueira for (i = 0; i < num_uclk_states; i++) { 590352b25a7SRodrigo Siqueira dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 591352b25a7SRodrigo Siqueira &optimal_dcfclk_for_uclk[i], NULL); 592352b25a7SRodrigo Siqueira if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 593352b25a7SRodrigo Siqueira optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 594352b25a7SRodrigo Siqueira } 595352b25a7SRodrigo Siqueira } 596352b25a7SRodrigo Siqueira 597352b25a7SRodrigo Siqueira // Calculate optimal uclk for each dcfclk sta target 598352b25a7SRodrigo Siqueira for (i = 0; i < num_dcfclk_sta_targets; i++) { 599352b25a7SRodrigo Siqueira for (j = 0; j < num_uclk_states; j++) { 600352b25a7SRodrigo Siqueira if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 601352b25a7SRodrigo Siqueira optimal_uclk_for_dcfclk_sta_targets[i] = 602352b25a7SRodrigo Siqueira bw_params->clk_table.entries[j].memclk_mhz * 16; 603352b25a7SRodrigo Siqueira break; 604352b25a7SRodrigo Siqueira } 605352b25a7SRodrigo Siqueira } 606352b25a7SRodrigo Siqueira } 607352b25a7SRodrigo Siqueira 608352b25a7SRodrigo Siqueira i = 0; 609352b25a7SRodrigo Siqueira j = 0; 610352b25a7SRodrigo Siqueira // create the final dcfclk and uclk table 611352b25a7SRodrigo Siqueira while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 612352b25a7SRodrigo Siqueira if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 613352b25a7SRodrigo Siqueira dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 614352b25a7SRodrigo Siqueira dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 615352b25a7SRodrigo Siqueira } else { 616352b25a7SRodrigo Siqueira if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 617352b25a7SRodrigo Siqueira dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 618352b25a7SRodrigo Siqueira dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 619352b25a7SRodrigo Siqueira } else { 620352b25a7SRodrigo Siqueira j = num_uclk_states; 621352b25a7SRodrigo Siqueira } 622352b25a7SRodrigo Siqueira } 623352b25a7SRodrigo Siqueira } 624352b25a7SRodrigo Siqueira 625352b25a7SRodrigo Siqueira while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 626352b25a7SRodrigo Siqueira dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 627352b25a7SRodrigo Siqueira dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 628352b25a7SRodrigo Siqueira } 629352b25a7SRodrigo Siqueira 630352b25a7SRodrigo Siqueira while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 631352b25a7SRodrigo Siqueira optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 632352b25a7SRodrigo Siqueira dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 633352b25a7SRodrigo Siqueira dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 634352b25a7SRodrigo Siqueira } 635352b25a7SRodrigo Siqueira 636352b25a7SRodrigo Siqueira dcn3_21_soc.num_states = num_states; 637352b25a7SRodrigo Siqueira for (i = 0; i < dcn3_21_soc.num_states; i++) { 638352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].state = i; 639352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 640352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 641352b25a7SRodrigo Siqueira 642352b25a7SRodrigo Siqueira /* Fill all states with max values of all these clocks */ 643352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 644352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 645352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 646352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 647352b25a7SRodrigo Siqueira 648352b25a7SRodrigo Siqueira /* Populate from bw_params for DTBCLK, SOCCLK */ 649352b25a7SRodrigo Siqueira if (i > 0) { 650352b25a7SRodrigo Siqueira if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 651352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; 652352b25a7SRodrigo Siqueira } else { 653352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 654352b25a7SRodrigo Siqueira } 655352b25a7SRodrigo Siqueira } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 656352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 657352b25a7SRodrigo Siqueira } 658352b25a7SRodrigo Siqueira 659352b25a7SRodrigo Siqueira if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 660352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; 661352b25a7SRodrigo Siqueira else 662352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 663352b25a7SRodrigo Siqueira 664352b25a7SRodrigo Siqueira if (!dram_speed_mts[i] && i > 0) 665352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; 666352b25a7SRodrigo Siqueira else 667352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 668352b25a7SRodrigo Siqueira 669352b25a7SRodrigo Siqueira /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ 670352b25a7SRodrigo Siqueira /* PHYCLK_D18, PHYCLK_D32 */ 671352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 672352b25a7SRodrigo Siqueira dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 673352b25a7SRodrigo Siqueira } 674352b25a7SRodrigo Siqueira } else { 675352b25a7SRodrigo Siqueira build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states); 676352b25a7SRodrigo Siqueira } 677352b25a7SRodrigo Siqueira 678352b25a7SRodrigo Siqueira /* Re-init DML with updated bb */ 679352b25a7SRodrigo Siqueira dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 680352b25a7SRodrigo Siqueira if (dc->current_state) 681352b25a7SRodrigo Siqueira dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 682352b25a7SRodrigo Siqueira } 683352b25a7SRodrigo Siqueira } 684352b25a7SRodrigo Siqueira 685