1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #ifndef __DCN32_FPU_H__
28 #define __DCN32_FPU_H__
29 
30 #include "clk_mgr_internal.h"
31 
32 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);
33 
34 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
35 					      struct dc_state *context,
36 					      display_e2e_pipe_params_st *pipes,
37 					      int pipe_cnt);
38 
39 uint8_t dcn32_predict_pipe_split(struct dc_state *context,
40 				  display_e2e_pipe_params_st *pipe_e2e);
41 
42 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
43 				    unsigned int *num_entries,
44 				    struct _vcs_dpi_voltage_scaling_st *entry);
45 
46 void dcn32_set_phantom_stream_timing(struct dc *dc,
47 				     struct dc_state *context,
48 				     struct pipe_ctx *ref_pipe,
49 				     struct dc_stream_state *phantom_stream,
50 				     display_e2e_pipe_params_st *pipes,
51 				     unsigned int pipe_cnt,
52 				     unsigned int dc_pipe_idx);
53 
54 bool dcn32_internal_validate_bw(struct dc *dc,
55 				struct dc_state *context,
56 				display_e2e_pipe_params_st *pipes,
57 				int *pipe_cnt_out,
58 				int *vlevel_out,
59 				bool fast_validate);
60 
61 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
62 				display_e2e_pipe_params_st *pipes,
63 				int pipe_cnt,
64 				int vlevel);
65 
66 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
67 
68 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
69 							    struct dc_state *context,
70 							    display_e2e_pipe_params_st *pipes,
71 							    int pipe_cnt,
72 							    int vlevel);
73 
74 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
75 
76 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
77 				  int pipe_cnt);
78 
79 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);
80 
81 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req);
82 
83 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb);
84 
85 #endif
86