1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include "dcn32_fpu.h" 27 #include "dc_link_dp.h" 28 #include "dcn32/dcn32_resource.h" 29 #include "dcn20/dcn20_resource.h" 30 #include "display_mode_vba_util_32.h" 31 // We need this includes for WATERMARKS_* defines 32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" 33 #include "dcn30/dcn30_resource.h" 34 35 #define DC_LOGGER_INIT(logger) 36 37 struct _vcs_dpi_ip_params_st dcn3_2_ip = { 38 .gpuvm_enable = 0, 39 .gpuvm_max_page_table_levels = 4, 40 .hostvm_enable = 0, 41 .rob_buffer_size_kbytes = 128, 42 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 43 .config_return_buffer_size_in_kbytes = 1280, 44 .compressed_buffer_segment_size_in_kbytes = 64, 45 .meta_fifo_size_in_kentries = 22, 46 .zero_size_buffer_entries = 512, 47 .compbuf_reserved_space_64b = 256, 48 .compbuf_reserved_space_zs = 64, 49 .dpp_output_buffer_pixels = 2560, 50 .opp_output_buffer_lines = 1, 51 .pixel_chunk_size_kbytes = 8, 52 .alpha_pixel_chunk_size_kbytes = 4, 53 .min_pixel_chunk_size_bytes = 1024, 54 .dcc_meta_buffer_size_bytes = 6272, 55 .meta_chunk_size_kbytes = 2, 56 .min_meta_chunk_size_bytes = 256, 57 .writeback_chunk_size_kbytes = 8, 58 .ptoi_supported = false, 59 .num_dsc = 4, 60 .maximum_dsc_bits_per_component = 12, 61 .maximum_pixels_per_line_per_dsc_unit = 6016, 62 .dsc422_native_support = true, 63 .is_line_buffer_bpp_fixed = true, 64 .line_buffer_fixed_bpp = 57, 65 .line_buffer_size_bits = 1171920, 66 .max_line_buffer_lines = 32, 67 .writeback_interface_buffer_size_kbytes = 90, 68 .max_num_dpp = 4, 69 .max_num_otg = 4, 70 .max_num_hdmi_frl_outputs = 1, 71 .max_num_wb = 1, 72 .max_dchub_pscl_bw_pix_per_clk = 4, 73 .max_pscl_lb_bw_pix_per_clk = 2, 74 .max_lb_vscl_bw_pix_per_clk = 4, 75 .max_vscl_hscl_bw_pix_per_clk = 4, 76 .max_hscl_ratio = 6, 77 .max_vscl_ratio = 6, 78 .max_hscl_taps = 8, 79 .max_vscl_taps = 8, 80 .dpte_buffer_size_in_pte_reqs_luma = 64, 81 .dpte_buffer_size_in_pte_reqs_chroma = 34, 82 .dispclk_ramp_margin_percent = 1, 83 .max_inter_dcn_tile_repeaters = 8, 84 .cursor_buffer_size = 16, 85 .cursor_chunk_size = 2, 86 .writeback_line_buffer_buffer_size = 0, 87 .writeback_min_hscl_ratio = 1, 88 .writeback_min_vscl_ratio = 1, 89 .writeback_max_hscl_ratio = 1, 90 .writeback_max_vscl_ratio = 1, 91 .writeback_max_hscl_taps = 1, 92 .writeback_max_vscl_taps = 1, 93 .dppclk_delay_subtotal = 47, 94 .dppclk_delay_scl = 50, 95 .dppclk_delay_scl_lb_only = 16, 96 .dppclk_delay_cnvc_formatter = 28, 97 .dppclk_delay_cnvc_cursor = 6, 98 .dispclk_delay_subtotal = 125, 99 .dynamic_metadata_vm_enabled = false, 100 .odm_combine_4to1_supported = false, 101 .dcc_supported = true, 102 .max_num_dp2p0_outputs = 2, 103 .max_num_dp2p0_streams = 4, 104 }; 105 106 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { 107 .clock_limits = { 108 { 109 .state = 0, 110 .dcfclk_mhz = 1564.0, 111 .fabricclk_mhz = 400.0, 112 .dispclk_mhz = 2150.0, 113 .dppclk_mhz = 2150.0, 114 .phyclk_mhz = 810.0, 115 .phyclk_d18_mhz = 667.0, 116 .phyclk_d32_mhz = 625.0, 117 .socclk_mhz = 1200.0, 118 .dscclk_mhz = 716.667, 119 .dram_speed_mts = 16000.0, 120 .dtbclk_mhz = 1564.0, 121 }, 122 }, 123 .num_states = 1, 124 .sr_exit_time_us = 42.97, 125 .sr_enter_plus_exit_time_us = 49.94, 126 .sr_exit_z8_time_us = 285.0, 127 .sr_enter_plus_exit_z8_time_us = 320, 128 .writeback_latency_us = 12.0, 129 .round_trip_ping_latency_dcfclk_cycles = 263, 130 .urgent_latency_pixel_data_only_us = 4.0, 131 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 132 .urgent_latency_vm_data_only_us = 4.0, 133 .fclk_change_latency_us = 20, 134 .usr_retraining_latency_us = 2, 135 .smn_latency_us = 2, 136 .mall_allocated_for_dcn_mbytes = 64, 137 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 138 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 139 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 140 .pct_ideal_sdp_bw_after_urgent = 100.0, 141 .pct_ideal_fabric_bw_after_urgent = 67.0, 142 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 143 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 144 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 145 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 146 .max_avg_sdp_bw_use_normal_percent = 80.0, 147 .max_avg_fabric_bw_use_normal_percent = 60.0, 148 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 149 .max_avg_dram_bw_use_normal_percent = 15.0, 150 .num_chans = 8, 151 .dram_channel_width_bytes = 2, 152 .fabric_datapath_to_dcn_data_return_bytes = 64, 153 .return_bus_width_bytes = 64, 154 .downspread_percent = 0.38, 155 .dcn_downspread_percent = 0.5, 156 .dram_clock_change_latency_us = 400, 157 .dispclk_dppclk_vco_speed_mhz = 4300.0, 158 .do_urgent_latency_adjustment = true, 159 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 160 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 161 }; 162 163 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 164 { 165 /* defaults */ 166 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 167 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; 168 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 169 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 170 /* For min clocks use as reported by PM FW and report those as min */ 171 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 172 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 173 uint16_t setb_min_uclk_mhz = min_uclk_mhz; 174 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; 175 176 dc_assert_fp_enabled(); 177 178 /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ 179 if (dcfclk_mhz_for_the_second_state) 180 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; 181 else 182 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 183 184 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) 185 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; 186 187 /* Set A - Normal - default values */ 188 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 189 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us; 191 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 193 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 194 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 195 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 196 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 197 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 198 199 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ 200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us; 203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 205 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 206 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 207 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; 208 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 209 210 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 211 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ 212 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { 213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38; 215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us; 216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 219 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 220 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 221 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 222 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 223 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; 224 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; 225 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; 226 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; 227 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; 228 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; 229 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; 230 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; 231 } 232 /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ 233 /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ 234 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; 235 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; 236 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; 237 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD 238 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD 239 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 240 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 241 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 242 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 243 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 244 } 245 246 /* 247 * Finds dummy_latency_index when MCLK switching using firmware based 248 * vblank stretch is enabled. This function will iterate through the 249 * table of dummy pstate latencies until the lowest value that allows 250 * dm_allow_self_refresh_and_mclk_switch to happen is found 251 */ 252 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 253 struct dc_state *context, 254 display_e2e_pipe_params_st *pipes, 255 int pipe_cnt, 256 int vlevel) 257 { 258 const int max_latency_table_entries = 4; 259 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 260 int dummy_latency_index = 0; 261 262 dc_assert_fp_enabled(); 263 264 while (dummy_latency_index < max_latency_table_entries) { 265 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 266 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 267 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 268 269 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && 270 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) 271 break; 272 273 dummy_latency_index++; 274 } 275 276 if (dummy_latency_index == max_latency_table_entries) { 277 ASSERT(dummy_latency_index != max_latency_table_entries); 278 /* If the execution gets here, it means dummy p_states are 279 * not possible. This should never happen and would mean 280 * something is severely wrong. 281 * Here we reset dummy_latency_index to 3, because it is 282 * better to have underflows than system crashes. 283 */ 284 dummy_latency_index = max_latency_table_entries - 1; 285 } 286 287 return dummy_latency_index; 288 } 289 290 /** 291 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 292 * and populate pipe_ctx with those params. 293 * @dc: [in] current dc state 294 * @context: [in] new dc state 295 * @pipes: [in] DML pipe params array 296 * @pipe_cnt: [in] DML pipe count 297 * 298 * This function must be called AFTER the phantom pipes are added to context 299 * and run through DML (so that the DLG params for the phantom pipes can be 300 * populated), and BEFORE we program the timing for the phantom pipes. 301 */ 302 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 303 struct dc_state *context, 304 display_e2e_pipe_params_st *pipes, 305 int pipe_cnt) 306 { 307 uint32_t i, pipe_idx; 308 309 dc_assert_fp_enabled(); 310 311 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 312 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 313 314 if (!pipe->stream) 315 continue; 316 317 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 318 pipes[pipe_idx].pipe.dest.vstartup_start = 319 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 320 pipes[pipe_idx].pipe.dest.vupdate_offset = 321 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 322 pipes[pipe_idx].pipe.dest.vupdate_width = 323 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 324 pipes[pipe_idx].pipe.dest.vready_offset = 325 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 326 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 327 } 328 pipe_idx++; 329 } 330 } 331 332 /** 333 * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe 334 * @context: [in] New DC state to be programmed 335 * @pipe_e2e: [in] DML pipe end to end context 336 * 337 * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both 338 * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is 339 * determined by DPPClk requirements 340 * 341 * This function follows the same policy as DML: 342 * - Check for ODM combine requirements / policy first 343 * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and 344 * MPC is required 345 * 346 * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits). 347 */ 348 uint8_t dcn32_predict_pipe_split(struct dc_state *context, 349 display_e2e_pipe_params_st *pipe_e2e) 350 { 351 double pscl_throughput; 352 double pscl_throughput_chroma; 353 double dpp_clk_single_dpp, clock; 354 double clk_frequency = 0.0; 355 double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; 356 bool total_available_pipes_support = false; 357 uint32_t number_of_dpp = 0; 358 enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled; 359 double req_dispclk_per_surface = 0; 360 uint8_t num_splits = 0; 361 362 dc_assert_fp_enabled(); 363 364 dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, 365 pipe_e2e->pipe.dest.hactive, 366 pipe_e2e->dout.output_format, 367 pipe_e2e->dout.output_type, 368 pipe_e2e->pipe.dest.odm_combine_policy, 369 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 370 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 371 pipe_e2e->dout.dsc_enable != 0, 372 0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */ 373 context->bw_ctx.dml.ip.max_num_dpp, 374 pipe_e2e->pipe.dest.pixel_rate_mhz, 375 context->bw_ctx.dml.soc.dcn_downspread_percent, 376 context->bw_ctx.dml.ip.dispclk_ramp_margin_percent, 377 context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz, 378 pipe_e2e->dout.dsc_slices, 379 /* Output */ 380 &total_available_pipes_support, 381 &number_of_dpp, 382 &odm_mode, 383 &req_dispclk_per_surface); 384 385 dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio, 386 pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c, 387 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio, 388 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c, 389 context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk, 390 context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk, 391 pipe_e2e->pipe.dest.pixel_rate_mhz, 392 pipe_e2e->pipe.src.source_format, 393 pipe_e2e->pipe.scale_taps.htaps, 394 pipe_e2e->pipe.scale_taps.htaps_c, 395 pipe_e2e->pipe.scale_taps.vtaps, 396 pipe_e2e->pipe.scale_taps.vtaps_c, 397 /* Output */ 398 &pscl_throughput, &pscl_throughput_chroma, 399 &dpp_clk_single_dpp); 400 401 clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100); 402 403 if (clock > 0) 404 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock); 405 406 if (odm_mode == dm_odm_combine_mode_2to1) 407 num_splits = 1; 408 else if (odm_mode == dm_odm_combine_mode_4to1) 409 num_splits = 3; 410 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) 411 num_splits = 1; 412 413 return num_splits; 414 } 415 416 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 417 { 418 float memory_bw_kbytes_sec; 419 float fabric_bw_kbytes_sec; 420 float sdp_bw_kbytes_sec; 421 float limiting_bw_kbytes_sec; 422 423 memory_bw_kbytes_sec = entry->dram_speed_mts * 424 dcn3_2_soc.num_chans * 425 dcn3_2_soc.dram_channel_width_bytes * 426 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 427 428 fabric_bw_kbytes_sec = entry->fabricclk_mhz * 429 dcn3_2_soc.return_bus_width_bytes * 430 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 431 432 sdp_bw_kbytes_sec = entry->dcfclk_mhz * 433 dcn3_2_soc.return_bus_width_bytes * 434 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 435 436 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 437 438 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 439 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 440 441 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 442 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 443 444 return limiting_bw_kbytes_sec; 445 } 446 447 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 448 { 449 if (entry->dcfclk_mhz > 0) { 450 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 451 452 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 453 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * 454 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 455 } else if (entry->fabricclk_mhz > 0) { 456 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 457 458 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 459 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * 460 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 461 } else if (entry->dram_speed_mts > 0) { 462 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * 463 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 464 465 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 466 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 467 } 468 } 469 470 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 471 unsigned int *num_entries, 472 struct _vcs_dpi_voltage_scaling_st *entry) 473 { 474 int i = 0; 475 int index = 0; 476 float net_bw_of_new_state = 0; 477 478 dc_assert_fp_enabled(); 479 480 get_optimal_ntuple(entry); 481 482 if (*num_entries == 0) { 483 table[0] = *entry; 484 (*num_entries)++; 485 } else { 486 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 487 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 488 index++; 489 if (index >= *num_entries) 490 break; 491 } 492 493 for (i = *num_entries; i > index; i--) 494 table[i] = table[i - 1]; 495 496 table[index] = *entry; 497 (*num_entries)++; 498 } 499 } 500 501 /** 502 * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream 503 * @dc: current dc state 504 * @context: new dc state 505 * @ref_pipe: Main pipe for the phantom stream 506 * @phantom_stream: target phantom stream state 507 * @pipes: DML pipe params 508 * @pipe_cnt: number of DML pipes 509 * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) 510 * 511 * Set timing params of the phantom stream based on calculated output from DML. 512 * This function first gets the DML pipe index using the DC pipe index, then 513 * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of 514 * lines required for SubVP MCLK switching and assigns to the phantom stream 515 * accordingly. 516 * 517 * - The number of SubVP lines calculated in DML does not take into account 518 * FW processing delays and required pstate allow width, so we must include 519 * that separately. 520 * 521 * - Set phantom backporch = vstartup of main pipe 522 */ 523 void dcn32_set_phantom_stream_timing(struct dc *dc, 524 struct dc_state *context, 525 struct pipe_ctx *ref_pipe, 526 struct dc_stream_state *phantom_stream, 527 display_e2e_pipe_params_st *pipes, 528 unsigned int pipe_cnt, 529 unsigned int dc_pipe_idx) 530 { 531 unsigned int i, pipe_idx; 532 struct pipe_ctx *pipe; 533 uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; 534 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; 535 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 536 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; 537 538 dc_assert_fp_enabled(); 539 540 // Find DML pipe index (pipe_idx) using dc_pipe_idx 541 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 542 pipe = &context->res_ctx.pipe_ctx[i]; 543 544 if (!pipe->stream) 545 continue; 546 547 if (i == dc_pipe_idx) 548 break; 549 550 pipe_idx++; 551 } 552 553 // Calculate lines required for pstate allow width and FW processing delays 554 pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + 555 dc->caps.subvp_pstate_allow_width_us) / 1000000) * 556 (ref_pipe->stream->timing.pix_clk_100hz * 100) / 557 (double)ref_pipe->stream->timing.h_total; 558 559 // Update clks_cfg for calling into recalculate 560 pipes[0].clks_cfg.voltage = vlevel; 561 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 562 pipes[0].clks_cfg.socclk_mhz = socclk; 563 564 // DML calculation for MALL region doesn't take into account FW delay 565 // and required pstate allow width for multi-display cases 566 /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned 567 * to 2 swaths (i.e. 16 lines) 568 */ 569 phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + 570 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; 571 572 // For backporch of phantom pipe, use vstartup of the main pipe 573 phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 574 575 phantom_stream->dst.y = 0; 576 phantom_stream->dst.height = phantom_vactive; 577 phantom_stream->src.y = 0; 578 phantom_stream->src.height = phantom_vactive; 579 580 phantom_stream->timing.v_addressable = phantom_vactive; 581 phantom_stream->timing.v_front_porch = 1; 582 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + 583 phantom_stream->timing.v_front_porch + 584 phantom_stream->timing.v_sync_width + 585 phantom_bp; 586 phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing 587 } 588 589 /** 590 * dcn32_get_num_free_pipes - Calculate number of free pipes 591 * @dc: current dc state 592 * @context: new dc state 593 * 594 * This function assumes that a "used" pipe is a pipe that has 595 * both a stream and a plane assigned to it. 596 * 597 * Return: Number of free pipes available in the context 598 */ 599 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) 600 { 601 unsigned int i; 602 unsigned int free_pipes = 0; 603 unsigned int num_pipes = 0; 604 605 for (i = 0; i < dc->res_pool->pipe_count; i++) { 606 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 607 608 if (pipe->stream && !pipe->top_pipe) { 609 while (pipe) { 610 num_pipes++; 611 pipe = pipe->bottom_pipe; 612 } 613 } 614 } 615 616 free_pipes = dc->res_pool->pipe_count - num_pipes; 617 return free_pipes; 618 } 619 620 /** 621 * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP. 622 * @dc: current dc state 623 * @context: new dc state 624 * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned 625 * 626 * We enter this function if we are Sub-VP capable (i.e. enough pipes available) 627 * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if 628 * we are forcing SubVP P-State switching on the current config. 629 * 630 * The number of pipes used for the chosen surface must be less than or equal to the 631 * number of free pipes available. 632 * 633 * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK). 634 * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own 635 * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't 636 * support MCLK switching naturally [i.e. ACTIVE or VBLANK]). 637 * 638 * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. 639 */ 640 static bool dcn32_assign_subvp_pipe(struct dc *dc, 641 struct dc_state *context, 642 unsigned int *index) 643 { 644 unsigned int i, pipe_idx; 645 unsigned int max_frame_time = 0; 646 bool valid_assignment_found = false; 647 unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); 648 bool current_assignment_freesync = false; 649 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 650 651 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 652 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 653 unsigned int num_pipes = 0; 654 unsigned int refresh_rate = 0; 655 656 if (!pipe->stream) 657 continue; 658 659 // Round up 660 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 661 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 662 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 663 /* SubVP pipe candidate requirements: 664 * - Refresh rate < 120hz 665 * - Not able to switch in vactive naturally (switching in active means the 666 * DET provides enough buffer to hide the P-State switch latency -- trying 667 * to combine this with SubVP can cause issues with the scheduling). 668 * - Not TMZ surface 669 */ 670 if (pipe->plane_state && !pipe->top_pipe && 671 pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface && 672 vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { 673 while (pipe) { 674 num_pipes++; 675 pipe = pipe->bottom_pipe; 676 } 677 678 pipe = &context->res_ctx.pipe_ctx[i]; 679 if (num_pipes <= free_pipes) { 680 struct dc_stream_state *stream = pipe->stream; 681 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / 682 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; 683 if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) { 684 *index = i; 685 max_frame_time = frame_us; 686 valid_assignment_found = true; 687 current_assignment_freesync = false; 688 /* For the 2-Freesync display case, still choose the one with the 689 * longest frame time 690 */ 691 } else if (stream->ignore_msa_timing_param && (!valid_assignment_found || 692 (current_assignment_freesync && frame_us > max_frame_time))) { 693 *index = i; 694 valid_assignment_found = true; 695 current_assignment_freesync = true; 696 } 697 } 698 } 699 pipe_idx++; 700 } 701 return valid_assignment_found; 702 } 703 704 /** 705 * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP. 706 * @dc: current dc state 707 * @context: new dc state 708 * 709 * This function returns true if there are enough free pipes 710 * to create the required phantom pipes for any given stream 711 * (that does not already have phantom pipe assigned). 712 * 713 * e.g. For a 2 stream config where the first stream uses one 714 * pipe and the second stream uses 2 pipes (i.e. pipe split), 715 * this function will return true because there is 1 remaining 716 * pipe which can be used as the phantom pipe for the non pipe 717 * split pipe. 718 * 719 * Return: 720 * True if there are enough free pipes to assign phantom pipes to at least one 721 * stream that does not already have phantom pipes assigned. Otherwise false. 722 */ 723 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) 724 { 725 unsigned int i, split_cnt, free_pipes; 726 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 727 bool subvp_possible = false; 728 729 for (i = 0; i < dc->res_pool->pipe_count; i++) { 730 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 731 732 // Find the minimum pipe split count for non SubVP pipes 733 if (pipe->stream && !pipe->top_pipe && 734 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 735 split_cnt = 0; 736 while (pipe) { 737 split_cnt++; 738 pipe = pipe->bottom_pipe; 739 } 740 741 if (split_cnt < min_pipe_split) 742 min_pipe_split = split_cnt; 743 } 744 } 745 746 free_pipes = dcn32_get_num_free_pipes(dc, context); 747 748 // SubVP only possible if at least one pipe is being used (i.e. free_pipes 749 // should not equal to the pipe_count) 750 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) 751 subvp_possible = true; 752 753 return subvp_possible; 754 } 755 756 /** 757 * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable 758 * @dc: current dc state 759 * @context: new dc state 760 * 761 * High level algorithm: 762 * 1. Find longest microschedule length (in us) between the two SubVP pipes 763 * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both 764 * pipes still allows for the maximum microschedule to fit in the active 765 * region for both pipes. 766 * 767 * Return: True if the SubVP + SubVP config is schedulable, false otherwise 768 */ 769 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) 770 { 771 struct pipe_ctx *subvp_pipes[2]; 772 struct dc_stream_state *phantom = NULL; 773 uint32_t microschedule_lines = 0; 774 uint32_t index = 0; 775 uint32_t i; 776 uint32_t max_microschedule_us = 0; 777 int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; 778 779 for (i = 0; i < dc->res_pool->pipe_count; i++) { 780 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 781 uint32_t time_us = 0; 782 783 /* Loop to calculate the maximum microschedule time between the two SubVP pipes, 784 * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. 785 */ 786 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 787 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 788 phantom = pipe->stream->mall_stream_config.paired_stream; 789 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + 790 phantom->timing.v_addressable; 791 792 // Round up when calculating microschedule time (+ 1 at the end) 793 time_us = (microschedule_lines * phantom->timing.h_total) / 794 (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + 795 dc->caps.subvp_prefetch_end_to_mall_start_us + 796 dc->caps.subvp_fw_processing_delay_us + 1; 797 if (time_us > max_microschedule_us) 798 max_microschedule_us = time_us; 799 800 subvp_pipes[index] = pipe; 801 index++; 802 803 // Maximum 2 SubVP pipes 804 if (index == 2) 805 break; 806 } 807 } 808 vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / 809 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 810 vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / 811 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 812 vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * 813 subvp_pipes[0]->stream->timing.h_total) / 814 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 815 vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * 816 subvp_pipes[1]->stream->timing.h_total) / 817 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 818 819 if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && 820 (vactive2_us - vblank1_us) / 2 > max_microschedule_us) 821 return true; 822 823 return false; 824 } 825 826 /** 827 * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable 828 * @dc: current dc state 829 * @context: new dc state 830 * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config 831 * 832 * High level algorithm: 833 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 834 * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching 835 * (the margin is equal to the MALL region + DRR margin (500us)) 836 * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) 837 * then report the configuration as supported 838 * 839 * Return: True if the SubVP + DRR config is schedulable, false otherwise 840 */ 841 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe) 842 { 843 bool schedulable = false; 844 uint32_t i; 845 struct pipe_ctx *pipe = NULL; 846 struct dc_crtc_timing *main_timing = NULL; 847 struct dc_crtc_timing *phantom_timing = NULL; 848 struct dc_crtc_timing *drr_timing = NULL; 849 int16_t prefetch_us = 0; 850 int16_t mall_region_us = 0; 851 int16_t drr_frame_us = 0; // nominal frame time 852 int16_t subvp_active_us = 0; 853 int16_t stretched_drr_us = 0; 854 int16_t drr_stretched_vblank_us = 0; 855 int16_t max_vblank_mallregion = 0; 856 857 // Find SubVP pipe 858 for (i = 0; i < dc->res_pool->pipe_count; i++) { 859 pipe = &context->res_ctx.pipe_ctx[i]; 860 861 // We check for master pipe, but it shouldn't matter since we only need 862 // the pipe for timing info (stream should be same for any pipe splits) 863 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 864 continue; 865 866 // Find the SubVP pipe 867 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 868 break; 869 } 870 871 main_timing = &pipe->stream->timing; 872 phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; 873 drr_timing = &drr_pipe->stream->timing; 874 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 875 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 876 dc->caps.subvp_prefetch_end_to_mall_start_us; 877 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 878 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 879 drr_frame_us = drr_timing->v_total * drr_timing->h_total / 880 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 881 // P-State allow width and FW delays already included phantom_timing->v_addressable 882 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 883 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 884 stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 885 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / 886 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); 887 max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; 888 889 /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the 890 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis 891 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 892 * and the max of (VBLANK blanking time, MALL region)). 893 */ 894 if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && 895 subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) 896 schedulable = true; 897 898 return schedulable; 899 } 900 901 902 /** 903 * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable 904 * @dc: current dc state 905 * @context: new dc state 906 * 907 * High level algorithm: 908 * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe 909 * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) 910 * then report the configuration as supported 911 * 3. If the VBLANK display is DRR, then take the DRR static schedulability path 912 * 913 * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise 914 */ 915 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) 916 { 917 struct pipe_ctx *pipe = NULL; 918 struct pipe_ctx *subvp_pipe = NULL; 919 bool found = false; 920 bool schedulable = false; 921 uint32_t i = 0; 922 uint8_t vblank_index = 0; 923 uint16_t prefetch_us = 0; 924 uint16_t mall_region_us = 0; 925 uint16_t vblank_frame_us = 0; 926 uint16_t subvp_active_us = 0; 927 uint16_t vblank_blank_us = 0; 928 uint16_t max_vblank_mallregion = 0; 929 struct dc_crtc_timing *main_timing = NULL; 930 struct dc_crtc_timing *phantom_timing = NULL; 931 struct dc_crtc_timing *vblank_timing = NULL; 932 933 /* For SubVP + VBLANK/DRR cases, we assume there can only be 934 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK 935 * is supported, it is either a single VBLANK case or two VBLANK 936 * displays which are synchronized (in which case they have identical 937 * timings). 938 */ 939 for (i = 0; i < dc->res_pool->pipe_count; i++) { 940 pipe = &context->res_ctx.pipe_ctx[i]; 941 942 // We check for master pipe, but it shouldn't matter since we only need 943 // the pipe for timing info (stream should be same for any pipe splits) 944 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 945 continue; 946 947 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 948 // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). 949 vblank_index = i; 950 found = true; 951 } 952 953 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 954 subvp_pipe = pipe; 955 } 956 // Use ignore_msa_timing_param flag to identify as DRR 957 if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) { 958 // SUBVP + DRR case 959 schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]); 960 } else if (found) { 961 main_timing = &subvp_pipe->stream->timing; 962 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 963 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; 964 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe 965 // Also include the prefetch end to mallstart delay time 966 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 967 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 968 dc->caps.subvp_prefetch_end_to_mall_start_us; 969 // P-State allow width and FW delays already included phantom_timing->v_addressable 970 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 971 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 972 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / 973 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 974 vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / 975 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 976 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 977 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 978 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; 979 980 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 981 // and the max of (VBLANK blanking time, MALL region) 982 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) 983 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) 984 schedulable = true; 985 } 986 return schedulable; 987 } 988 989 /** 990 * subvp_validate_static_schedulability - Check which SubVP case is calculated 991 * and handle static analysis based on the case. 992 * @dc: current dc state 993 * @context: new dc state 994 * @vlevel: Voltage level calculated by DML 995 * 996 * Three cases: 997 * 1. SubVP + SubVP 998 * 2. SubVP + VBLANK (DRR checked internally) 999 * 3. SubVP + VACTIVE (currently unsupported) 1000 * 1001 * Return: True if statically schedulable, false otherwise 1002 */ 1003 static bool subvp_validate_static_schedulability(struct dc *dc, 1004 struct dc_state *context, 1005 int vlevel) 1006 { 1007 bool schedulable = true; // true by default for single display case 1008 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1009 uint32_t i, pipe_idx; 1010 uint8_t subvp_count = 0; 1011 uint8_t vactive_count = 0; 1012 1013 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1014 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1015 1016 if (!pipe->stream) 1017 continue; 1018 1019 if (pipe->plane_state && !pipe->top_pipe && 1020 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 1021 subvp_count++; 1022 1023 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE 1024 // switching (SubVP + VACTIVE unsupported). In situations where we force 1025 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count. 1026 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && 1027 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1028 vactive_count++; 1029 } 1030 pipe_idx++; 1031 } 1032 1033 if (subvp_count == 2) { 1034 // Static schedulability check for SubVP + SubVP case 1035 schedulable = subvp_subvp_schedulable(dc, context); 1036 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) { 1037 // Static schedulability check for SubVP + VBLANK case. Also handle the case where 1038 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK) 1039 if (vactive_count > 0) 1040 schedulable = false; 1041 else 1042 schedulable = subvp_vblank_schedulable(dc, context); 1043 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp && 1044 vactive_count > 0) { 1045 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default. 1046 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count. 1047 // SubVP + VACTIVE currently unsupported 1048 schedulable = false; 1049 } 1050 return schedulable; 1051 } 1052 1053 static void dcn32_full_validate_bw_helper(struct dc *dc, 1054 struct dc_state *context, 1055 display_e2e_pipe_params_st *pipes, 1056 int *vlevel, 1057 int *split, 1058 bool *merge, 1059 int *pipe_cnt) 1060 { 1061 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1062 unsigned int dc_pipe_idx = 0; 1063 bool found_supported_config = false; 1064 struct pipe_ctx *pipe = NULL; 1065 uint32_t non_subvp_pipes = 0; 1066 bool drr_pipe_found = false; 1067 uint32_t drr_pipe_index = 0; 1068 uint32_t i = 0; 1069 1070 dc_assert_fp_enabled(); 1071 1072 /* 1073 * DML favors voltage over p-state, but we're more interested in 1074 * supporting p-state over voltage. We can't support p-state in 1075 * prefetch mode > 0 so try capping the prefetch mode to start. 1076 * Override present for testing. 1077 */ 1078 if (dc->debug.dml_disallow_alternate_prefetch_modes) 1079 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1080 dm_prefetch_support_uclk_fclk_and_stutter; 1081 else 1082 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1083 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1084 1085 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1086 /* This may adjust vlevel and maxMpcComb */ 1087 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1088 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1089 vba->VoltageLevel = *vlevel; 1090 } 1091 1092 /* Conditions for setting up phantom pipes for SubVP: 1093 * 1. Not force disable SubVP 1094 * 2. Full update (i.e. !fast_validate) 1095 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) 1096 * 4. Display configuration passes validation 1097 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) 1098 */ 1099 if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) && 1100 !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && 1101 (*vlevel == context->bw_ctx.dml.soc.num_states || 1102 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || 1103 dc->debug.force_subvp_mclk_switch)) { 1104 1105 dcn32_merge_pipes_for_subvp(dc, context); 1106 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1107 1108 /* to re-initialize viewport after the pipe merge */ 1109 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1110 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1111 1112 if (!pipe_ctx->plane_state || !pipe_ctx->stream) 1113 continue; 1114 1115 resource_build_scaling_params(pipe_ctx); 1116 } 1117 1118 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && 1119 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { 1120 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. 1121 * Adding phantom pipes won't change the validation result, so change the DML input param 1122 * for P-State support before adding phantom pipes and recalculating the DML result. 1123 * However, this case is only applicable for SubVP + DRR cases because the prefetch mode 1124 * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched 1125 * enough to support MCLK switching. 1126 */ 1127 if (*vlevel == context->bw_ctx.dml.soc.num_states && 1128 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final == 1129 dm_prefetch_support_uclk_fclk_and_stutter) { 1130 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1131 dm_prefetch_support_stutter; 1132 /* There are params (such as FabricClock) that need to be recalculated 1133 * after validation fails (otherwise it will be 0). Calculation for 1134 * phantom vactive requires call into DML, so we must ensure all the 1135 * vba params are valid otherwise we'll get incorrect phantom vactive. 1136 */ 1137 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1138 } 1139 1140 dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); 1141 1142 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1143 // Populate dppclk to trigger a recalculate in dml_get_voltage_level 1144 // so the phantom pipe DLG params can be assigned correctly. 1145 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); 1146 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1147 1148 if (*vlevel < context->bw_ctx.dml.soc.num_states && 1149 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported 1150 && subvp_validate_static_schedulability(dc, context, *vlevel)) { 1151 found_supported_config = true; 1152 } else if (*vlevel < context->bw_ctx.dml.soc.num_states && 1153 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { 1154 /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles 1155 * the case for SubVP + DRR, where the DRR display does not support MCLK switch 1156 * at it's native refresh rate / timing. 1157 */ 1158 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1159 pipe = &context->res_ctx.pipe_ctx[i]; 1160 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 1161 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1162 non_subvp_pipes++; 1163 // Use ignore_msa_timing_param flag to identify as DRR 1164 if (pipe->stream->ignore_msa_timing_param) { 1165 drr_pipe_found = true; 1166 drr_pipe_index = i; 1167 } 1168 } 1169 } 1170 // If there is only 1 remaining non SubVP pipe that is DRR, check static 1171 // schedulability for SubVP + DRR. 1172 if (non_subvp_pipes == 1 && drr_pipe_found) { 1173 found_supported_config = subvp_drr_schedulable(dc, context, 1174 &context->res_ctx.pipe_ctx[drr_pipe_index]); 1175 } 1176 } 1177 } 1178 1179 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) 1180 // remove phantom pipes and repopulate dml pipes 1181 if (!found_supported_config) { 1182 dc->res_pool->funcs->remove_phantom_pipes(dc, context); 1183 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; 1184 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1185 1186 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1187 /* This may adjust vlevel and maxMpcComb */ 1188 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1189 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1190 vba->VoltageLevel = *vlevel; 1191 } 1192 } else { 1193 // Most populate phantom DLG params before programming hardware / timing for phantom pipe 1194 DC_FP_START(); 1195 dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); 1196 DC_FP_END(); 1197 1198 /* Call validate_apply_pipe_split flags after calling DML getters for 1199 * phantom dlg params, or some of the VBA params indicating pipe split 1200 * can be overwritten by the getters. 1201 * 1202 * When setting up SubVP config, all pipes are merged before attempting to 1203 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main 1204 * and phantom pipes will be split in the regular pipe splitting sequence. 1205 */ 1206 memset(split, 0, MAX_PIPES * sizeof(int)); 1207 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1208 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1209 vba->VoltageLevel = *vlevel; 1210 // Note: We can't apply the phantom pipes to hardware at this time. We have to wait 1211 // until driver has acquired the DMCUB lock to do it safely. 1212 } 1213 } 1214 } 1215 1216 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 1217 { 1218 int i; 1219 1220 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1221 if (!context->res_ctx.pipe_ctx[i].stream) 1222 continue; 1223 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 1224 return true; 1225 } 1226 return false; 1227 } 1228 1229 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 1230 display_e2e_pipe_params_st *pipes, 1231 int pipe_cnt, int vlevel) 1232 { 1233 int i, pipe_idx; 1234 bool usr_retraining_support = false; 1235 bool unbounded_req_enabled = false; 1236 1237 dc_assert_fp_enabled(); 1238 1239 /* Writeback MCIF_WB arbitration parameters */ 1240 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1241 1242 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 1243 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 1244 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 1245 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 1246 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 1247 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 1248 context->bw_ctx.bw.dcn.clk.p_state_change_support = 1249 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 1250 != dm_dram_clock_change_unsupported; 1251 context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); 1252 1253 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1254 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 1255 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; 1256 if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) 1257 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; 1258 else 1259 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1260 1261 usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1262 ASSERT(usr_retraining_support); 1263 1264 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 1265 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 1266 1267 unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); 1268 1269 if (unbounded_req_enabled && pipe_cnt > 1) { 1270 // Unbounded requesting should not ever be used when more than 1 pipe is enabled. 1271 ASSERT(false); 1272 unbounded_req_enabled = false; 1273 } 1274 1275 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1276 if (!context->res_ctx.pipe_ctx[i].stream) 1277 continue; 1278 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, 1279 pipe_idx); 1280 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1281 pipe_idx); 1282 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, 1283 pipe_idx); 1284 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1285 pipe_idx); 1286 1287 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1288 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests 1289 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; 1290 context->res_ctx.pipe_ctx[i].unbounded_req = false; 1291 } else { 1292 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, 1293 pipe_idx); 1294 context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; 1295 } 1296 1297 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1298 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1299 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1300 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 1301 pipe_idx++; 1302 } 1303 /*save a original dppclock copy*/ 1304 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 1305 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 1306 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz 1307 * 1000; 1308 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz 1309 * 1000; 1310 1311 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes; 1312 1313 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1314 if (context->res_ctx.pipe_ctx[i].stream) 1315 context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb; 1316 } 1317 1318 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1319 1320 if (!context->res_ctx.pipe_ctx[i].stream) 1321 continue; 1322 1323 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, 1324 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, 1325 pipe_cnt, pipe_idx); 1326 1327 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, 1328 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1329 pipe_idx++; 1330 } 1331 } 1332 1333 static struct pipe_ctx *dcn32_find_split_pipe( 1334 struct dc *dc, 1335 struct dc_state *context, 1336 int old_index) 1337 { 1338 struct pipe_ctx *pipe = NULL; 1339 int i; 1340 1341 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { 1342 pipe = &context->res_ctx.pipe_ctx[old_index]; 1343 pipe->pipe_idx = old_index; 1344 } 1345 1346 if (!pipe) 1347 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1348 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL 1349 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1350 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1351 pipe = &context->res_ctx.pipe_ctx[i]; 1352 pipe->pipe_idx = i; 1353 break; 1354 } 1355 } 1356 } 1357 1358 /* 1359 * May need to fix pipes getting tossed from 1 opp to another on flip 1360 * Add for debugging transient underflow during topology updates: 1361 * ASSERT(pipe); 1362 */ 1363 if (!pipe) 1364 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1365 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1366 pipe = &context->res_ctx.pipe_ctx[i]; 1367 pipe->pipe_idx = i; 1368 break; 1369 } 1370 } 1371 1372 return pipe; 1373 } 1374 1375 static bool dcn32_split_stream_for_mpc_or_odm( 1376 const struct dc *dc, 1377 struct resource_context *res_ctx, 1378 struct pipe_ctx *pri_pipe, 1379 struct pipe_ctx *sec_pipe, 1380 bool odm) 1381 { 1382 int pipe_idx = sec_pipe->pipe_idx; 1383 const struct resource_pool *pool = dc->res_pool; 1384 1385 DC_LOGGER_INIT(dc->ctx->logger); 1386 1387 if (odm && pri_pipe->plane_state) { 1388 /* ODM + window MPO, where MPO window is on left half only */ 1389 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= 1390 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1391 1392 DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n", 1393 __func__, 1394 pri_pipe->pipe_idx); 1395 return true; 1396 } 1397 1398 /* ODM + window MPO, where MPO window is on right half only */ 1399 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1400 1401 DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n", 1402 __func__, 1403 pri_pipe->pipe_idx); 1404 return true; 1405 } 1406 } 1407 1408 *sec_pipe = *pri_pipe; 1409 1410 sec_pipe->pipe_idx = pipe_idx; 1411 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1412 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1413 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1414 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1415 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1416 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1417 sec_pipe->stream_res.dsc = NULL; 1418 if (odm) { 1419 if (pri_pipe->next_odm_pipe) { 1420 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1421 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1422 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1423 } 1424 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { 1425 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; 1426 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; 1427 } 1428 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { 1429 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; 1430 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; 1431 } 1432 pri_pipe->next_odm_pipe = sec_pipe; 1433 sec_pipe->prev_odm_pipe = pri_pipe; 1434 ASSERT(sec_pipe->top_pipe == NULL); 1435 1436 if (!sec_pipe->top_pipe) 1437 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1438 else 1439 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 1440 if (sec_pipe->stream->timing.flags.DSC == 1) { 1441 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1442 ASSERT(sec_pipe->stream_res.dsc); 1443 if (sec_pipe->stream_res.dsc == NULL) 1444 return false; 1445 } 1446 } else { 1447 if (pri_pipe->bottom_pipe) { 1448 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1449 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1450 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1451 } 1452 pri_pipe->bottom_pipe = sec_pipe; 1453 sec_pipe->top_pipe = pri_pipe; 1454 1455 ASSERT(pri_pipe->plane_state); 1456 } 1457 1458 return true; 1459 } 1460 1461 bool dcn32_internal_validate_bw(struct dc *dc, 1462 struct dc_state *context, 1463 display_e2e_pipe_params_st *pipes, 1464 int *pipe_cnt_out, 1465 int *vlevel_out, 1466 bool fast_validate) 1467 { 1468 bool out = false; 1469 bool repopulate_pipes = false; 1470 int split[MAX_PIPES] = { 0 }; 1471 bool merge[MAX_PIPES] = { false }; 1472 bool newly_split[MAX_PIPES] = { false }; 1473 int pipe_cnt, i, pipe_idx; 1474 int vlevel = context->bw_ctx.dml.soc.num_states; 1475 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1476 1477 dc_assert_fp_enabled(); 1478 1479 ASSERT(pipes); 1480 if (!pipes) 1481 return false; 1482 1483 // For each full update, remove all existing phantom pipes first 1484 dc->res_pool->funcs->remove_phantom_pipes(dc, context); 1485 1486 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1487 1488 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1489 1490 if (!pipe_cnt) { 1491 out = true; 1492 goto validate_out; 1493 } 1494 1495 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1496 1497 if (!fast_validate) { 1498 DC_FP_START(); 1499 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); 1500 DC_FP_END(); 1501 } 1502 1503 if (fast_validate || 1504 (dc->debug.dml_disallow_alternate_prefetch_modes && 1505 (vlevel == context->bw_ctx.dml.soc.num_states || 1506 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { 1507 /* 1508 * If dml_disallow_alternate_prefetch_modes is false, then we have already 1509 * tried alternate prefetch modes during full validation. 1510 * 1511 * If mode is unsupported or there is no p-state support, then 1512 * fall back to favouring voltage. 1513 * 1514 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try 1515 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2) 1516 */ 1517 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1518 dm_prefetch_support_fclk_and_stutter; 1519 1520 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1521 1522 /* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */ 1523 if (vlevel == context->bw_ctx.dml.soc.num_states) { 1524 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1525 dm_prefetch_support_stutter; 1526 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1527 } 1528 1529 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1530 memset(split, 0, sizeof(split)); 1531 memset(merge, 0, sizeof(merge)); 1532 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1533 // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML 1534 vba->VoltageLevel = vlevel; 1535 } 1536 } 1537 1538 dml_log_mode_support_params(&context->bw_ctx.dml); 1539 1540 if (vlevel == context->bw_ctx.dml.soc.num_states) 1541 goto validate_fail; 1542 1543 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1544 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1545 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1546 1547 if (!pipe->stream) 1548 continue; 1549 1550 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1551 && !dc->config.enable_windowed_mpo_odm 1552 && pipe->plane_state && mpo_pipe 1553 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1554 &pipe->plane_res.scl_data.recout, 1555 sizeof(struct rect)) != 0) { 1556 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1557 goto validate_fail; 1558 } 1559 pipe_idx++; 1560 } 1561 1562 /* merge pipes if necessary */ 1563 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1564 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1565 1566 /*skip pipes that don't need merging*/ 1567 if (!merge[i]) 1568 continue; 1569 1570 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 1571 if (pipe->prev_odm_pipe) { 1572 /*split off odm pipe*/ 1573 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 1574 if (pipe->next_odm_pipe) 1575 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 1576 1577 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/ 1578 if (pipe->bottom_pipe) { 1579 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) { 1580 /*MPC split rules will handle this case*/ 1581 pipe->bottom_pipe->top_pipe = NULL; 1582 } else { 1583 /* when merging an ODM pipes, the bottom MPC pipe must now point to 1584 * the previous ODM pipe and its associated stream assets 1585 */ 1586 if (pipe->prev_odm_pipe->bottom_pipe) { 1587 /* 3 plane MPO*/ 1588 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe; 1589 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; 1590 } else { 1591 /* 2 plane MPO*/ 1592 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe; 1593 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; 1594 } 1595 1596 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource)); 1597 } 1598 } 1599 1600 if (pipe->top_pipe) { 1601 pipe->top_pipe->bottom_pipe = NULL; 1602 } 1603 1604 pipe->bottom_pipe = NULL; 1605 pipe->next_odm_pipe = NULL; 1606 pipe->plane_state = NULL; 1607 pipe->stream = NULL; 1608 pipe->top_pipe = NULL; 1609 pipe->prev_odm_pipe = NULL; 1610 if (pipe->stream_res.dsc) 1611 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 1612 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1613 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1614 repopulate_pipes = true; 1615 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 1616 struct pipe_ctx *top_pipe = pipe->top_pipe; 1617 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 1618 1619 top_pipe->bottom_pipe = bottom_pipe; 1620 if (bottom_pipe) 1621 bottom_pipe->top_pipe = top_pipe; 1622 1623 pipe->top_pipe = NULL; 1624 pipe->bottom_pipe = NULL; 1625 pipe->plane_state = NULL; 1626 pipe->stream = NULL; 1627 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1628 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1629 repopulate_pipes = true; 1630 } else 1631 ASSERT(0); /* Should never try to merge master pipe */ 1632 1633 } 1634 1635 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1636 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1637 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1638 struct pipe_ctx *hsplit_pipe = NULL; 1639 bool odm; 1640 int old_index = -1; 1641 1642 if (!pipe->stream || newly_split[i]) 1643 continue; 1644 1645 pipe_idx++; 1646 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 1647 1648 if (!pipe->plane_state && !odm) 1649 continue; 1650 1651 if (split[i]) { 1652 if (odm) { 1653 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) 1654 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1655 else if (old_pipe->next_odm_pipe) 1656 old_index = old_pipe->next_odm_pipe->pipe_idx; 1657 } else { 1658 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1659 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1660 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1661 else if (old_pipe->bottom_pipe && 1662 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1663 old_index = old_pipe->bottom_pipe->pipe_idx; 1664 } 1665 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); 1666 ASSERT(hsplit_pipe); 1667 if (!hsplit_pipe) 1668 goto validate_fail; 1669 1670 if (!dcn32_split_stream_for_mpc_or_odm( 1671 dc, &context->res_ctx, 1672 pipe, hsplit_pipe, odm)) 1673 goto validate_fail; 1674 1675 newly_split[hsplit_pipe->pipe_idx] = true; 1676 repopulate_pipes = true; 1677 } 1678 if (split[i] == 4) { 1679 struct pipe_ctx *pipe_4to1; 1680 1681 if (odm && old_pipe->next_odm_pipe) 1682 old_index = old_pipe->next_odm_pipe->pipe_idx; 1683 else if (!odm && old_pipe->bottom_pipe && 1684 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1685 old_index = old_pipe->bottom_pipe->pipe_idx; 1686 else 1687 old_index = -1; 1688 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1689 ASSERT(pipe_4to1); 1690 if (!pipe_4to1) 1691 goto validate_fail; 1692 if (!dcn32_split_stream_for_mpc_or_odm( 1693 dc, &context->res_ctx, 1694 pipe, pipe_4to1, odm)) 1695 goto validate_fail; 1696 newly_split[pipe_4to1->pipe_idx] = true; 1697 1698 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe 1699 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) 1700 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1701 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1702 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && 1703 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1704 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1705 else 1706 old_index = -1; 1707 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1708 ASSERT(pipe_4to1); 1709 if (!pipe_4to1) 1710 goto validate_fail; 1711 if (!dcn32_split_stream_for_mpc_or_odm( 1712 dc, &context->res_ctx, 1713 hsplit_pipe, pipe_4to1, odm)) 1714 goto validate_fail; 1715 newly_split[pipe_4to1->pipe_idx] = true; 1716 } 1717 if (odm) 1718 dcn20_build_mapped_resource(dc, context, pipe->stream); 1719 } 1720 1721 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1722 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1723 1724 if (pipe->plane_state) { 1725 if (!resource_build_scaling_params(pipe)) 1726 goto validate_fail; 1727 } 1728 } 1729 1730 /* Actual dsc count per stream dsc validation*/ 1731 if (!dcn20_validate_dsc(dc, context)) { 1732 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 1733 goto validate_fail; 1734 } 1735 1736 if (repopulate_pipes) { 1737 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1738 1739 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case 1740 * we have to re-calculate the DET allocation and run through DML once more to 1741 * ensure all the params are calculated correctly. We do not need to run the 1742 * pipe split check again after this call (pipes are already split / merged). 1743 * */ 1744 if (!fast_validate) { 1745 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1746 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1747 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1748 } 1749 } 1750 *vlevel_out = vlevel; 1751 *pipe_cnt_out = pipe_cnt; 1752 1753 out = true; 1754 goto validate_out; 1755 1756 validate_fail: 1757 out = false; 1758 1759 validate_out: 1760 return out; 1761 } 1762 1763 1764 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 1765 display_e2e_pipe_params_st *pipes, 1766 int pipe_cnt, 1767 int vlevel) 1768 { 1769 int i, pipe_idx, vlevel_temp = 0; 1770 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 1771 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1772 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; 1773 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 1774 dm_dram_clock_change_unsupported; 1775 unsigned int dummy_latency_index = 0; 1776 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1777 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1778 unsigned int min_dram_speed_mts_margin; 1779 1780 dc_assert_fp_enabled(); 1781 1782 // Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK 1783 if (!pstate_en && dcn32_subvp_in_use(dc, context)) { 1784 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 1785 pstate_en = true; 1786 } 1787 1788 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1789 1790 if (!pstate_en) { 1791 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ 1792 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = 1793 dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); 1794 1795 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 1796 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 1797 context, pipes, pipe_cnt, vlevel); 1798 1799 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch 1800 * we reinstate the original dram_clock_change_latency_us on the context 1801 * and all variables that may have changed up to this point, except the 1802 * newly found dummy_latency_index 1803 */ 1804 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1805 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 1806 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 1807 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1808 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1809 pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != 1810 dm_dram_clock_change_unsupported; 1811 } 1812 } 1813 1814 /* Set B: 1815 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, 1816 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark 1817 * calculations to cover bootup clocks. 1818 * DCFCLK: soc.clock_limits[2] when available 1819 * UCLK: soc.clock_limits[2] when available 1820 */ 1821 if (dcn3_2_soc.num_states > 2) { 1822 vlevel_temp = 2; 1823 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; 1824 } else 1825 dcfclk = 615; //DCFCLK Vmin_lv 1826 1827 pipes[0].clks_cfg.voltage = vlevel_temp; 1828 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1829 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 1830 1831 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1832 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1833 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us; 1834 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1835 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1836 } 1837 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1838 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1839 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1840 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1841 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1842 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1843 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1844 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1845 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1846 context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1847 1848 /* Set D: 1849 * All clocks min. 1850 * DCFCLK: Min, as reported by PM FW when available 1851 * UCLK : Min, as reported by PM FW when available 1852 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) 1853 */ 1854 1855 if (dcn3_2_soc.num_states > 2) { 1856 vlevel_temp = 0; 1857 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; 1858 } else 1859 dcfclk = 615; //DCFCLK Vmin_lv 1860 1861 pipes[0].clks_cfg.voltage = vlevel_temp; 1862 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1863 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 1864 1865 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1866 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1867 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us; 1868 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1869 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1870 } 1871 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1872 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1873 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1874 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1875 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1876 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1877 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1878 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1879 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1880 context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1881 1882 /* Set C, for Dummy P-State: 1883 * All clocks min. 1884 * DCFCLK: Min, as reported by PM FW, when available 1885 * UCLK : Min, as reported by PM FW, when available 1886 * pstate latency as per UCLK state dummy pstate latency 1887 */ 1888 1889 // For Set A and Set C use values from validation 1890 pipes[0].clks_cfg.voltage = vlevel; 1891 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; 1892 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1893 1894 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 1895 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching; 1896 } 1897 1898 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1899 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1900 min_dram_speed_mts_margin = 160; 1901 1902 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1903 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; 1904 1905 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == 1906 dm_dram_clock_change_unsupported) { 1907 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1; 1908 1909 min_dram_speed_mts = 1910 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; 1911 } 1912 1913 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 1914 /* find largest table entry that is lower than dram speed, 1915 * but lower than DPM0 still uses DPM0 1916 */ 1917 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) 1918 if (min_dram_speed_mts + min_dram_speed_mts_margin > 1919 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) 1920 break; 1921 } 1922 1923 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1924 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 1925 1926 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us; 1927 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1928 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1929 } 1930 1931 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1932 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1933 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1934 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1935 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1936 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1937 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1938 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1939 /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. 1940 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM 1941 * value. 1942 */ 1943 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1944 context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1945 1946 if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { 1947 /* The only difference between A and C is p-state latency, if p-state is not supported 1948 * with full p-state latency we want to calculate DLG based on dummy p-state latency, 1949 * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30. 1950 */ 1951 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 1952 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 1953 } else { 1954 /* Set A: 1955 * All clocks min. 1956 * DCFCLK: Min, as reported by PM FW, when available 1957 * UCLK: Min, as reported by PM FW, when available 1958 */ 1959 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1960 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1961 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1962 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1963 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1964 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1965 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1966 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1967 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1968 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1969 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1970 } 1971 1972 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1973 if (!context->res_ctx.pipe_ctx[i].stream) 1974 continue; 1975 1976 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1977 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1978 1979 if (dc->config.forced_clocks) { 1980 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1981 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1982 } 1983 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1984 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1985 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1986 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1987 1988 pipe_idx++; 1989 } 1990 1991 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 1992 1993 dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1994 1995 if (!pstate_en) 1996 /* Restore full p-state latency */ 1997 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1998 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 1999 2000 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) 2001 dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context); 2002 } 2003 2004 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 2005 unsigned int *optimal_dcfclk, 2006 unsigned int *optimal_fclk) 2007 { 2008 double bw_from_dram, bw_from_dram1, bw_from_dram2; 2009 2010 bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * 2011 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); 2012 bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * 2013 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); 2014 2015 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 2016 2017 if (optimal_fclk) 2018 *optimal_fclk = bw_from_dram / 2019 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2020 2021 if (optimal_dcfclk) 2022 *optimal_dcfclk = bw_from_dram / 2023 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2024 } 2025 2026 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 2027 unsigned int index) 2028 { 2029 int i; 2030 2031 if (*num_entries == 0) 2032 return; 2033 2034 for (i = index; i < *num_entries - 1; i++) { 2035 table[i] = table[i + 1]; 2036 } 2037 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 2038 } 2039 2040 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) 2041 { 2042 int i; 2043 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2044 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2045 2046 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2047 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2048 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2049 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2050 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2051 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2052 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2053 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2054 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2055 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2056 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2057 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2058 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2059 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2060 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2061 } 2062 2063 /* Scan through clock values we currently have and if they are 0, 2064 * then populate it with dcn3_2_soc.clock_limits[] value. 2065 * 2066 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being 2067 * 0, will cause it to skip building the clock table. 2068 */ 2069 if (max_dcfclk_mhz == 0) 2070 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2071 if (max_dispclk_mhz == 0) 2072 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2073 if (max_dtbclk_mhz == 0) 2074 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; 2075 if (max_uclk_mhz == 0) 2076 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; 2077 } 2078 2079 static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 2080 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2081 { 2082 int i, j; 2083 struct _vcs_dpi_voltage_scaling_st entry = {0}; 2084 2085 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2086 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2087 2088 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 2089 2090 static const unsigned int num_dcfclk_stas = 5; 2091 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2092 2093 unsigned int num_uclk_dpms = 0; 2094 unsigned int num_fclk_dpms = 0; 2095 unsigned int num_dcfclk_dpms = 0; 2096 2097 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2098 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2099 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2100 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2101 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2102 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2103 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2104 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2105 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2106 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2107 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2108 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2109 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2110 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2111 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2112 2113 if (bw_params->clk_table.entries[i].memclk_mhz > 0) 2114 num_uclk_dpms++; 2115 if (bw_params->clk_table.entries[i].fclk_mhz > 0) 2116 num_fclk_dpms++; 2117 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 2118 num_dcfclk_dpms++; 2119 } 2120 2121 if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 2122 return -1; 2123 2124 if (max_dppclk_mhz == 0) 2125 max_dppclk_mhz = max_dispclk_mhz; 2126 2127 if (max_fclk_mhz == 0) 2128 max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; 2129 2130 if (max_phyclk_mhz == 0) 2131 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2132 2133 *num_entries = 0; 2134 entry.dispclk_mhz = max_dispclk_mhz; 2135 entry.dscclk_mhz = max_dispclk_mhz / 3; 2136 entry.dppclk_mhz = max_dppclk_mhz; 2137 entry.dtbclk_mhz = max_dtbclk_mhz; 2138 entry.phyclk_mhz = max_phyclk_mhz; 2139 entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2140 entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2141 2142 // Insert all the DCFCLK STAs 2143 for (i = 0; i < num_dcfclk_stas; i++) { 2144 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 2145 entry.fabricclk_mhz = 0; 2146 entry.dram_speed_mts = 0; 2147 2148 DC_FP_START(); 2149 insert_entry_into_table_sorted(table, num_entries, &entry); 2150 DC_FP_END(); 2151 } 2152 2153 // Insert the max DCFCLK 2154 entry.dcfclk_mhz = max_dcfclk_mhz; 2155 entry.fabricclk_mhz = 0; 2156 entry.dram_speed_mts = 0; 2157 2158 DC_FP_START(); 2159 insert_entry_into_table_sorted(table, num_entries, &entry); 2160 DC_FP_END(); 2161 2162 // Insert the UCLK DPMS 2163 for (i = 0; i < num_uclk_dpms; i++) { 2164 entry.dcfclk_mhz = 0; 2165 entry.fabricclk_mhz = 0; 2166 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 2167 2168 DC_FP_START(); 2169 insert_entry_into_table_sorted(table, num_entries, &entry); 2170 DC_FP_END(); 2171 } 2172 2173 // If FCLK is coarse grained, insert individual DPMs. 2174 if (num_fclk_dpms > 2) { 2175 for (i = 0; i < num_fclk_dpms; i++) { 2176 entry.dcfclk_mhz = 0; 2177 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2178 entry.dram_speed_mts = 0; 2179 2180 DC_FP_START(); 2181 insert_entry_into_table_sorted(table, num_entries, &entry); 2182 DC_FP_END(); 2183 } 2184 } 2185 // If FCLK fine grained, only insert max 2186 else { 2187 entry.dcfclk_mhz = 0; 2188 entry.fabricclk_mhz = max_fclk_mhz; 2189 entry.dram_speed_mts = 0; 2190 2191 DC_FP_START(); 2192 insert_entry_into_table_sorted(table, num_entries, &entry); 2193 DC_FP_END(); 2194 } 2195 2196 // At this point, the table contains all "points of interest" based on 2197 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 2198 // ratios (by derate, are exact). 2199 2200 // Remove states that require higher clocks than are supported 2201 for (i = *num_entries - 1; i >= 0 ; i--) { 2202 if (table[i].dcfclk_mhz > max_dcfclk_mhz || 2203 table[i].fabricclk_mhz > max_fclk_mhz || 2204 table[i].dram_speed_mts > max_uclk_mhz * 16) 2205 remove_entry_from_table_at_index(table, num_entries, i); 2206 } 2207 2208 // At this point, the table only contains supported points of interest 2209 // it could be used as is, but some states may be redundant due to 2210 // coarse grained nature of some clocks, so we want to round up to 2211 // coarse grained DPMs and remove duplicates. 2212 2213 // Round up UCLKs 2214 for (i = *num_entries - 1; i >= 0 ; i--) { 2215 for (j = 0; j < num_uclk_dpms; j++) { 2216 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 2217 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 2218 break; 2219 } 2220 } 2221 } 2222 2223 // If FCLK is coarse grained, round up to next DPMs 2224 if (num_fclk_dpms > 2) { 2225 for (i = *num_entries - 1; i >= 0 ; i--) { 2226 for (j = 0; j < num_fclk_dpms; j++) { 2227 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 2228 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 2229 break; 2230 } 2231 } 2232 } 2233 } 2234 // Otherwise, round up to minimum. 2235 else { 2236 for (i = *num_entries - 1; i >= 0 ; i--) { 2237 if (table[i].fabricclk_mhz < min_fclk_mhz) { 2238 table[i].fabricclk_mhz = min_fclk_mhz; 2239 break; 2240 } 2241 } 2242 } 2243 2244 // Round DCFCLKs up to minimum 2245 for (i = *num_entries - 1; i >= 0 ; i--) { 2246 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 2247 table[i].dcfclk_mhz = min_dcfclk_mhz; 2248 break; 2249 } 2250 } 2251 2252 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 2253 i = 0; 2254 while (i < *num_entries - 1) { 2255 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 2256 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 2257 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 2258 remove_entry_from_table_at_index(table, num_entries, i + 1); 2259 else 2260 i++; 2261 } 2262 2263 // Fix up the state indicies 2264 for (i = *num_entries - 1; i >= 0 ; i--) { 2265 table[i].state = i; 2266 } 2267 2268 return 0; 2269 } 2270 2271 /* 2272 * dcn32_update_bw_bounding_box 2273 * 2274 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from 2275 * spreadsheet with actual values as per dGPU SKU: 2276 * - with passed few options from dc->config 2277 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might 2278 * need to get it from PM FW) 2279 * - with passed latency values (passed in ns units) in dc-> bb override for 2280 * debugging purposes 2281 * - with passed latencies from VBIOS (in 100_ns units) if available for 2282 * certain dGPU SKU 2283 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU 2284 * of the same ASIC) 2285 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM 2286 * FW for different clocks (which might differ for certain dGPU SKU of the 2287 * same ASIC) 2288 */ 2289 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 2290 { 2291 dc_assert_fp_enabled(); 2292 2293 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2294 /* Overrides from dc->config options */ 2295 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 2296 2297 /* Override from passed dc->bb_overrides if available*/ 2298 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 2299 && dc->bb_overrides.sr_exit_time_ns) { 2300 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 2301 } 2302 2303 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) 2304 != dc->bb_overrides.sr_enter_plus_exit_time_ns 2305 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 2306 dcn3_2_soc.sr_enter_plus_exit_time_us = 2307 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 2308 } 2309 2310 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 2311 && dc->bb_overrides.urgent_latency_ns) { 2312 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2313 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2314 } 2315 2316 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) 2317 != dc->bb_overrides.dram_clock_change_latency_ns 2318 && dc->bb_overrides.dram_clock_change_latency_ns) { 2319 dcn3_2_soc.dram_clock_change_latency_us = 2320 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 2321 } 2322 2323 if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000) 2324 != dc->bb_overrides.fclk_clock_change_latency_ns 2325 && dc->bb_overrides.fclk_clock_change_latency_ns) { 2326 dcn3_2_soc.fclk_change_latency_us = 2327 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 2328 } 2329 2330 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) 2331 != dc->bb_overrides.dummy_clock_change_latency_ns 2332 && dc->bb_overrides.dummy_clock_change_latency_ns) { 2333 dcn3_2_soc.dummy_pstate_latency_us = 2334 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 2335 } 2336 2337 /* Override from VBIOS if VBIOS bb_info available */ 2338 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 2339 struct bp_soc_bb_info bb_info = {0}; 2340 2341 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 2342 if (bb_info.dram_clock_change_latency_100ns > 0) 2343 dcn3_2_soc.dram_clock_change_latency_us = 2344 bb_info.dram_clock_change_latency_100ns * 10; 2345 2346 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 2347 dcn3_2_soc.sr_enter_plus_exit_time_us = 2348 bb_info.dram_sr_enter_exit_latency_100ns * 10; 2349 2350 if (bb_info.dram_sr_exit_latency_100ns > 0) 2351 dcn3_2_soc.sr_exit_time_us = 2352 bb_info.dram_sr_exit_latency_100ns * 10; 2353 } 2354 } 2355 2356 /* Override from VBIOS for num_chan */ 2357 if (dc->ctx->dc_bios->vram_info.num_chans) 2358 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2359 2360 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2361 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2362 } 2363 2364 /* DML DSC delay factor workaround */ 2365 dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 2366 2367 dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 2368 2369 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 2370 dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2371 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2372 2373 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 2374 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 2375 if (dc->debug.use_legacy_soc_bb_mechanism) { 2376 unsigned int i = 0, j = 0, num_states = 0; 2377 2378 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2379 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2380 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2381 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2382 unsigned int min_dcfclk = UINT_MAX; 2383 /* Set 199 as first value in STA target array to have a minimum DCFCLK value. 2384 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */ 2385 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2386 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 2387 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 2388 2389 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2390 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2391 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2392 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && 2393 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk) 2394 min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz; 2395 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2396 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2397 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2398 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2399 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2400 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2401 } 2402 if (min_dcfclk > dcfclk_sta_targets[0]) 2403 dcfclk_sta_targets[0] = min_dcfclk; 2404 if (!max_dcfclk_mhz) 2405 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2406 if (!max_dispclk_mhz) 2407 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2408 if (!max_dppclk_mhz) 2409 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; 2410 if (!max_phyclk_mhz) 2411 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2412 2413 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2414 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2415 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2416 num_dcfclk_sta_targets++; 2417 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2418 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2419 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2420 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2421 dcfclk_sta_targets[i] = max_dcfclk_mhz; 2422 break; 2423 } 2424 } 2425 // Update size of array since we "removed" duplicates 2426 num_dcfclk_sta_targets = i + 1; 2427 } 2428 2429 num_uclk_states = bw_params->clk_table.num_entries; 2430 2431 // Calculate optimal dcfclk for each uclk 2432 for (i = 0; i < num_uclk_states; i++) { 2433 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2434 &optimal_dcfclk_for_uclk[i], NULL); 2435 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2436 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2437 } 2438 } 2439 2440 // Calculate optimal uclk for each dcfclk sta target 2441 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2442 for (j = 0; j < num_uclk_states; j++) { 2443 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2444 optimal_uclk_for_dcfclk_sta_targets[i] = 2445 bw_params->clk_table.entries[j].memclk_mhz * 16; 2446 break; 2447 } 2448 } 2449 } 2450 2451 i = 0; 2452 j = 0; 2453 // create the final dcfclk and uclk table 2454 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2455 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2456 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2457 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2458 } else { 2459 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2460 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2461 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2462 } else { 2463 j = num_uclk_states; 2464 } 2465 } 2466 } 2467 2468 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2469 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2470 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2471 } 2472 2473 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2474 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2475 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2476 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2477 } 2478 2479 dcn3_2_soc.num_states = num_states; 2480 for (i = 0; i < dcn3_2_soc.num_states; i++) { 2481 dcn3_2_soc.clock_limits[i].state = i; 2482 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2483 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2484 2485 /* Fill all states with max values of all these clocks */ 2486 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2487 dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2488 dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2489 dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 2490 2491 /* Populate from bw_params for DTBCLK, SOCCLK */ 2492 if (i > 0) { 2493 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 2494 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; 2495 } else { 2496 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2497 } 2498 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 2499 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2500 } 2501 2502 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 2503 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; 2504 else 2505 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 2506 2507 if (!dram_speed_mts[i] && i > 0) 2508 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; 2509 else 2510 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2511 2512 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ 2513 /* PHYCLK_D18, PHYCLK_D32 */ 2514 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2515 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2516 } 2517 } else { 2518 build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); 2519 } 2520 2521 /* Re-init DML with updated bb */ 2522 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2523 if (dc->current_state) 2524 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2525 } 2526 } 2527 2528