1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include "dcn32_fpu.h" 27 #include "dcn32/dcn32_resource.h" 28 #include "dcn20/dcn20_resource.h" 29 #include "display_mode_vba_util_32.h" 30 #include "dml/dcn32/display_mode_vba_32.h" 31 // We need this includes for WATERMARKS_* defines 32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" 33 #include "dcn30/dcn30_resource.h" 34 #include "link.h" 35 36 #define DC_LOGGER_INIT(logger) 37 38 static const struct subvp_high_refresh_list subvp_high_refresh_list = { 39 .min_refresh = 120, 40 .max_refresh = 175, 41 .res = { 42 {.width = 3840, .height = 2160, }, 43 {.width = 3440, .height = 1440, }, 44 {.width = 2560, .height = 1440, }}, 45 }; 46 47 struct _vcs_dpi_ip_params_st dcn3_2_ip = { 48 .gpuvm_enable = 0, 49 .gpuvm_max_page_table_levels = 4, 50 .hostvm_enable = 0, 51 .rob_buffer_size_kbytes = 128, 52 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 53 .config_return_buffer_size_in_kbytes = 1280, 54 .compressed_buffer_segment_size_in_kbytes = 64, 55 .meta_fifo_size_in_kentries = 22, 56 .zero_size_buffer_entries = 512, 57 .compbuf_reserved_space_64b = 256, 58 .compbuf_reserved_space_zs = 64, 59 .dpp_output_buffer_pixels = 2560, 60 .opp_output_buffer_lines = 1, 61 .pixel_chunk_size_kbytes = 8, 62 .alpha_pixel_chunk_size_kbytes = 4, 63 .min_pixel_chunk_size_bytes = 1024, 64 .dcc_meta_buffer_size_bytes = 6272, 65 .meta_chunk_size_kbytes = 2, 66 .min_meta_chunk_size_bytes = 256, 67 .writeback_chunk_size_kbytes = 8, 68 .ptoi_supported = false, 69 .num_dsc = 4, 70 .maximum_dsc_bits_per_component = 12, 71 .maximum_pixels_per_line_per_dsc_unit = 6016, 72 .dsc422_native_support = true, 73 .is_line_buffer_bpp_fixed = true, 74 .line_buffer_fixed_bpp = 57, 75 .line_buffer_size_bits = 1171920, 76 .max_line_buffer_lines = 32, 77 .writeback_interface_buffer_size_kbytes = 90, 78 .max_num_dpp = 4, 79 .max_num_otg = 4, 80 .max_num_hdmi_frl_outputs = 1, 81 .max_num_wb = 1, 82 .max_dchub_pscl_bw_pix_per_clk = 4, 83 .max_pscl_lb_bw_pix_per_clk = 2, 84 .max_lb_vscl_bw_pix_per_clk = 4, 85 .max_vscl_hscl_bw_pix_per_clk = 4, 86 .max_hscl_ratio = 6, 87 .max_vscl_ratio = 6, 88 .max_hscl_taps = 8, 89 .max_vscl_taps = 8, 90 .dpte_buffer_size_in_pte_reqs_luma = 64, 91 .dpte_buffer_size_in_pte_reqs_chroma = 34, 92 .dispclk_ramp_margin_percent = 1, 93 .max_inter_dcn_tile_repeaters = 8, 94 .cursor_buffer_size = 16, 95 .cursor_chunk_size = 2, 96 .writeback_line_buffer_buffer_size = 0, 97 .writeback_min_hscl_ratio = 1, 98 .writeback_min_vscl_ratio = 1, 99 .writeback_max_hscl_ratio = 1, 100 .writeback_max_vscl_ratio = 1, 101 .writeback_max_hscl_taps = 1, 102 .writeback_max_vscl_taps = 1, 103 .dppclk_delay_subtotal = 47, 104 .dppclk_delay_scl = 50, 105 .dppclk_delay_scl_lb_only = 16, 106 .dppclk_delay_cnvc_formatter = 28, 107 .dppclk_delay_cnvc_cursor = 6, 108 .dispclk_delay_subtotal = 125, 109 .dynamic_metadata_vm_enabled = false, 110 .odm_combine_4to1_supported = false, 111 .dcc_supported = true, 112 .max_num_dp2p0_outputs = 2, 113 .max_num_dp2p0_streams = 4, 114 }; 115 116 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { 117 .clock_limits = { 118 { 119 .state = 0, 120 .dcfclk_mhz = 1564.0, 121 .fabricclk_mhz = 2500.0, 122 .dispclk_mhz = 2150.0, 123 .dppclk_mhz = 2150.0, 124 .phyclk_mhz = 810.0, 125 .phyclk_d18_mhz = 667.0, 126 .phyclk_d32_mhz = 625.0, 127 .socclk_mhz = 1200.0, 128 .dscclk_mhz = 716.667, 129 .dram_speed_mts = 18000.0, 130 .dtbclk_mhz = 1564.0, 131 }, 132 }, 133 .num_states = 1, 134 .sr_exit_time_us = 42.97, 135 .sr_enter_plus_exit_time_us = 49.94, 136 .sr_exit_z8_time_us = 285.0, 137 .sr_enter_plus_exit_z8_time_us = 320, 138 .writeback_latency_us = 12.0, 139 .round_trip_ping_latency_dcfclk_cycles = 263, 140 .urgent_latency_pixel_data_only_us = 4.0, 141 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 142 .urgent_latency_vm_data_only_us = 4.0, 143 .fclk_change_latency_us = 25, 144 .usr_retraining_latency_us = 2, 145 .smn_latency_us = 2, 146 .mall_allocated_for_dcn_mbytes = 64, 147 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 148 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 149 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 150 .pct_ideal_sdp_bw_after_urgent = 90.0, 151 .pct_ideal_fabric_bw_after_urgent = 67.0, 152 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 153 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 154 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 155 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 156 .max_avg_sdp_bw_use_normal_percent = 80.0, 157 .max_avg_fabric_bw_use_normal_percent = 60.0, 158 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 159 .max_avg_dram_bw_use_normal_percent = 15.0, 160 .num_chans = 24, 161 .dram_channel_width_bytes = 2, 162 .fabric_datapath_to_dcn_data_return_bytes = 64, 163 .return_bus_width_bytes = 64, 164 .downspread_percent = 0.38, 165 .dcn_downspread_percent = 0.5, 166 .dram_clock_change_latency_us = 400, 167 .dispclk_dppclk_vco_speed_mhz = 4300.0, 168 .do_urgent_latency_adjustment = true, 169 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 170 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, 171 }; 172 173 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 174 { 175 /* defaults */ 176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; 178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 180 /* For min clocks use as reported by PM FW and report those as min */ 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 183 uint16_t setb_min_uclk_mhz = min_uclk_mhz; 184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; 185 186 dc_assert_fp_enabled(); 187 188 /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ 189 if (dcfclk_mhz_for_the_second_state) 190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; 191 else 192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 193 194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) 195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; 196 197 /* Set A - Normal - default values */ 198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us; 201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 205 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 206 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 207 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 208 209 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ 210 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us; 213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; 218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 219 220 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 221 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ 222 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { 223 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 224 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; 225 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us; 226 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 227 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 228 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 229 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 230 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 231 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 232 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 233 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; 234 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; 235 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; 236 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; 237 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; 238 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; 239 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; 240 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; 241 } 242 /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ 243 /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ 244 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; 245 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; 246 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; 247 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD 248 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD 249 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 250 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 251 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 252 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 253 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 254 } 255 256 /* 257 * Finds dummy_latency_index when MCLK switching using firmware based 258 * vblank stretch is enabled. This function will iterate through the 259 * table of dummy pstate latencies until the lowest value that allows 260 * dm_allow_self_refresh_and_mclk_switch to happen is found 261 */ 262 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 263 struct dc_state *context, 264 display_e2e_pipe_params_st *pipes, 265 int pipe_cnt, 266 int vlevel) 267 { 268 const int max_latency_table_entries = 4; 269 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 270 int dummy_latency_index = 0; 271 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 272 273 dc_assert_fp_enabled(); 274 275 while (dummy_latency_index < max_latency_table_entries) { 276 if (temp_clock_change_support != dm_dram_clock_change_unsupported) 277 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 278 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 279 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 281 282 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ 283 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && 284 dcn32_subvp_in_use(dc, context)) 285 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 286 287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && 288 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) 289 break; 290 291 dummy_latency_index++; 292 } 293 294 if (dummy_latency_index == max_latency_table_entries) { 295 ASSERT(dummy_latency_index != max_latency_table_entries); 296 /* If the execution gets here, it means dummy p_states are 297 * not possible. This should never happen and would mean 298 * something is severely wrong. 299 * Here we reset dummy_latency_index to 3, because it is 300 * better to have underflows than system crashes. 301 */ 302 dummy_latency_index = max_latency_table_entries - 1; 303 } 304 305 return dummy_latency_index; 306 } 307 308 /** 309 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 310 * and populate pipe_ctx with those params. 311 * @dc: [in] current dc state 312 * @context: [in] new dc state 313 * @pipes: [in] DML pipe params array 314 * @pipe_cnt: [in] DML pipe count 315 * 316 * This function must be called AFTER the phantom pipes are added to context 317 * and run through DML (so that the DLG params for the phantom pipes can be 318 * populated), and BEFORE we program the timing for the phantom pipes. 319 */ 320 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 321 struct dc_state *context, 322 display_e2e_pipe_params_st *pipes, 323 int pipe_cnt) 324 { 325 uint32_t i, pipe_idx; 326 327 dc_assert_fp_enabled(); 328 329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 330 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 331 332 if (!pipe->stream) 333 continue; 334 335 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 336 pipes[pipe_idx].pipe.dest.vstartup_start = 337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 338 pipes[pipe_idx].pipe.dest.vupdate_offset = 339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 340 pipes[pipe_idx].pipe.dest.vupdate_width = 341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 342 pipes[pipe_idx].pipe.dest.vready_offset = 343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 344 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 345 } 346 pipe_idx++; 347 } 348 } 349 350 /** 351 * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe 352 * @context: [in] New DC state to be programmed 353 * @pipe_e2e: [in] DML pipe end to end context 354 * 355 * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both 356 * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is 357 * determined by DPPClk requirements 358 * 359 * This function follows the same policy as DML: 360 * - Check for ODM combine requirements / policy first 361 * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and 362 * MPC is required 363 * 364 * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits). 365 */ 366 uint8_t dcn32_predict_pipe_split(struct dc_state *context, 367 display_e2e_pipe_params_st *pipe_e2e) 368 { 369 double pscl_throughput; 370 double pscl_throughput_chroma; 371 double dpp_clk_single_dpp, clock; 372 double clk_frequency = 0.0; 373 double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; 374 bool total_available_pipes_support = false; 375 uint32_t number_of_dpp = 0; 376 enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled; 377 double req_dispclk_per_surface = 0; 378 uint8_t num_splits = 0; 379 380 dc_assert_fp_enabled(); 381 382 dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, 383 pipe_e2e->pipe.dest.hactive, 384 pipe_e2e->dout.output_format, 385 pipe_e2e->dout.output_type, 386 pipe_e2e->pipe.dest.odm_combine_policy, 387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 389 pipe_e2e->dout.dsc_enable != 0, 390 0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */ 391 context->bw_ctx.dml.ip.max_num_dpp, 392 pipe_e2e->pipe.dest.pixel_rate_mhz, 393 context->bw_ctx.dml.soc.dcn_downspread_percent, 394 context->bw_ctx.dml.ip.dispclk_ramp_margin_percent, 395 context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz, 396 pipe_e2e->dout.dsc_slices, 397 /* Output */ 398 &total_available_pipes_support, 399 &number_of_dpp, 400 &odm_mode, 401 &req_dispclk_per_surface); 402 403 dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio, 404 pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c, 405 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio, 406 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c, 407 context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk, 408 context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk, 409 pipe_e2e->pipe.dest.pixel_rate_mhz, 410 pipe_e2e->pipe.src.source_format, 411 pipe_e2e->pipe.scale_taps.htaps, 412 pipe_e2e->pipe.scale_taps.htaps_c, 413 pipe_e2e->pipe.scale_taps.vtaps, 414 pipe_e2e->pipe.scale_taps.vtaps_c, 415 /* Output */ 416 &pscl_throughput, &pscl_throughput_chroma, 417 &dpp_clk_single_dpp); 418 419 clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100); 420 421 if (clock > 0) 422 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock); 423 424 if (odm_mode == dm_odm_combine_mode_2to1) 425 num_splits = 1; 426 else if (odm_mode == dm_odm_combine_mode_4to1) 427 num_splits = 3; 428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) 429 num_splits = 1; 430 431 return num_splits; 432 } 433 434 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 435 { 436 float memory_bw_kbytes_sec; 437 float fabric_bw_kbytes_sec; 438 float sdp_bw_kbytes_sec; 439 float limiting_bw_kbytes_sec; 440 441 memory_bw_kbytes_sec = entry->dram_speed_mts * 442 dcn3_2_soc.num_chans * 443 dcn3_2_soc.dram_channel_width_bytes * 444 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 445 446 fabric_bw_kbytes_sec = entry->fabricclk_mhz * 447 dcn3_2_soc.return_bus_width_bytes * 448 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 449 450 sdp_bw_kbytes_sec = entry->dcfclk_mhz * 451 dcn3_2_soc.return_bus_width_bytes * 452 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 453 454 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 455 456 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 457 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 458 459 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 460 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 461 462 return limiting_bw_kbytes_sec; 463 } 464 465 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 466 { 467 if (entry->dcfclk_mhz > 0) { 468 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 469 470 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 471 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * 472 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 473 } else if (entry->fabricclk_mhz > 0) { 474 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 475 476 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 477 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * 478 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 479 } else if (entry->dram_speed_mts > 0) { 480 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * 481 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 482 483 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 484 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 485 } 486 } 487 488 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 489 unsigned int *num_entries, 490 struct _vcs_dpi_voltage_scaling_st *entry) 491 { 492 int i = 0; 493 int index = 0; 494 495 dc_assert_fp_enabled(); 496 497 if (*num_entries == 0) { 498 table[0] = *entry; 499 (*num_entries)++; 500 } else { 501 while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) { 502 index++; 503 if (index >= *num_entries) 504 break; 505 } 506 507 for (i = *num_entries; i > index; i--) 508 table[i] = table[i - 1]; 509 510 table[index] = *entry; 511 (*num_entries)++; 512 } 513 } 514 515 /** 516 * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream 517 * @dc: current dc state 518 * @context: new dc state 519 * @ref_pipe: Main pipe for the phantom stream 520 * @phantom_stream: target phantom stream state 521 * @pipes: DML pipe params 522 * @pipe_cnt: number of DML pipes 523 * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) 524 * 525 * Set timing params of the phantom stream based on calculated output from DML. 526 * This function first gets the DML pipe index using the DC pipe index, then 527 * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of 528 * lines required for SubVP MCLK switching and assigns to the phantom stream 529 * accordingly. 530 * 531 * - The number of SubVP lines calculated in DML does not take into account 532 * FW processing delays and required pstate allow width, so we must include 533 * that separately. 534 * 535 * - Set phantom backporch = vstartup of main pipe 536 */ 537 void dcn32_set_phantom_stream_timing(struct dc *dc, 538 struct dc_state *context, 539 struct pipe_ctx *ref_pipe, 540 struct dc_stream_state *phantom_stream, 541 display_e2e_pipe_params_st *pipes, 542 unsigned int pipe_cnt, 543 unsigned int dc_pipe_idx) 544 { 545 unsigned int i, pipe_idx; 546 struct pipe_ctx *pipe; 547 uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; 548 unsigned int num_dpp; 549 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; 550 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 551 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; 552 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 553 struct dc_stream_state *main_stream = ref_pipe->stream; 554 555 dc_assert_fp_enabled(); 556 557 // Find DML pipe index (pipe_idx) using dc_pipe_idx 558 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 559 pipe = &context->res_ctx.pipe_ctx[i]; 560 561 if (!pipe->stream) 562 continue; 563 564 if (i == dc_pipe_idx) 565 break; 566 567 pipe_idx++; 568 } 569 570 // Calculate lines required for pstate allow width and FW processing delays 571 pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + 572 dc->caps.subvp_pstate_allow_width_us) / 1000000) * 573 (ref_pipe->stream->timing.pix_clk_100hz * 100) / 574 (double)ref_pipe->stream->timing.h_total; 575 576 // Update clks_cfg for calling into recalculate 577 pipes[0].clks_cfg.voltage = vlevel; 578 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 579 pipes[0].clks_cfg.socclk_mhz = socclk; 580 581 // DML calculation for MALL region doesn't take into account FW delay 582 // and required pstate allow width for multi-display cases 583 /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned 584 * to 2 swaths (i.e. 16 lines) 585 */ 586 phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + 587 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; 588 589 // W/A for DCC corruption with certain high resolution timings. 590 // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. 591 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; 592 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; 593 594 /* dc->debug.subvp_extra_lines 0 by default*/ 595 phantom_vactive += dc->debug.subvp_extra_lines; 596 597 // For backporch of phantom pipe, use vstartup of the main pipe 598 phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 599 600 phantom_stream->dst.y = 0; 601 phantom_stream->dst.height = phantom_vactive; 602 /* When scaling, DML provides the end to end required number of lines for MALL. 603 * dst.height is always correct for this case, but src.height is not which causes a 604 * delta between main and phantom pipe scaling outputs. Need to adjust src.height on 605 * phantom for this case. 606 */ 607 phantom_stream->src.y = 0; 608 phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height; 609 610 phantom_stream->timing.v_addressable = phantom_vactive; 611 phantom_stream->timing.v_front_porch = 1; 612 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + 613 phantom_stream->timing.v_front_porch + 614 phantom_stream->timing.v_sync_width + 615 phantom_bp; 616 phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing 617 } 618 619 /** 620 * dcn32_get_num_free_pipes - Calculate number of free pipes 621 * @dc: current dc state 622 * @context: new dc state 623 * 624 * This function assumes that a "used" pipe is a pipe that has 625 * both a stream and a plane assigned to it. 626 * 627 * Return: Number of free pipes available in the context 628 */ 629 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) 630 { 631 unsigned int i; 632 unsigned int free_pipes = 0; 633 unsigned int num_pipes = 0; 634 635 for (i = 0; i < dc->res_pool->pipe_count; i++) { 636 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 637 638 if (pipe->stream && !pipe->top_pipe) { 639 while (pipe) { 640 num_pipes++; 641 pipe = pipe->bottom_pipe; 642 } 643 } 644 } 645 646 free_pipes = dc->res_pool->pipe_count - num_pipes; 647 return free_pipes; 648 } 649 650 /** 651 * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP. 652 * @dc: current dc state 653 * @context: new dc state 654 * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned 655 * 656 * We enter this function if we are Sub-VP capable (i.e. enough pipes available) 657 * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if 658 * we are forcing SubVP P-State switching on the current config. 659 * 660 * The number of pipes used for the chosen surface must be less than or equal to the 661 * number of free pipes available. 662 * 663 * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK). 664 * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own 665 * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't 666 * support MCLK switching naturally [i.e. ACTIVE or VBLANK]). 667 * 668 * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. 669 */ 670 static bool dcn32_assign_subvp_pipe(struct dc *dc, 671 struct dc_state *context, 672 unsigned int *index) 673 { 674 unsigned int i, pipe_idx; 675 unsigned int max_frame_time = 0; 676 bool valid_assignment_found = false; 677 unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); 678 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 679 680 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 681 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 682 unsigned int num_pipes = 0; 683 unsigned int refresh_rate = 0; 684 685 if (!pipe->stream) 686 continue; 687 688 // Round up 689 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 690 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 691 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 692 /* SubVP pipe candidate requirements: 693 * - Refresh rate < 120hz 694 * - Not able to switch in vactive naturally (switching in active means the 695 * DET provides enough buffer to hide the P-State switch latency -- trying 696 * to combine this with SubVP can cause issues with the scheduling). 697 * - Not TMZ surface 698 */ 699 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && 700 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && 701 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && 702 pipe->stream->mall_stream_config.type == SUBVP_NONE && 703 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) && 704 !pipe->plane_state->address.tmz_surface && 705 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 || 706 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && 707 dcn32_allow_subvp_with_active_margin(pipe)))) { 708 while (pipe) { 709 num_pipes++; 710 pipe = pipe->bottom_pipe; 711 } 712 713 pipe = &context->res_ctx.pipe_ctx[i]; 714 if (num_pipes <= free_pipes) { 715 struct dc_stream_state *stream = pipe->stream; 716 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / 717 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; 718 if (frame_us > max_frame_time) { 719 *index = i; 720 max_frame_time = frame_us; 721 valid_assignment_found = true; 722 } 723 } 724 } 725 pipe_idx++; 726 } 727 return valid_assignment_found; 728 } 729 730 /** 731 * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP. 732 * @dc: current dc state 733 * @context: new dc state 734 * 735 * This function returns true if there are enough free pipes 736 * to create the required phantom pipes for any given stream 737 * (that does not already have phantom pipe assigned). 738 * 739 * e.g. For a 2 stream config where the first stream uses one 740 * pipe and the second stream uses 2 pipes (i.e. pipe split), 741 * this function will return true because there is 1 remaining 742 * pipe which can be used as the phantom pipe for the non pipe 743 * split pipe. 744 * 745 * Return: 746 * True if there are enough free pipes to assign phantom pipes to at least one 747 * stream that does not already have phantom pipes assigned. Otherwise false. 748 */ 749 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) 750 { 751 unsigned int i, split_cnt, free_pipes; 752 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 753 bool subvp_possible = false; 754 755 for (i = 0; i < dc->res_pool->pipe_count; i++) { 756 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 757 758 // Find the minimum pipe split count for non SubVP pipes 759 if (pipe->stream && !pipe->top_pipe && 760 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 761 split_cnt = 0; 762 while (pipe) { 763 split_cnt++; 764 pipe = pipe->bottom_pipe; 765 } 766 767 if (split_cnt < min_pipe_split) 768 min_pipe_split = split_cnt; 769 } 770 } 771 772 free_pipes = dcn32_get_num_free_pipes(dc, context); 773 774 // SubVP only possible if at least one pipe is being used (i.e. free_pipes 775 // should not equal to the pipe_count) 776 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) 777 subvp_possible = true; 778 779 return subvp_possible; 780 } 781 782 /** 783 * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable 784 * @dc: current dc state 785 * @context: new dc state 786 * 787 * High level algorithm: 788 * 1. Find longest microschedule length (in us) between the two SubVP pipes 789 * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both 790 * pipes still allows for the maximum microschedule to fit in the active 791 * region for both pipes. 792 * 793 * Return: True if the SubVP + SubVP config is schedulable, false otherwise 794 */ 795 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) 796 { 797 struct pipe_ctx *subvp_pipes[2]; 798 struct dc_stream_state *phantom = NULL; 799 uint32_t microschedule_lines = 0; 800 uint32_t index = 0; 801 uint32_t i; 802 uint32_t max_microschedule_us = 0; 803 int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; 804 805 for (i = 0; i < dc->res_pool->pipe_count; i++) { 806 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 807 uint32_t time_us = 0; 808 809 /* Loop to calculate the maximum microschedule time between the two SubVP pipes, 810 * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. 811 */ 812 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 813 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 814 phantom = pipe->stream->mall_stream_config.paired_stream; 815 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + 816 phantom->timing.v_addressable; 817 818 // Round up when calculating microschedule time (+ 1 at the end) 819 time_us = (microschedule_lines * phantom->timing.h_total) / 820 (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + 821 dc->caps.subvp_prefetch_end_to_mall_start_us + 822 dc->caps.subvp_fw_processing_delay_us + 1; 823 if (time_us > max_microschedule_us) 824 max_microschedule_us = time_us; 825 826 subvp_pipes[index] = pipe; 827 index++; 828 829 // Maximum 2 SubVP pipes 830 if (index == 2) 831 break; 832 } 833 } 834 vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / 835 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 836 vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / 837 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 838 vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * 839 subvp_pipes[0]->stream->timing.h_total) / 840 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 841 vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * 842 subvp_pipes[1]->stream->timing.h_total) / 843 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 844 845 if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && 846 (vactive2_us - vblank1_us) / 2 > max_microschedule_us) 847 return true; 848 849 return false; 850 } 851 852 /** 853 * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable 854 * @dc: current dc state 855 * @context: new dc state 856 * 857 * High level algorithm: 858 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 859 * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching 860 * (the margin is equal to the MALL region + DRR margin (500us)) 861 * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) 862 * then report the configuration as supported 863 * 864 * Return: True if the SubVP + DRR config is schedulable, false otherwise 865 */ 866 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) 867 { 868 bool schedulable = false; 869 uint32_t i; 870 struct pipe_ctx *pipe = NULL; 871 struct pipe_ctx *drr_pipe = NULL; 872 struct dc_crtc_timing *main_timing = NULL; 873 struct dc_crtc_timing *phantom_timing = NULL; 874 struct dc_crtc_timing *drr_timing = NULL; 875 int16_t prefetch_us = 0; 876 int16_t mall_region_us = 0; 877 int16_t drr_frame_us = 0; // nominal frame time 878 int16_t subvp_active_us = 0; 879 int16_t stretched_drr_us = 0; 880 int16_t drr_stretched_vblank_us = 0; 881 int16_t max_vblank_mallregion = 0; 882 883 // Find SubVP pipe 884 for (i = 0; i < dc->res_pool->pipe_count; i++) { 885 pipe = &context->res_ctx.pipe_ctx[i]; 886 887 // We check for master pipe, but it shouldn't matter since we only need 888 // the pipe for timing info (stream should be same for any pipe splits) 889 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 890 continue; 891 892 // Find the SubVP pipe 893 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 894 break; 895 } 896 897 // Find the DRR pipe 898 for (i = 0; i < dc->res_pool->pipe_count; i++) { 899 drr_pipe = &context->res_ctx.pipe_ctx[i]; 900 901 // We check for master pipe only 902 if (!drr_pipe->stream || !drr_pipe->plane_state || drr_pipe->top_pipe || drr_pipe->prev_odm_pipe) 903 continue; 904 905 if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param && 906 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable)) 907 break; 908 } 909 910 main_timing = &pipe->stream->timing; 911 phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; 912 drr_timing = &drr_pipe->stream->timing; 913 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 914 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 915 dc->caps.subvp_prefetch_end_to_mall_start_us; 916 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 917 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 918 drr_frame_us = drr_timing->v_total * drr_timing->h_total / 919 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 920 // P-State allow width and FW delays already included phantom_timing->v_addressable 921 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 922 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 923 stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 924 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / 925 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); 926 max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; 927 928 /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the 929 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis 930 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 931 * and the max of (VBLANK blanking time, MALL region)). 932 */ 933 if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && 934 subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) 935 schedulable = true; 936 937 return schedulable; 938 } 939 940 941 /** 942 * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable 943 * @dc: current dc state 944 * @context: new dc state 945 * 946 * High level algorithm: 947 * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe 948 * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) 949 * then report the configuration as supported 950 * 3. If the VBLANK display is DRR, then take the DRR static schedulability path 951 * 952 * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise 953 */ 954 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) 955 { 956 struct pipe_ctx *pipe = NULL; 957 struct pipe_ctx *subvp_pipe = NULL; 958 bool found = false; 959 bool schedulable = false; 960 uint32_t i = 0; 961 uint8_t vblank_index = 0; 962 uint16_t prefetch_us = 0; 963 uint16_t mall_region_us = 0; 964 uint16_t vblank_frame_us = 0; 965 uint16_t subvp_active_us = 0; 966 uint16_t vblank_blank_us = 0; 967 uint16_t max_vblank_mallregion = 0; 968 struct dc_crtc_timing *main_timing = NULL; 969 struct dc_crtc_timing *phantom_timing = NULL; 970 struct dc_crtc_timing *vblank_timing = NULL; 971 972 /* For SubVP + VBLANK/DRR cases, we assume there can only be 973 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK 974 * is supported, it is either a single VBLANK case or two VBLANK 975 * displays which are synchronized (in which case they have identical 976 * timings). 977 */ 978 for (i = 0; i < dc->res_pool->pipe_count; i++) { 979 pipe = &context->res_ctx.pipe_ctx[i]; 980 981 // We check for master pipe, but it shouldn't matter since we only need 982 // the pipe for timing info (stream should be same for any pipe splits) 983 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 984 continue; 985 986 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 987 // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). 988 vblank_index = i; 989 found = true; 990 } 991 992 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 993 subvp_pipe = pipe; 994 } 995 if (found) { 996 main_timing = &subvp_pipe->stream->timing; 997 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 998 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; 999 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe 1000 // Also include the prefetch end to mallstart delay time 1001 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 1002 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 1003 dc->caps.subvp_prefetch_end_to_mall_start_us; 1004 // P-State allow width and FW delays already included phantom_timing->v_addressable 1005 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 1006 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 1007 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / 1008 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1009 vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / 1010 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1011 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 1012 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 1013 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; 1014 1015 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 1016 // and the max of (VBLANK blanking time, MALL region) 1017 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) 1018 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) 1019 schedulable = true; 1020 } 1021 return schedulable; 1022 } 1023 1024 /** 1025 * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible 1026 * 1027 * @dc: Current DC state 1028 * @context: New DC state to be programmed 1029 * 1030 * SubVP + SubVP is admissible under the following conditions: 1031 * - All SubVP pipes are < 120Hz OR 1032 * - All SubVP pipes are >= 120hz 1033 * 1034 * Return: True if admissible, false otherwise 1035 */ 1036 static bool subvp_subvp_admissable(struct dc *dc, 1037 struct dc_state *context) 1038 { 1039 bool result = false; 1040 uint32_t i; 1041 uint8_t subvp_count = 0; 1042 uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0; 1043 uint64_t refresh_rate = 0; 1044 1045 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1046 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1047 1048 if (!pipe->stream) 1049 continue; 1050 1051 if (pipe->plane_state && !pipe->top_pipe && 1052 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 1053 refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + 1054 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); 1055 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); 1056 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); 1057 1058 if ((uint32_t)refresh_rate < min_refresh) 1059 min_refresh = (uint32_t)refresh_rate; 1060 if ((uint32_t)refresh_rate > max_refresh) 1061 max_refresh = (uint32_t)refresh_rate; 1062 subvp_count++; 1063 } 1064 } 1065 1066 if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) || 1067 (min_refresh >= subvp_high_refresh_list.min_refresh && 1068 max_refresh <= subvp_high_refresh_list.max_refresh))) 1069 result = true; 1070 1071 return result; 1072 } 1073 1074 /** 1075 * subvp_validate_static_schedulability - Check which SubVP case is calculated 1076 * and handle static analysis based on the case. 1077 * @dc: current dc state 1078 * @context: new dc state 1079 * @vlevel: Voltage level calculated by DML 1080 * 1081 * Three cases: 1082 * 1. SubVP + SubVP 1083 * 2. SubVP + VBLANK (DRR checked internally) 1084 * 3. SubVP + VACTIVE (currently unsupported) 1085 * 1086 * Return: True if statically schedulable, false otherwise 1087 */ 1088 static bool subvp_validate_static_schedulability(struct dc *dc, 1089 struct dc_state *context, 1090 int vlevel) 1091 { 1092 bool schedulable = false; 1093 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1094 uint32_t i, pipe_idx; 1095 uint8_t subvp_count = 0; 1096 uint8_t vactive_count = 0; 1097 uint8_t non_subvp_pipes = 0; 1098 1099 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1100 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1101 1102 if (!pipe->stream) 1103 continue; 1104 1105 if (pipe->plane_state && !pipe->top_pipe) { 1106 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 1107 subvp_count++; 1108 if (pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1109 non_subvp_pipes++; 1110 } 1111 } 1112 1113 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE 1114 // switching (SubVP + VACTIVE unsupported). In situations where we force 1115 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count. 1116 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && 1117 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1118 vactive_count++; 1119 } 1120 pipe_idx++; 1121 } 1122 1123 if (subvp_count == 2) { 1124 // Static schedulability check for SubVP + SubVP case 1125 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context); 1126 } else if (subvp_count == 1 && non_subvp_pipes == 0) { 1127 // Single SubVP configs will be supported by default as long as it's suppported by DML 1128 schedulable = true; 1129 } else if (subvp_count == 1 && non_subvp_pipes == 1) { 1130 if (dcn32_subvp_drr_admissable(dc, context)) 1131 schedulable = subvp_drr_schedulable(dc, context); 1132 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel)) 1133 schedulable = subvp_vblank_schedulable(dc, context); 1134 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp && 1135 vactive_count > 0) { 1136 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default. 1137 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count. 1138 // SubVP + VACTIVE currently unsupported 1139 schedulable = false; 1140 } 1141 return schedulable; 1142 } 1143 1144 static void dcn32_full_validate_bw_helper(struct dc *dc, 1145 struct dc_state *context, 1146 display_e2e_pipe_params_st *pipes, 1147 int *vlevel, 1148 int *split, 1149 bool *merge, 1150 int *pipe_cnt) 1151 { 1152 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1153 unsigned int dc_pipe_idx = 0; 1154 int i = 0; 1155 bool found_supported_config = false; 1156 1157 dc_assert_fp_enabled(); 1158 1159 /* 1160 * DML favors voltage over p-state, but we're more interested in 1161 * supporting p-state over voltage. We can't support p-state in 1162 * prefetch mode > 0 so try capping the prefetch mode to start. 1163 * Override present for testing. 1164 */ 1165 if (dc->debug.dml_disallow_alternate_prefetch_modes) 1166 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1167 dm_prefetch_support_uclk_fclk_and_stutter; 1168 else 1169 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1170 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1171 1172 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1173 /* This may adjust vlevel and maxMpcComb */ 1174 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1175 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1176 vba->VoltageLevel = *vlevel; 1177 } 1178 1179 /* Conditions for setting up phantom pipes for SubVP: 1180 * 1. Not force disable SubVP 1181 * 2. Full update (i.e. !fast_validate) 1182 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) 1183 * 4. Display configuration passes validation 1184 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) 1185 */ 1186 if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) && 1187 !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && 1188 (*vlevel == context->bw_ctx.dml.soc.num_states || 1189 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || 1190 dc->debug.force_subvp_mclk_switch)) { 1191 1192 dcn32_merge_pipes_for_subvp(dc, context); 1193 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1194 1195 /* to re-initialize viewport after the pipe merge */ 1196 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1197 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1198 1199 if (!pipe_ctx->plane_state || !pipe_ctx->stream) 1200 continue; 1201 1202 resource_build_scaling_params(pipe_ctx); 1203 } 1204 1205 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && 1206 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { 1207 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. 1208 * Adding phantom pipes won't change the validation result, so change the DML input param 1209 * for P-State support before adding phantom pipes and recalculating the DML result. 1210 * However, this case is only applicable for SubVP + DRR cases because the prefetch mode 1211 * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched 1212 * enough to support MCLK switching. 1213 */ 1214 if (*vlevel == context->bw_ctx.dml.soc.num_states && 1215 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final == 1216 dm_prefetch_support_uclk_fclk_and_stutter) { 1217 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1218 dm_prefetch_support_fclk_and_stutter; 1219 /* There are params (such as FabricClock) that need to be recalculated 1220 * after validation fails (otherwise it will be 0). Calculation for 1221 * phantom vactive requires call into DML, so we must ensure all the 1222 * vba params are valid otherwise we'll get incorrect phantom vactive. 1223 */ 1224 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1225 } 1226 1227 dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); 1228 1229 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1230 // Populate dppclk to trigger a recalculate in dml_get_voltage_level 1231 // so the phantom pipe DLG params can be assigned correctly. 1232 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); 1233 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1234 1235 /* Check that vlevel requested supports pstate or not 1236 * if not, select the lowest vlevel that supports it 1237 */ 1238 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1239 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { 1240 *vlevel = i; 1241 break; 1242 } 1243 } 1244 1245 if (*vlevel < context->bw_ctx.dml.soc.num_states 1246 && subvp_validate_static_schedulability(dc, context, *vlevel)) 1247 found_supported_config = true; 1248 if (found_supported_config) { 1249 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode 1250 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) { 1251 /* find lowest vlevel that supports the config */ 1252 for (i = *vlevel; i >= 0; i--) { 1253 if (vba->ModeSupport[i][vba->maxMpcComb]) { 1254 *vlevel = i; 1255 } else { 1256 break; 1257 } 1258 } 1259 } 1260 } 1261 } 1262 1263 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) 1264 // remove phantom pipes and repopulate dml pipes 1265 if (!found_supported_config) { 1266 dc->res_pool->funcs->remove_phantom_pipes(dc, context, false); 1267 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; 1268 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1269 1270 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1271 /* This may adjust vlevel and maxMpcComb */ 1272 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1273 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1274 vba->VoltageLevel = *vlevel; 1275 } 1276 } else { 1277 // Most populate phantom DLG params before programming hardware / timing for phantom pipe 1278 dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); 1279 1280 /* Call validate_apply_pipe_split flags after calling DML getters for 1281 * phantom dlg params, or some of the VBA params indicating pipe split 1282 * can be overwritten by the getters. 1283 * 1284 * When setting up SubVP config, all pipes are merged before attempting to 1285 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main 1286 * and phantom pipes will be split in the regular pipe splitting sequence. 1287 */ 1288 memset(split, 0, MAX_PIPES * sizeof(int)); 1289 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1290 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1291 vba->VoltageLevel = *vlevel; 1292 // Note: We can't apply the phantom pipes to hardware at this time. We have to wait 1293 // until driver has acquired the DMCUB lock to do it safely. 1294 } 1295 } 1296 } 1297 1298 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 1299 { 1300 int i; 1301 1302 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1303 if (!context->res_ctx.pipe_ctx[i].stream) 1304 continue; 1305 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 1306 return true; 1307 } 1308 return false; 1309 } 1310 1311 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start) 1312 { 1313 struct dc_crtc_timing patched_crtc_timing; 1314 uint32_t asic_blank_end = 0; 1315 uint32_t asic_blank_start = 0; 1316 uint32_t newVstartup = 0; 1317 1318 patched_crtc_timing = *dc_crtc_timing; 1319 1320 if (patched_crtc_timing.flags.INTERLACE == 1) { 1321 if (patched_crtc_timing.v_front_porch < 2) 1322 patched_crtc_timing.v_front_porch = 2; 1323 } else { 1324 if (patched_crtc_timing.v_front_porch < 1) 1325 patched_crtc_timing.v_front_porch = 1; 1326 } 1327 1328 /* blank_start = frame end - front porch */ 1329 asic_blank_start = patched_crtc_timing.v_total - 1330 patched_crtc_timing.v_front_porch; 1331 1332 /* blank_end = blank_start - active */ 1333 asic_blank_end = asic_blank_start - 1334 patched_crtc_timing.v_border_bottom - 1335 patched_crtc_timing.v_addressable - 1336 patched_crtc_timing.v_border_top; 1337 1338 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); 1339 1340 *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); 1341 } 1342 1343 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 1344 display_e2e_pipe_params_st *pipes, 1345 int pipe_cnt, int vlevel) 1346 { 1347 int i, pipe_idx, active_hubp_count = 0; 1348 bool usr_retraining_support = false; 1349 bool unbounded_req_enabled = false; 1350 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1351 1352 dc_assert_fp_enabled(); 1353 1354 /* Writeback MCIF_WB arbitration parameters */ 1355 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1356 1357 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 1358 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 1359 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 1360 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 1361 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 1362 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 1363 context->bw_ctx.bw.dcn.clk.p_state_change_support = 1364 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 1365 != dm_dram_clock_change_unsupported; 1366 1367 /* Pstate change might not be supported by hardware, but it might be 1368 * possible with firmware driven vertical blank stretching. 1369 */ 1370 context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; 1371 1372 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1373 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 1374 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; 1375 if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) 1376 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; 1377 else 1378 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1379 1380 usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1381 ASSERT(usr_retraining_support); 1382 1383 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 1384 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 1385 1386 unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); 1387 1388 if (unbounded_req_enabled && pipe_cnt > 1) { 1389 // Unbounded requesting should not ever be used when more than 1 pipe is enabled. 1390 ASSERT(false); 1391 unbounded_req_enabled = false; 1392 } 1393 1394 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 1395 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 1396 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 1397 1398 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1399 if (!context->res_ctx.pipe_ctx[i].stream) 1400 continue; 1401 if (context->res_ctx.pipe_ctx[i].plane_state) 1402 active_hubp_count++; 1403 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, 1404 pipe_idx); 1405 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1406 pipe_idx); 1407 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, 1408 pipe_idx); 1409 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1410 pipe_idx); 1411 1412 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1413 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests 1414 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; 1415 context->res_ctx.pipe_ctx[i].unbounded_req = false; 1416 } else { 1417 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, 1418 pipe_idx); 1419 context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; 1420 } 1421 1422 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1423 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1424 if (context->res_ctx.pipe_ctx[i].plane_state) 1425 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1426 else 1427 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; 1428 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 1429 1430 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1431 1432 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) 1433 context->res_ctx.pipe_ctx[i].has_vactive_margin = true; 1434 else 1435 context->res_ctx.pipe_ctx[i].has_vactive_margin = false; 1436 1437 /* MALL Allocation Sizes */ 1438 /* count from active, top pipes per plane only */ 1439 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state && 1440 (context->res_ctx.pipe_ctx[i].top_pipe == NULL || 1441 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) && 1442 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1443 /* SS: all active surfaces stored in MALL */ 1444 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { 1445 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1446 1447 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) { 1448 /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */ 1449 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1450 } 1451 } else { 1452 /* SUBVP: phantom surfaces only stored in MALL */ 1453 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1454 } 1455 } 1456 1457 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) 1458 dcn20_adjust_freesync_v_startup( 1459 &context->res_ctx.pipe_ctx[i].stream->timing, 1460 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); 1461 1462 pipe_idx++; 1463 } 1464 /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ 1465 if (!active_hubp_count) { 1466 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; 1467 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1468 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; 1469 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; 1470 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; 1471 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; 1472 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 1473 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1474 } 1475 /*save a original dppclock copy*/ 1476 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 1477 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 1478 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz 1479 * 1000; 1480 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz 1481 * 1000; 1482 1483 context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); 1484 1485 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes; 1486 1487 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1488 if (context->res_ctx.pipe_ctx[i].stream) 1489 context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb; 1490 } 1491 1492 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1493 1494 if (!context->res_ctx.pipe_ctx[i].stream) 1495 continue; 1496 1497 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, 1498 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, 1499 pipe_cnt, pipe_idx); 1500 1501 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, 1502 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1503 pipe_idx++; 1504 } 1505 } 1506 1507 static struct pipe_ctx *dcn32_find_split_pipe( 1508 struct dc *dc, 1509 struct dc_state *context, 1510 int old_index) 1511 { 1512 struct pipe_ctx *pipe = NULL; 1513 int i; 1514 1515 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { 1516 pipe = &context->res_ctx.pipe_ctx[old_index]; 1517 pipe->pipe_idx = old_index; 1518 } 1519 1520 if (!pipe) 1521 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1522 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL 1523 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1524 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1525 pipe = &context->res_ctx.pipe_ctx[i]; 1526 pipe->pipe_idx = i; 1527 break; 1528 } 1529 } 1530 } 1531 1532 /* 1533 * May need to fix pipes getting tossed from 1 opp to another on flip 1534 * Add for debugging transient underflow during topology updates: 1535 * ASSERT(pipe); 1536 */ 1537 if (!pipe) 1538 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1539 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1540 pipe = &context->res_ctx.pipe_ctx[i]; 1541 pipe->pipe_idx = i; 1542 break; 1543 } 1544 } 1545 1546 return pipe; 1547 } 1548 1549 static bool dcn32_split_stream_for_mpc_or_odm( 1550 const struct dc *dc, 1551 struct resource_context *res_ctx, 1552 struct pipe_ctx *pri_pipe, 1553 struct pipe_ctx *sec_pipe, 1554 bool odm) 1555 { 1556 int pipe_idx = sec_pipe->pipe_idx; 1557 const struct resource_pool *pool = dc->res_pool; 1558 1559 DC_LOGGER_INIT(dc->ctx->logger); 1560 1561 if (odm && pri_pipe->plane_state) { 1562 /* ODM + window MPO, where MPO window is on left half only */ 1563 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= 1564 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1565 1566 DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n", 1567 __func__, 1568 pri_pipe->pipe_idx); 1569 return true; 1570 } 1571 1572 /* ODM + window MPO, where MPO window is on right half only */ 1573 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1574 1575 DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n", 1576 __func__, 1577 pri_pipe->pipe_idx); 1578 return true; 1579 } 1580 } 1581 1582 *sec_pipe = *pri_pipe; 1583 1584 sec_pipe->pipe_idx = pipe_idx; 1585 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1586 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1587 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1588 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1589 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1590 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1591 sec_pipe->stream_res.dsc = NULL; 1592 if (odm) { 1593 if (pri_pipe->next_odm_pipe) { 1594 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1595 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1596 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1597 } 1598 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { 1599 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; 1600 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; 1601 } 1602 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { 1603 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; 1604 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; 1605 } 1606 pri_pipe->next_odm_pipe = sec_pipe; 1607 sec_pipe->prev_odm_pipe = pri_pipe; 1608 ASSERT(sec_pipe->top_pipe == NULL); 1609 1610 if (!sec_pipe->top_pipe) 1611 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1612 else 1613 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 1614 if (sec_pipe->stream->timing.flags.DSC == 1) { 1615 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1616 ASSERT(sec_pipe->stream_res.dsc); 1617 if (sec_pipe->stream_res.dsc == NULL) 1618 return false; 1619 } 1620 } else { 1621 if (pri_pipe->bottom_pipe) { 1622 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1623 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1624 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1625 } 1626 pri_pipe->bottom_pipe = sec_pipe; 1627 sec_pipe->top_pipe = pri_pipe; 1628 1629 ASSERT(pri_pipe->plane_state); 1630 } 1631 1632 return true; 1633 } 1634 1635 bool dcn32_internal_validate_bw(struct dc *dc, 1636 struct dc_state *context, 1637 display_e2e_pipe_params_st *pipes, 1638 int *pipe_cnt_out, 1639 int *vlevel_out, 1640 bool fast_validate) 1641 { 1642 bool out = false; 1643 bool repopulate_pipes = false; 1644 int split[MAX_PIPES] = { 0 }; 1645 bool merge[MAX_PIPES] = { false }; 1646 bool newly_split[MAX_PIPES] = { false }; 1647 int pipe_cnt, i, pipe_idx; 1648 int vlevel = context->bw_ctx.dml.soc.num_states; 1649 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1650 1651 dc_assert_fp_enabled(); 1652 1653 ASSERT(pipes); 1654 if (!pipes) 1655 return false; 1656 1657 // For each full update, remove all existing phantom pipes first 1658 dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate); 1659 1660 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1661 1662 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1663 1664 if (!pipe_cnt) { 1665 out = true; 1666 goto validate_out; 1667 } 1668 1669 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1670 context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context); 1671 1672 if (!fast_validate) 1673 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); 1674 1675 if (fast_validate || 1676 (dc->debug.dml_disallow_alternate_prefetch_modes && 1677 (vlevel == context->bw_ctx.dml.soc.num_states || 1678 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { 1679 /* 1680 * If dml_disallow_alternate_prefetch_modes is false, then we have already 1681 * tried alternate prefetch modes during full validation. 1682 * 1683 * If mode is unsupported or there is no p-state support, then 1684 * fall back to favouring voltage. 1685 * 1686 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try 1687 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2) 1688 */ 1689 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1690 dm_prefetch_support_none; 1691 1692 context->bw_ctx.dml.validate_max_state = fast_validate; 1693 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1694 1695 context->bw_ctx.dml.validate_max_state = false; 1696 1697 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1698 memset(split, 0, sizeof(split)); 1699 memset(merge, 0, sizeof(merge)); 1700 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1701 // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML 1702 vba->VoltageLevel = vlevel; 1703 } 1704 } 1705 1706 dml_log_mode_support_params(&context->bw_ctx.dml); 1707 1708 if (vlevel == context->bw_ctx.dml.soc.num_states) 1709 goto validate_fail; 1710 1711 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1712 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1713 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1714 1715 if (!pipe->stream) 1716 continue; 1717 1718 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1719 && !dc->config.enable_windowed_mpo_odm 1720 && pipe->plane_state && mpo_pipe 1721 && memcmp(&mpo_pipe->plane_state->clip_rect, 1722 &pipe->stream->src, 1723 sizeof(struct rect)) != 0) { 1724 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1725 goto validate_fail; 1726 } 1727 pipe_idx++; 1728 } 1729 1730 /* merge pipes if necessary */ 1731 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1732 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1733 1734 /*skip pipes that don't need merging*/ 1735 if (!merge[i]) 1736 continue; 1737 1738 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 1739 if (pipe->prev_odm_pipe) { 1740 /*split off odm pipe*/ 1741 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 1742 if (pipe->next_odm_pipe) 1743 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 1744 1745 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/ 1746 if (pipe->bottom_pipe) { 1747 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) { 1748 /*MPC split rules will handle this case*/ 1749 pipe->bottom_pipe->top_pipe = NULL; 1750 } else { 1751 /* when merging an ODM pipes, the bottom MPC pipe must now point to 1752 * the previous ODM pipe and its associated stream assets 1753 */ 1754 if (pipe->prev_odm_pipe->bottom_pipe) { 1755 /* 3 plane MPO*/ 1756 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe; 1757 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; 1758 } else { 1759 /* 2 plane MPO*/ 1760 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe; 1761 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; 1762 } 1763 1764 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource)); 1765 } 1766 } 1767 1768 if (pipe->top_pipe) { 1769 pipe->top_pipe->bottom_pipe = NULL; 1770 } 1771 1772 pipe->bottom_pipe = NULL; 1773 pipe->next_odm_pipe = NULL; 1774 pipe->plane_state = NULL; 1775 pipe->stream = NULL; 1776 pipe->top_pipe = NULL; 1777 pipe->prev_odm_pipe = NULL; 1778 if (pipe->stream_res.dsc) 1779 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 1780 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1781 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1782 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1783 repopulate_pipes = true; 1784 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 1785 struct pipe_ctx *top_pipe = pipe->top_pipe; 1786 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 1787 1788 top_pipe->bottom_pipe = bottom_pipe; 1789 if (bottom_pipe) 1790 bottom_pipe->top_pipe = top_pipe; 1791 1792 pipe->top_pipe = NULL; 1793 pipe->bottom_pipe = NULL; 1794 pipe->plane_state = NULL; 1795 pipe->stream = NULL; 1796 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1797 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1798 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1799 repopulate_pipes = true; 1800 } else 1801 ASSERT(0); /* Should never try to merge master pipe */ 1802 1803 } 1804 1805 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1806 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1807 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1808 struct pipe_ctx *hsplit_pipe = NULL; 1809 bool odm; 1810 int old_index = -1; 1811 1812 if (!pipe->stream || newly_split[i]) 1813 continue; 1814 1815 pipe_idx++; 1816 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 1817 1818 if (!pipe->plane_state && !odm) 1819 continue; 1820 1821 if (split[i]) { 1822 if (odm) { 1823 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) 1824 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1825 else if (old_pipe->next_odm_pipe) 1826 old_index = old_pipe->next_odm_pipe->pipe_idx; 1827 } else { 1828 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1829 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1830 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1831 else if (old_pipe->bottom_pipe && 1832 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1833 old_index = old_pipe->bottom_pipe->pipe_idx; 1834 } 1835 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); 1836 ASSERT(hsplit_pipe); 1837 if (!hsplit_pipe) 1838 goto validate_fail; 1839 1840 if (!dcn32_split_stream_for_mpc_or_odm( 1841 dc, &context->res_ctx, 1842 pipe, hsplit_pipe, odm)) 1843 goto validate_fail; 1844 1845 newly_split[hsplit_pipe->pipe_idx] = true; 1846 repopulate_pipes = true; 1847 } 1848 if (split[i] == 4) { 1849 struct pipe_ctx *pipe_4to1; 1850 1851 if (odm && old_pipe->next_odm_pipe) 1852 old_index = old_pipe->next_odm_pipe->pipe_idx; 1853 else if (!odm && old_pipe->bottom_pipe && 1854 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1855 old_index = old_pipe->bottom_pipe->pipe_idx; 1856 else 1857 old_index = -1; 1858 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1859 ASSERT(pipe_4to1); 1860 if (!pipe_4to1) 1861 goto validate_fail; 1862 if (!dcn32_split_stream_for_mpc_or_odm( 1863 dc, &context->res_ctx, 1864 pipe, pipe_4to1, odm)) 1865 goto validate_fail; 1866 newly_split[pipe_4to1->pipe_idx] = true; 1867 1868 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe 1869 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) 1870 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1871 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1872 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && 1873 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1874 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1875 else 1876 old_index = -1; 1877 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1878 ASSERT(pipe_4to1); 1879 if (!pipe_4to1) 1880 goto validate_fail; 1881 if (!dcn32_split_stream_for_mpc_or_odm( 1882 dc, &context->res_ctx, 1883 hsplit_pipe, pipe_4to1, odm)) 1884 goto validate_fail; 1885 newly_split[pipe_4to1->pipe_idx] = true; 1886 } 1887 if (odm) 1888 dcn20_build_mapped_resource(dc, context, pipe->stream); 1889 } 1890 1891 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1892 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1893 1894 if (pipe->plane_state) { 1895 if (!resource_build_scaling_params(pipe)) 1896 goto validate_fail; 1897 } 1898 } 1899 1900 /* Actual dsc count per stream dsc validation*/ 1901 if (!dcn20_validate_dsc(dc, context)) { 1902 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 1903 goto validate_fail; 1904 } 1905 1906 if (repopulate_pipes) { 1907 int flag_max_mpc_comb = vba->maxMpcComb; 1908 int flag_vlevel = vlevel; 1909 int i; 1910 1911 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1912 1913 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case 1914 * we have to re-calculate the DET allocation and run through DML once more to 1915 * ensure all the params are calculated correctly. We do not need to run the 1916 * pipe split check again after this call (pipes are already split / merged). 1917 * */ 1918 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1919 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1920 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1921 if (vlevel == context->bw_ctx.dml.soc.num_states) { 1922 /* failed after DET size changes */ 1923 goto validate_fail; 1924 } else if (flag_max_mpc_comb == 0 && 1925 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { 1926 /* check the context constructed with pipe split flags is still valid*/ 1927 bool flags_valid = false; 1928 for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1929 if (vba->ModeSupport[i][flag_max_mpc_comb]) { 1930 vba->maxMpcComb = flag_max_mpc_comb; 1931 vba->VoltageLevel = i; 1932 vlevel = i; 1933 flags_valid = true; 1934 } 1935 } 1936 1937 /* this should never happen */ 1938 if (!flags_valid) 1939 goto validate_fail; 1940 } 1941 } 1942 *vlevel_out = vlevel; 1943 *pipe_cnt_out = pipe_cnt; 1944 1945 out = true; 1946 goto validate_out; 1947 1948 validate_fail: 1949 out = false; 1950 1951 validate_out: 1952 return out; 1953 } 1954 1955 1956 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 1957 display_e2e_pipe_params_st *pipes, 1958 int pipe_cnt, 1959 int vlevel) 1960 { 1961 int i, pipe_idx, vlevel_temp = 0; 1962 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 1963 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1964 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; 1965 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 1966 dm_dram_clock_change_unsupported; 1967 unsigned int dummy_latency_index = 0; 1968 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1969 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1970 bool subvp_in_use = dcn32_subvp_in_use(dc, context); 1971 unsigned int min_dram_speed_mts_margin; 1972 bool need_fclk_lat_as_dummy = false; 1973 bool is_subvp_p_drr = false; 1974 struct dc_stream_state *fpo_candidate_stream = NULL; 1975 1976 dc_assert_fp_enabled(); 1977 1978 /* need to find dummy latency index for subvp */ 1979 if (subvp_in_use) { 1980 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */ 1981 if (!pstate_en) { 1982 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 1983 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter; 1984 pstate_en = true; 1985 is_subvp_p_drr = true; 1986 } 1987 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 1988 context, pipes, pipe_cnt, vlevel); 1989 1990 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is 1991 * scheduled correctly to account for dummy pstate. 1992 */ 1993 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 1994 need_fclk_lat_as_dummy = true; 1995 context->bw_ctx.dml.soc.fclk_change_latency_us = 1996 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 1997 } 1998 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 1999 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2000 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2001 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 2002 if (is_subvp_p_drr) { 2003 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 2004 } 2005 } 2006 2007 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 2008 for (i = 0; i < context->stream_count; i++) { 2009 if (context->streams[i]) 2010 context->streams[i]->fpo_in_use = false; 2011 } 2012 2013 if (!pstate_en || (!dc->debug.disable_fpo_optimizations && 2014 pstate_en && vlevel != 0)) { 2015 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ 2016 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); 2017 if (fpo_candidate_stream) { 2018 fpo_candidate_stream->fpo_in_use = true; 2019 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; 2020 } 2021 2022 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2023 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 2024 context, pipes, pipe_cnt, vlevel); 2025 2026 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch 2027 * we reinstate the original dram_clock_change_latency_us on the context 2028 * and all variables that may have changed up to this point, except the 2029 * newly found dummy_latency_index 2030 */ 2031 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2032 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2033 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so 2034 * prefetch is scheduled correctly to account for dummy pstate. 2035 */ 2036 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 2037 need_fclk_lat_as_dummy = true; 2038 context->bw_ctx.dml.soc.fclk_change_latency_us = 2039 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2040 } 2041 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false); 2042 if (vlevel_temp < vlevel) { 2043 vlevel = vlevel_temp; 2044 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 2045 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2046 pstate_en = true; 2047 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank; 2048 } else { 2049 /* Restore FCLK latency and re-run validation to go back to original validation 2050 * output if we find that enabling FPO does not give us any benefit (i.e. lower 2051 * voltage level) 2052 */ 2053 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 2054 for (i = 0; i < context->stream_count; i++) { 2055 if (context->streams[i]) 2056 context->streams[i]->fpo_in_use = false; 2057 } 2058 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2059 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2060 } 2061 } 2062 } 2063 2064 /* Set B: 2065 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, 2066 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark 2067 * calculations to cover bootup clocks. 2068 * DCFCLK: soc.clock_limits[2] when available 2069 * UCLK: soc.clock_limits[2] when available 2070 */ 2071 if (dcn3_2_soc.num_states > 2) { 2072 vlevel_temp = 2; 2073 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; 2074 } else 2075 dcfclk = 615; //DCFCLK Vmin_lv 2076 2077 pipes[0].clks_cfg.voltage = vlevel_temp; 2078 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2079 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2080 2081 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 2082 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 2083 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us; 2084 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 2085 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 2086 } 2087 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2088 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2089 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2090 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2091 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2092 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2093 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2094 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2095 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2096 context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2097 2098 /* Set D: 2099 * All clocks min. 2100 * DCFCLK: Min, as reported by PM FW when available 2101 * UCLK : Min, as reported by PM FW when available 2102 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) 2103 */ 2104 2105 /* 2106 if (dcn3_2_soc.num_states > 2) { 2107 vlevel_temp = 0; 2108 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; 2109 } else 2110 dcfclk = 615; //DCFCLK Vmin_lv 2111 2112 pipes[0].clks_cfg.voltage = vlevel_temp; 2113 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2114 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2115 2116 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 2117 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 2118 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us; 2119 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 2120 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 2121 } 2122 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2123 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2124 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2125 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2126 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2127 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2128 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2129 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2130 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2131 context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2132 */ 2133 2134 /* Set C, for Dummy P-State: 2135 * All clocks min. 2136 * DCFCLK: Min, as reported by PM FW, when available 2137 * UCLK : Min, as reported by PM FW, when available 2138 * pstate latency as per UCLK state dummy pstate latency 2139 */ 2140 2141 // For Set A and Set C use values from validation 2142 pipes[0].clks_cfg.voltage = vlevel; 2143 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; 2144 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2145 2146 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2147 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching; 2148 } 2149 2150 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 2151 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 2152 min_dram_speed_mts_margin = 160; 2153 2154 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2155 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; 2156 2157 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == 2158 dm_dram_clock_change_unsupported) { 2159 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; 2160 2161 min_dram_speed_mts = 2162 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; 2163 } 2164 2165 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) { 2166 /* find largest table entry that is lower than dram speed, 2167 * but lower than DPM0 still uses DPM0 2168 */ 2169 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) 2170 if (min_dram_speed_mts + min_dram_speed_mts_margin > 2171 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) 2172 break; 2173 } 2174 2175 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2176 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2177 2178 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us; 2179 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 2180 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 2181 } 2182 2183 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2184 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2185 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2186 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2187 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2188 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2189 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2190 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2191 /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. 2192 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM 2193 * value. 2194 */ 2195 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2196 context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2197 2198 if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { 2199 /* The only difference between A and C is p-state latency, if p-state is not supported 2200 * with full p-state latency we want to calculate DLG based on dummy p-state latency, 2201 * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30. 2202 */ 2203 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 2204 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 2205 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case 2206 * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported 2207 */ 2208 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2209 } else { 2210 /* Set A: 2211 * All clocks min. 2212 * DCFCLK: Min, as reported by PM FW, when available 2213 * UCLK: Min, as reported by PM FW, when available 2214 */ 2215 2216 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally 2217 */ 2218 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2219 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 2220 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 2221 2222 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2223 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2224 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2225 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2226 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2227 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2228 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2229 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2230 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2231 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2232 } 2233 2234 /* Make set D = set A since we do not optimized watermarks for MALL */ 2235 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 2236 2237 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2238 if (!context->res_ctx.pipe_ctx[i].stream) 2239 continue; 2240 2241 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 2242 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 2243 2244 if (dc->config.forced_clocks) { 2245 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2246 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2247 } 2248 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 2249 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2250 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2251 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2252 2253 pipe_idx++; 2254 } 2255 2256 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 2257 2258 /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */ 2259 if (need_fclk_lat_as_dummy) 2260 context->bw_ctx.dml.soc.fclk_change_latency_us = 2261 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2262 2263 dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2264 2265 if (!pstate_en) 2266 /* Restore full p-state latency */ 2267 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2268 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2269 2270 /* revert fclk lat changes if required */ 2271 if (need_fclk_lat_as_dummy) 2272 context->bw_ctx.dml.soc.fclk_change_latency_us = 2273 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2274 } 2275 2276 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 2277 unsigned int *optimal_dcfclk, 2278 unsigned int *optimal_fclk) 2279 { 2280 double bw_from_dram, bw_from_dram1, bw_from_dram2; 2281 2282 bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * 2283 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); 2284 bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * 2285 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); 2286 2287 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 2288 2289 if (optimal_fclk) 2290 *optimal_fclk = bw_from_dram / 2291 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2292 2293 if (optimal_dcfclk) 2294 *optimal_dcfclk = bw_from_dram / 2295 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2296 } 2297 2298 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 2299 unsigned int index) 2300 { 2301 int i; 2302 2303 if (*num_entries == 0) 2304 return; 2305 2306 for (i = index; i < *num_entries - 1; i++) { 2307 table[i] = table[i + 1]; 2308 } 2309 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 2310 } 2311 2312 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) 2313 { 2314 int i; 2315 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2316 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2317 2318 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2319 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2320 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2321 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2322 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2323 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2324 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2325 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2326 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2327 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2328 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2329 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2330 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2331 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2332 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2333 } 2334 2335 /* Scan through clock values we currently have and if they are 0, 2336 * then populate it with dcn3_2_soc.clock_limits[] value. 2337 * 2338 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being 2339 * 0, will cause it to skip building the clock table. 2340 */ 2341 if (max_dcfclk_mhz == 0) 2342 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2343 if (max_dispclk_mhz == 0) 2344 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2345 if (max_dtbclk_mhz == 0) 2346 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; 2347 if (max_uclk_mhz == 0) 2348 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; 2349 } 2350 2351 static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry, 2352 struct _vcs_dpi_voltage_scaling_st *second_entry) 2353 { 2354 struct _vcs_dpi_voltage_scaling_st temp_entry = *first_entry; 2355 *first_entry = *second_entry; 2356 *second_entry = temp_entry; 2357 } 2358 2359 /* 2360 * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK 2361 */ 2362 static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2363 { 2364 unsigned int start_index = 0; 2365 unsigned int end_index = 0; 2366 unsigned int current_bw = 0; 2367 2368 for (int i = 0; i < (*num_entries - 1); i++) { 2369 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { 2370 current_bw = table[i].net_bw_in_kbytes_sec; 2371 start_index = i; 2372 end_index = ++i; 2373 2374 while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) 2375 end_index = ++i; 2376 } 2377 2378 if (start_index != end_index) { 2379 for (int j = start_index; j < end_index; j++) { 2380 for (int k = start_index; k < end_index; k++) { 2381 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) 2382 swap_table_entries(&table[k], &table[k+1]); 2383 } 2384 } 2385 } 2386 2387 start_index = 0; 2388 end_index = 0; 2389 2390 } 2391 } 2392 2393 /* 2394 * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing 2395 * and remove entries that do not 2396 */ 2397 static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2398 { 2399 for (int i = 0; i < (*num_entries - 1); i++) { 2400 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { 2401 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || 2402 (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) 2403 remove_entry_from_table_at_index(table, num_entries, i); 2404 } 2405 } 2406 } 2407 2408 /* 2409 * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings 2410 * Input: 2411 * max_clk_limit - struct containing the desired clock timings 2412 * Output: 2413 * curr_clk_limit - struct containing the timings that need to be overwritten 2414 * Return: 0 upon success, non-zero for failure 2415 */ 2416 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, 2417 struct clk_limit_table_entry *curr_clk_limit) 2418 { 2419 if (NULL == max_clk_limit || NULL == curr_clk_limit) 2420 return -1; //invalid parameters 2421 2422 //only overwrite if desired max clock frequency is initialized 2423 if (max_clk_limit->dcfclk_mhz != 0) 2424 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; 2425 2426 if (max_clk_limit->fclk_mhz != 0) 2427 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz; 2428 2429 if (max_clk_limit->memclk_mhz != 0) 2430 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz; 2431 2432 if (max_clk_limit->socclk_mhz != 0) 2433 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz; 2434 2435 if (max_clk_limit->dtbclk_mhz != 0) 2436 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz; 2437 2438 if (max_clk_limit->dispclk_mhz != 0) 2439 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz; 2440 2441 return 0; 2442 } 2443 2444 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, 2445 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2446 { 2447 int i, j; 2448 struct _vcs_dpi_voltage_scaling_st entry = {0}; 2449 struct clk_limit_table_entry max_clk_data = {0}; 2450 2451 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 2452 2453 static const unsigned int num_dcfclk_stas = 5; 2454 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2455 2456 unsigned int num_uclk_dpms = 0; 2457 unsigned int num_fclk_dpms = 0; 2458 unsigned int num_dcfclk_dpms = 0; 2459 2460 unsigned int num_dc_uclk_dpms = 0; 2461 unsigned int num_dc_fclk_dpms = 0; 2462 unsigned int num_dc_dcfclk_dpms = 0; 2463 2464 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2465 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) 2466 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2467 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) 2468 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2469 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) 2470 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2471 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) 2472 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2473 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) 2474 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2475 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz) 2476 max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2477 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz) 2478 max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2479 2480 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { 2481 num_uclk_dpms++; 2482 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) 2483 num_dc_uclk_dpms++; 2484 } 2485 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { 2486 num_fclk_dpms++; 2487 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) 2488 num_dc_fclk_dpms++; 2489 } 2490 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) { 2491 num_dcfclk_dpms++; 2492 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) 2493 num_dc_dcfclk_dpms++; 2494 } 2495 } 2496 2497 if (!disable_dc_mode_overwrite) { 2498 //Overwrite max frequencies with max DC mode frequencies for DC mode systems 2499 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); 2500 num_uclk_dpms = num_dc_uclk_dpms; 2501 num_fclk_dpms = num_dc_fclk_dpms; 2502 num_dcfclk_dpms = num_dc_dcfclk_dpms; 2503 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; 2504 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; 2505 } 2506 2507 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) 2508 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; 2509 2510 if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz) 2511 return -1; 2512 2513 if (max_clk_data.dppclk_mhz == 0) 2514 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; 2515 2516 if (max_clk_data.fclk_mhz == 0) 2517 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * 2518 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 2519 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; 2520 2521 if (max_clk_data.phyclk_mhz == 0) 2522 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2523 2524 *num_entries = 0; 2525 entry.dispclk_mhz = max_clk_data.dispclk_mhz; 2526 entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3; 2527 entry.dppclk_mhz = max_clk_data.dppclk_mhz; 2528 entry.dtbclk_mhz = max_clk_data.dtbclk_mhz; 2529 entry.phyclk_mhz = max_clk_data.phyclk_mhz; 2530 entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2531 entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2532 2533 // Insert all the DCFCLK STAs 2534 for (i = 0; i < num_dcfclk_stas; i++) { 2535 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 2536 entry.fabricclk_mhz = 0; 2537 entry.dram_speed_mts = 0; 2538 2539 get_optimal_ntuple(&entry); 2540 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2541 insert_entry_into_table_sorted(table, num_entries, &entry); 2542 } 2543 2544 // Insert the max DCFCLK 2545 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; 2546 entry.fabricclk_mhz = 0; 2547 entry.dram_speed_mts = 0; 2548 2549 get_optimal_ntuple(&entry); 2550 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2551 insert_entry_into_table_sorted(table, num_entries, &entry); 2552 2553 // Insert the UCLK DPMS 2554 for (i = 0; i < num_uclk_dpms; i++) { 2555 entry.dcfclk_mhz = 0; 2556 entry.fabricclk_mhz = 0; 2557 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 2558 2559 get_optimal_ntuple(&entry); 2560 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2561 insert_entry_into_table_sorted(table, num_entries, &entry); 2562 } 2563 2564 // If FCLK is coarse grained, insert individual DPMs. 2565 if (num_fclk_dpms > 2) { 2566 for (i = 0; i < num_fclk_dpms; i++) { 2567 entry.dcfclk_mhz = 0; 2568 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2569 entry.dram_speed_mts = 0; 2570 2571 get_optimal_ntuple(&entry); 2572 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2573 insert_entry_into_table_sorted(table, num_entries, &entry); 2574 } 2575 } 2576 // If FCLK fine grained, only insert max 2577 else { 2578 entry.dcfclk_mhz = 0; 2579 entry.fabricclk_mhz = max_clk_data.fclk_mhz; 2580 entry.dram_speed_mts = 0; 2581 2582 get_optimal_ntuple(&entry); 2583 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2584 insert_entry_into_table_sorted(table, num_entries, &entry); 2585 } 2586 2587 // At this point, the table contains all "points of interest" based on 2588 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 2589 // ratios (by derate, are exact). 2590 2591 // Remove states that require higher clocks than are supported 2592 for (i = *num_entries - 1; i >= 0 ; i--) { 2593 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || 2594 table[i].fabricclk_mhz > max_clk_data.fclk_mhz || 2595 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16) 2596 remove_entry_from_table_at_index(table, num_entries, i); 2597 } 2598 2599 // Insert entry with all max dc limits without bandwidth matching 2600 if (!disable_dc_mode_overwrite) { 2601 struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry; 2602 2603 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; 2604 max_dc_limits_entry.fabricclk_mhz = max_clk_data.fclk_mhz; 2605 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16; 2606 2607 max_dc_limits_entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&max_dc_limits_entry); 2608 insert_entry_into_table_sorted(table, num_entries, &max_dc_limits_entry); 2609 2610 sort_entries_with_same_bw(table, num_entries); 2611 remove_inconsistent_entries(table, num_entries); 2612 } 2613 2614 // At this point, the table only contains supported points of interest 2615 // it could be used as is, but some states may be redundant due to 2616 // coarse grained nature of some clocks, so we want to round up to 2617 // coarse grained DPMs and remove duplicates. 2618 2619 // Round up UCLKs 2620 for (i = *num_entries - 1; i >= 0 ; i--) { 2621 for (j = 0; j < num_uclk_dpms; j++) { 2622 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 2623 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 2624 break; 2625 } 2626 } 2627 } 2628 2629 // If FCLK is coarse grained, round up to next DPMs 2630 if (num_fclk_dpms > 2) { 2631 for (i = *num_entries - 1; i >= 0 ; i--) { 2632 for (j = 0; j < num_fclk_dpms; j++) { 2633 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 2634 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 2635 break; 2636 } 2637 } 2638 } 2639 } 2640 // Otherwise, round up to minimum. 2641 else { 2642 for (i = *num_entries - 1; i >= 0 ; i--) { 2643 if (table[i].fabricclk_mhz < min_fclk_mhz) { 2644 table[i].fabricclk_mhz = min_fclk_mhz; 2645 } 2646 } 2647 } 2648 2649 // Round DCFCLKs up to minimum 2650 for (i = *num_entries - 1; i >= 0 ; i--) { 2651 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 2652 table[i].dcfclk_mhz = min_dcfclk_mhz; 2653 } 2654 } 2655 2656 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 2657 i = 0; 2658 while (i < *num_entries - 1) { 2659 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 2660 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 2661 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 2662 remove_entry_from_table_at_index(table, num_entries, i + 1); 2663 else 2664 i++; 2665 } 2666 2667 // Fix up the state indicies 2668 for (i = *num_entries - 1; i >= 0 ; i--) { 2669 table[i].state = i; 2670 } 2671 2672 return 0; 2673 } 2674 2675 /* 2676 * dcn32_update_bw_bounding_box 2677 * 2678 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from 2679 * spreadsheet with actual values as per dGPU SKU: 2680 * - with passed few options from dc->config 2681 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might 2682 * need to get it from PM FW) 2683 * - with passed latency values (passed in ns units) in dc-> bb override for 2684 * debugging purposes 2685 * - with passed latencies from VBIOS (in 100_ns units) if available for 2686 * certain dGPU SKU 2687 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU 2688 * of the same ASIC) 2689 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM 2690 * FW for different clocks (which might differ for certain dGPU SKU of the 2691 * same ASIC) 2692 */ 2693 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 2694 { 2695 dc_assert_fp_enabled(); 2696 2697 /* Overrides from dc->config options */ 2698 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 2699 2700 /* Override from passed dc->bb_overrides if available*/ 2701 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 2702 && dc->bb_overrides.sr_exit_time_ns) { 2703 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 2704 } 2705 2706 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) 2707 != dc->bb_overrides.sr_enter_plus_exit_time_ns 2708 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 2709 dcn3_2_soc.sr_enter_plus_exit_time_us = 2710 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 2711 } 2712 2713 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 2714 && dc->bb_overrides.urgent_latency_ns) { 2715 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2716 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2717 } 2718 2719 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) 2720 != dc->bb_overrides.dram_clock_change_latency_ns 2721 && dc->bb_overrides.dram_clock_change_latency_ns) { 2722 dcn3_2_soc.dram_clock_change_latency_us = 2723 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 2724 } 2725 2726 if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000) 2727 != dc->bb_overrides.fclk_clock_change_latency_ns 2728 && dc->bb_overrides.fclk_clock_change_latency_ns) { 2729 dcn3_2_soc.fclk_change_latency_us = 2730 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 2731 } 2732 2733 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) 2734 != dc->bb_overrides.dummy_clock_change_latency_ns 2735 && dc->bb_overrides.dummy_clock_change_latency_ns) { 2736 dcn3_2_soc.dummy_pstate_latency_us = 2737 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 2738 } 2739 2740 /* Override from VBIOS if VBIOS bb_info available */ 2741 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 2742 struct bp_soc_bb_info bb_info = {0}; 2743 2744 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 2745 if (bb_info.dram_clock_change_latency_100ns > 0) 2746 dcn3_2_soc.dram_clock_change_latency_us = 2747 bb_info.dram_clock_change_latency_100ns * 10; 2748 2749 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 2750 dcn3_2_soc.sr_enter_plus_exit_time_us = 2751 bb_info.dram_sr_enter_exit_latency_100ns * 10; 2752 2753 if (bb_info.dram_sr_exit_latency_100ns > 0) 2754 dcn3_2_soc.sr_exit_time_us = 2755 bb_info.dram_sr_exit_latency_100ns * 10; 2756 } 2757 } 2758 2759 /* Override from VBIOS for num_chan */ 2760 if (dc->ctx->dc_bios->vram_info.num_chans) { 2761 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2762 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc, 2763 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); 2764 } 2765 2766 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2767 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2768 2769 /* DML DSC delay factor workaround */ 2770 dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 2771 2772 dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 2773 2774 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 2775 dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2776 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2777 2778 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 2779 if (bw_params->clk_table.entries[0].memclk_mhz) { 2780 if (dc->debug.use_legacy_soc_bb_mechanism) { 2781 unsigned int i = 0, j = 0, num_states = 0; 2782 2783 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2784 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2785 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2786 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2787 unsigned int min_dcfclk = UINT_MAX; 2788 /* Set 199 as first value in STA target array to have a minimum DCFCLK value. 2789 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */ 2790 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2791 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 2792 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 2793 2794 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2795 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2796 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2797 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && 2798 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk) 2799 min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz; 2800 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2801 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2802 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2803 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2804 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2805 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2806 } 2807 if (min_dcfclk > dcfclk_sta_targets[0]) 2808 dcfclk_sta_targets[0] = min_dcfclk; 2809 if (!max_dcfclk_mhz) 2810 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2811 if (!max_dispclk_mhz) 2812 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2813 if (!max_dppclk_mhz) 2814 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; 2815 if (!max_phyclk_mhz) 2816 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2817 2818 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2819 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2820 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2821 num_dcfclk_sta_targets++; 2822 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2823 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2824 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2825 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2826 dcfclk_sta_targets[i] = max_dcfclk_mhz; 2827 break; 2828 } 2829 } 2830 // Update size of array since we "removed" duplicates 2831 num_dcfclk_sta_targets = i + 1; 2832 } 2833 2834 num_uclk_states = bw_params->clk_table.num_entries; 2835 2836 // Calculate optimal dcfclk for each uclk 2837 for (i = 0; i < num_uclk_states; i++) { 2838 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2839 &optimal_dcfclk_for_uclk[i], NULL); 2840 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2841 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2842 } 2843 } 2844 2845 // Calculate optimal uclk for each dcfclk sta target 2846 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2847 for (j = 0; j < num_uclk_states; j++) { 2848 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2849 optimal_uclk_for_dcfclk_sta_targets[i] = 2850 bw_params->clk_table.entries[j].memclk_mhz * 16; 2851 break; 2852 } 2853 } 2854 } 2855 2856 i = 0; 2857 j = 0; 2858 // create the final dcfclk and uclk table 2859 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2860 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2861 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2862 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2863 } else { 2864 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2865 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2866 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2867 } else { 2868 j = num_uclk_states; 2869 } 2870 } 2871 } 2872 2873 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2874 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2875 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2876 } 2877 2878 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2879 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2880 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2881 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2882 } 2883 2884 dcn3_2_soc.num_states = num_states; 2885 for (i = 0; i < dcn3_2_soc.num_states; i++) { 2886 dcn3_2_soc.clock_limits[i].state = i; 2887 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2888 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2889 2890 /* Fill all states with max values of all these clocks */ 2891 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2892 dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2893 dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2894 dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 2895 2896 /* Populate from bw_params for DTBCLK, SOCCLK */ 2897 if (i > 0) { 2898 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 2899 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; 2900 } else { 2901 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2902 } 2903 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 2904 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2905 } 2906 2907 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 2908 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; 2909 else 2910 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 2911 2912 if (!dram_speed_mts[i] && i > 0) 2913 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; 2914 else 2915 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2916 2917 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ 2918 /* PHYCLK_D18, PHYCLK_D32 */ 2919 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2920 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2921 } 2922 } else { 2923 build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params, 2924 dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); 2925 } 2926 2927 /* Re-init DML with updated bb */ 2928 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2929 if (dc->current_state) 2930 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2931 } 2932 } 2933 2934 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 2935 int pipe_cnt) 2936 { 2937 dc_assert_fp_enabled(); 2938 2939 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 2940 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 2941 } 2942 2943 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) 2944 { 2945 bool allow = false; 2946 uint32_t refresh_rate = 0; 2947 2948 /* Allow subvp on displays that have active margin for 2560x1440@60hz displays 2949 * only for now. There must be no scaling as well. 2950 * 2951 * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs 2952 * for p-state switching. 2953 */ 2954 if (pipe->stream && pipe->plane_state) { 2955 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 2956 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 2957 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 2958 if (pipe->stream->timing.v_addressable == 1440 && 2959 pipe->stream->timing.h_addressable == 2560 && 2960 refresh_rate >= 55 && refresh_rate <= 65 && 2961 pipe->plane_state->src_rect.height == 1440 && 2962 pipe->plane_state->src_rect.width == 2560 && 2963 pipe->plane_state->dst_rect.height == 1440 && 2964 pipe->plane_state->dst_rect.width == 2560) 2965 allow = true; 2966 } 2967 return allow; 2968 } 2969 2970 /** 2971 * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp 2972 * 2973 * @dc: Current DC state 2974 * @context: New DC state to be programmed 2975 * @pipe: Pipe to be considered for use in subvp 2976 * 2977 * On high refresh rate display configs, we will allow subvp under the following conditions: 2978 * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440 2979 * 2. Refresh rate is between 120hz - 165hz 2980 * 3. No scaling 2981 * 4. Freesync is inactive 2982 * 5. For single display cases, freesync must be disabled 2983 * 2984 * Return: True if pipe can be used for subvp, false otherwise 2985 */ 2986 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe) 2987 { 2988 bool allow = false; 2989 uint32_t refresh_rate = 0; 2990 uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh; 2991 uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh; 2992 uint32_t min_refresh = subvp_max_refresh; 2993 uint32_t i; 2994 2995 /* Only allow SubVP on high refresh displays if all connected displays 2996 * are considered "high refresh" (i.e. >= 120hz). We do not want to 2997 * allow combinations such as 120hz (SubVP) + 60hz (SubVP). 2998 */ 2999 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3000 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3001 3002 if (!pipe_ctx->stream) 3003 continue; 3004 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 + 3005 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1) 3006 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total); 3007 3008 if (refresh_rate < min_refresh) 3009 min_refresh = refresh_rate; 3010 } 3011 3012 if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream && 3013 pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) { 3014 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 3015 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 3016 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 3017 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) { 3018 for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) { 3019 uint32_t width = subvp_high_refresh_list.res[i].width; 3020 uint32_t height = subvp_high_refresh_list.res[i].height; 3021 3022 if (dcn32_check_native_scaling_for_res(pipe, width, height)) { 3023 if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) { 3024 allow = true; 3025 break; 3026 } 3027 } 3028 } 3029 } 3030 } 3031 return allow; 3032 } 3033 3034 /** 3035 * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy 3036 * 3037 * @dc: Current DC state 3038 * @context: New DC state to be programmed 3039 * 3040 * Return: Max vratio for prefetch 3041 */ 3042 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context) 3043 { 3044 double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4 3045 int i; 3046 3047 /* For single display MPO configs, allow the max vratio to be 8 3048 * if any plane is YUV420 format 3049 */ 3050 if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) { 3051 for (i = 0; i < context->stream_status[0].plane_count; i++) { 3052 if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr || 3053 context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) { 3054 max_vratio_pre = __DML_MAX_VRATIO_PRE__; 3055 } 3056 } 3057 } 3058 return max_vratio_pre; 3059 } 3060 3061 /** 3062 * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case 3063 * 3064 * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config). 3065 * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the 3066 * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has 3067 * ActiveMargin <= 0 to be the FPO stream candidate if found. 3068 * 3069 * 3070 * @dc: current dc state 3071 * @context: new dc state 3072 * @fpo_candidate_stream: pointer to FPO stream candidate if one is found 3073 * 3074 * Return: void 3075 */ 3076 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream) 3077 { 3078 unsigned int i, pipe_idx; 3079 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 3080 3081 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3082 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3083 3084 if (!pipe->stream) 3085 continue; 3086 3087 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { 3088 *fpo_candidate_stream = pipe->stream; 3089 break; 3090 } 3091 pipe_idx++; 3092 } 3093 } 3094 3095 /** 3096 * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE 3097 * 3098 * @dc: current dc state 3099 * @context: new dc state 3100 * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found" 3101 * 3102 * Return: True if VACTIVE display is found, false otherwise 3103 */ 3104 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us) 3105 { 3106 unsigned int i, pipe_idx; 3107 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 3108 bool vactive_found = false; 3109 unsigned int blank_us = 0; 3110 3111 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3112 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3113 3114 if (!pipe->stream) 3115 continue; 3116 3117 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / 3118 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000; 3119 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us && 3120 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) { 3121 vactive_found = true; 3122 break; 3123 } 3124 pipe_idx++; 3125 } 3126 return vactive_found; 3127 } 3128 3129 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 3130 { 3131 dc_assert_fp_enabled(); 3132 dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0; 3133 } 3134 3135 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) 3136 { 3137 // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue) 3138 if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) && 3139 dc->dml.soc.num_chans <= 8) { 3140 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; 3141 3142 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 && 3143 num_mclk_levels > 1) { 3144 context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16; 3145 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 3146 } 3147 } 3148 } 3149