1 /* 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "resource.h" 27 #include "clk_mgr.h" 28 29 #include "dml/dcn20/dcn20_fpu.h" 30 #include "dcn31_fpu.h" 31 32 /** 33 * DOC: DCN31x FPU manipulation Overview 34 * 35 * The DCN architecture relies on FPU operations, which require special 36 * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we 37 * want to avoid spreading FPU access across multiple files. With this idea in 38 * mind, this file aims to centralize all DCN3.1.x functions that require FPU 39 * access in a single place. Code in this file follows the following code 40 * pattern: 41 * 42 * 1. Functions that use FPU operations should be isolated in static functions. 43 * 2. The FPU functions should have the noinline attribute to ensure anything 44 * that deals with FP register is contained within this call. 45 * 3. All function that needs to be accessed outside this file requires a 46 * public interface that not uses any FPU reference. 47 * 4. Developers **must not** use DC_FP_START/END in this file, but they need 48 * to ensure that the caller invokes it before access any function available 49 * in this file. For this reason, public functions in this file must invoke 50 * dc_assert_fp_enabled(); 51 */ 52 53 struct _vcs_dpi_ip_params_st dcn3_1_ip = { 54 .gpuvm_enable = 1, 55 .gpuvm_max_page_table_levels = 1, 56 .hostvm_enable = 1, 57 .hostvm_max_page_table_levels = 2, 58 .rob_buffer_size_kbytes = 64, 59 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, 60 .config_return_buffer_size_in_kbytes = 1792, 61 .compressed_buffer_segment_size_in_kbytes = 64, 62 .meta_fifo_size_in_kentries = 32, 63 .zero_size_buffer_entries = 512, 64 .compbuf_reserved_space_64b = 256, 65 .compbuf_reserved_space_zs = 64, 66 .dpp_output_buffer_pixels = 2560, 67 .opp_output_buffer_lines = 1, 68 .pixel_chunk_size_kbytes = 8, 69 .meta_chunk_size_kbytes = 2, 70 .min_meta_chunk_size_bytes = 256, 71 .writeback_chunk_size_kbytes = 8, 72 .ptoi_supported = false, 73 .num_dsc = 3, 74 .maximum_dsc_bits_per_component = 10, 75 .dsc422_native_support = false, 76 .is_line_buffer_bpp_fixed = true, 77 .line_buffer_fixed_bpp = 48, 78 .line_buffer_size_bits = 789504, 79 .max_line_buffer_lines = 12, 80 .writeback_interface_buffer_size_kbytes = 90, 81 .max_num_dpp = 4, 82 .max_num_otg = 4, 83 .max_num_hdmi_frl_outputs = 1, 84 .max_num_wb = 1, 85 .max_dchub_pscl_bw_pix_per_clk = 4, 86 .max_pscl_lb_bw_pix_per_clk = 2, 87 .max_lb_vscl_bw_pix_per_clk = 4, 88 .max_vscl_hscl_bw_pix_per_clk = 4, 89 .max_hscl_ratio = 6, 90 .max_vscl_ratio = 6, 91 .max_hscl_taps = 8, 92 .max_vscl_taps = 8, 93 .dpte_buffer_size_in_pte_reqs_luma = 64, 94 .dpte_buffer_size_in_pte_reqs_chroma = 34, 95 .dispclk_ramp_margin_percent = 1, 96 .max_inter_dcn_tile_repeaters = 8, 97 .cursor_buffer_size = 16, 98 .cursor_chunk_size = 2, 99 .writeback_line_buffer_buffer_size = 0, 100 .writeback_min_hscl_ratio = 1, 101 .writeback_min_vscl_ratio = 1, 102 .writeback_max_hscl_ratio = 1, 103 .writeback_max_vscl_ratio = 1, 104 .writeback_max_hscl_taps = 1, 105 .writeback_max_vscl_taps = 1, 106 .dppclk_delay_subtotal = 46, 107 .dppclk_delay_scl = 50, 108 .dppclk_delay_scl_lb_only = 16, 109 .dppclk_delay_cnvc_formatter = 27, 110 .dppclk_delay_cnvc_cursor = 6, 111 .dispclk_delay_subtotal = 119, 112 .dynamic_metadata_vm_enabled = false, 113 .odm_combine_4to1_supported = false, 114 .dcc_supported = true, 115 }; 116 117 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 118 /*TODO: correct dispclk/dppclk voltage level determination*/ 119 .clock_limits = { 120 { 121 .state = 0, 122 .dispclk_mhz = 1200.0, 123 .dppclk_mhz = 1200.0, 124 .phyclk_mhz = 600.0, 125 .phyclk_d18_mhz = 667.0, 126 .dscclk_mhz = 186.0, 127 .dtbclk_mhz = 625.0, 128 }, 129 { 130 .state = 1, 131 .dispclk_mhz = 1200.0, 132 .dppclk_mhz = 1200.0, 133 .phyclk_mhz = 810.0, 134 .phyclk_d18_mhz = 667.0, 135 .dscclk_mhz = 209.0, 136 .dtbclk_mhz = 625.0, 137 }, 138 { 139 .state = 2, 140 .dispclk_mhz = 1200.0, 141 .dppclk_mhz = 1200.0, 142 .phyclk_mhz = 810.0, 143 .phyclk_d18_mhz = 667.0, 144 .dscclk_mhz = 209.0, 145 .dtbclk_mhz = 625.0, 146 }, 147 { 148 .state = 3, 149 .dispclk_mhz = 1200.0, 150 .dppclk_mhz = 1200.0, 151 .phyclk_mhz = 810.0, 152 .phyclk_d18_mhz = 667.0, 153 .dscclk_mhz = 371.0, 154 .dtbclk_mhz = 625.0, 155 }, 156 { 157 .state = 4, 158 .dispclk_mhz = 1200.0, 159 .dppclk_mhz = 1200.0, 160 .phyclk_mhz = 810.0, 161 .phyclk_d18_mhz = 667.0, 162 .dscclk_mhz = 417.0, 163 .dtbclk_mhz = 625.0, 164 }, 165 }, 166 .num_states = 5, 167 .sr_exit_time_us = 9.0, 168 .sr_enter_plus_exit_time_us = 11.0, 169 .sr_exit_z8_time_us = 442.0, 170 .sr_enter_plus_exit_z8_time_us = 560.0, 171 .writeback_latency_us = 12.0, 172 .dram_channel_width_bytes = 4, 173 .round_trip_ping_latency_dcfclk_cycles = 106, 174 .urgent_latency_pixel_data_only_us = 4.0, 175 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 176 .urgent_latency_vm_data_only_us = 4.0, 177 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 178 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 179 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 180 .pct_ideal_sdp_bw_after_urgent = 80.0, 181 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 182 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 183 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 184 .max_avg_sdp_bw_use_normal_percent = 60.0, 185 .max_avg_dram_bw_use_normal_percent = 60.0, 186 .fabric_datapath_to_dcn_data_return_bytes = 32, 187 .return_bus_width_bytes = 64, 188 .downspread_percent = 0.38, 189 .dcn_downspread_percent = 0.5, 190 .gpuvm_min_page_size_bytes = 4096, 191 .hostvm_min_page_size_bytes = 4096, 192 .do_urgent_latency_adjustment = false, 193 .urgent_latency_adjustment_fabric_clock_component_us = 0, 194 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 195 }; 196 197 struct _vcs_dpi_ip_params_st dcn3_15_ip = { 198 .gpuvm_enable = 1, 199 .gpuvm_max_page_table_levels = 1, 200 .hostvm_enable = 1, 201 .hostvm_max_page_table_levels = 2, 202 .rob_buffer_size_kbytes = 64, 203 .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE, 204 .min_comp_buffer_size_kbytes = 64, 205 .config_return_buffer_size_in_kbytes = 1024, 206 .compressed_buffer_segment_size_in_kbytes = 64, 207 .meta_fifo_size_in_kentries = 32, 208 .zero_size_buffer_entries = 512, 209 .compbuf_reserved_space_64b = 256, 210 .compbuf_reserved_space_zs = 64, 211 .dpp_output_buffer_pixels = 2560, 212 .opp_output_buffer_lines = 1, 213 .pixel_chunk_size_kbytes = 8, 214 .meta_chunk_size_kbytes = 2, 215 .min_meta_chunk_size_bytes = 256, 216 .writeback_chunk_size_kbytes = 8, 217 .ptoi_supported = false, 218 .num_dsc = 3, 219 .maximum_dsc_bits_per_component = 10, 220 .dsc422_native_support = false, 221 .is_line_buffer_bpp_fixed = true, 222 .line_buffer_fixed_bpp = 49, 223 .line_buffer_size_bits = 789504, 224 .max_line_buffer_lines = 12, 225 .writeback_interface_buffer_size_kbytes = 90, 226 .max_num_dpp = 4, 227 .max_num_otg = 4, 228 .max_num_hdmi_frl_outputs = 1, 229 .max_num_wb = 1, 230 .max_dchub_pscl_bw_pix_per_clk = 4, 231 .max_pscl_lb_bw_pix_per_clk = 2, 232 .max_lb_vscl_bw_pix_per_clk = 4, 233 .max_vscl_hscl_bw_pix_per_clk = 4, 234 .max_hscl_ratio = 6, 235 .max_vscl_ratio = 6, 236 .max_hscl_taps = 8, 237 .max_vscl_taps = 8, 238 .dpte_buffer_size_in_pte_reqs_luma = 64, 239 .dpte_buffer_size_in_pte_reqs_chroma = 34, 240 .dispclk_ramp_margin_percent = 1, 241 .max_inter_dcn_tile_repeaters = 9, 242 .cursor_buffer_size = 16, 243 .cursor_chunk_size = 2, 244 .writeback_line_buffer_buffer_size = 0, 245 .writeback_min_hscl_ratio = 1, 246 .writeback_min_vscl_ratio = 1, 247 .writeback_max_hscl_ratio = 1, 248 .writeback_max_vscl_ratio = 1, 249 .writeback_max_hscl_taps = 1, 250 .writeback_max_vscl_taps = 1, 251 .dppclk_delay_subtotal = 46, 252 .dppclk_delay_scl = 50, 253 .dppclk_delay_scl_lb_only = 16, 254 .dppclk_delay_cnvc_formatter = 27, 255 .dppclk_delay_cnvc_cursor = 6, 256 .dispclk_delay_subtotal = 119, 257 .dynamic_metadata_vm_enabled = false, 258 .odm_combine_4to1_supported = false, 259 .dcc_supported = true, 260 }; 261 262 struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = { 263 .sr_exit_time_us = 9.0, 264 .sr_enter_plus_exit_time_us = 11.0, 265 .sr_exit_z8_time_us = 50.0, 266 .sr_enter_plus_exit_z8_time_us = 50.0, 267 .writeback_latency_us = 12.0, 268 .dram_channel_width_bytes = 4, 269 .round_trip_ping_latency_dcfclk_cycles = 106, 270 .urgent_latency_pixel_data_only_us = 4.0, 271 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 272 .urgent_latency_vm_data_only_us = 4.0, 273 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 274 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 275 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 276 .pct_ideal_sdp_bw_after_urgent = 80.0, 277 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 279 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 280 .max_avg_sdp_bw_use_normal_percent = 60.0, 281 .max_avg_dram_bw_use_normal_percent = 60.0, 282 .fabric_datapath_to_dcn_data_return_bytes = 32, 283 .return_bus_width_bytes = 64, 284 .downspread_percent = 0.38, 285 .dcn_downspread_percent = 0.38, 286 .gpuvm_min_page_size_bytes = 4096, 287 .hostvm_min_page_size_bytes = 4096, 288 .do_urgent_latency_adjustment = false, 289 .urgent_latency_adjustment_fabric_clock_component_us = 0, 290 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 291 }; 292 293 struct _vcs_dpi_ip_params_st dcn3_16_ip = { 294 .gpuvm_enable = 1, 295 .gpuvm_max_page_table_levels = 1, 296 .hostvm_enable = 1, 297 .hostvm_max_page_table_levels = 2, 298 .rob_buffer_size_kbytes = 64, 299 .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE, 300 .min_comp_buffer_size_kbytes = 64, 301 .config_return_buffer_size_in_kbytes = 1024, 302 .compressed_buffer_segment_size_in_kbytes = 64, 303 .meta_fifo_size_in_kentries = 32, 304 .zero_size_buffer_entries = 512, 305 .compbuf_reserved_space_64b = 256, 306 .compbuf_reserved_space_zs = 64, 307 .dpp_output_buffer_pixels = 2560, 308 .opp_output_buffer_lines = 1, 309 .pixel_chunk_size_kbytes = 8, 310 .meta_chunk_size_kbytes = 2, 311 .min_meta_chunk_size_bytes = 256, 312 .writeback_chunk_size_kbytes = 8, 313 .ptoi_supported = false, 314 .num_dsc = 3, 315 .maximum_dsc_bits_per_component = 10, 316 .dsc422_native_support = false, 317 .is_line_buffer_bpp_fixed = true, 318 .line_buffer_fixed_bpp = 48, 319 .line_buffer_size_bits = 789504, 320 .max_line_buffer_lines = 12, 321 .writeback_interface_buffer_size_kbytes = 90, 322 .max_num_dpp = 4, 323 .max_num_otg = 4, 324 .max_num_hdmi_frl_outputs = 1, 325 .max_num_wb = 1, 326 .max_dchub_pscl_bw_pix_per_clk = 4, 327 .max_pscl_lb_bw_pix_per_clk = 2, 328 .max_lb_vscl_bw_pix_per_clk = 4, 329 .max_vscl_hscl_bw_pix_per_clk = 4, 330 .max_hscl_ratio = 6, 331 .max_vscl_ratio = 6, 332 .max_hscl_taps = 8, 333 .max_vscl_taps = 8, 334 .dpte_buffer_size_in_pte_reqs_luma = 64, 335 .dpte_buffer_size_in_pte_reqs_chroma = 34, 336 .dispclk_ramp_margin_percent = 1, 337 .max_inter_dcn_tile_repeaters = 8, 338 .cursor_buffer_size = 16, 339 .cursor_chunk_size = 2, 340 .writeback_line_buffer_buffer_size = 0, 341 .writeback_min_hscl_ratio = 1, 342 .writeback_min_vscl_ratio = 1, 343 .writeback_max_hscl_ratio = 1, 344 .writeback_max_vscl_ratio = 1, 345 .writeback_max_hscl_taps = 1, 346 .writeback_max_vscl_taps = 1, 347 .dppclk_delay_subtotal = 46, 348 .dppclk_delay_scl = 50, 349 .dppclk_delay_scl_lb_only = 16, 350 .dppclk_delay_cnvc_formatter = 27, 351 .dppclk_delay_cnvc_cursor = 6, 352 .dispclk_delay_subtotal = 119, 353 .dynamic_metadata_vm_enabled = false, 354 .odm_combine_4to1_supported = false, 355 .dcc_supported = true, 356 }; 357 358 struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = { 359 /*TODO: correct dispclk/dppclk voltage level determination*/ 360 .clock_limits = { 361 { 362 .state = 0, 363 .dispclk_mhz = 556.0, 364 .dppclk_mhz = 556.0, 365 .phyclk_mhz = 600.0, 366 .phyclk_d18_mhz = 445.0, 367 .dscclk_mhz = 186.0, 368 .dtbclk_mhz = 625.0, 369 }, 370 { 371 .state = 1, 372 .dispclk_mhz = 625.0, 373 .dppclk_mhz = 625.0, 374 .phyclk_mhz = 810.0, 375 .phyclk_d18_mhz = 667.0, 376 .dscclk_mhz = 209.0, 377 .dtbclk_mhz = 625.0, 378 }, 379 { 380 .state = 2, 381 .dispclk_mhz = 625.0, 382 .dppclk_mhz = 625.0, 383 .phyclk_mhz = 810.0, 384 .phyclk_d18_mhz = 667.0, 385 .dscclk_mhz = 209.0, 386 .dtbclk_mhz = 625.0, 387 }, 388 { 389 .state = 3, 390 .dispclk_mhz = 1112.0, 391 .dppclk_mhz = 1112.0, 392 .phyclk_mhz = 810.0, 393 .phyclk_d18_mhz = 667.0, 394 .dscclk_mhz = 371.0, 395 .dtbclk_mhz = 625.0, 396 }, 397 { 398 .state = 4, 399 .dispclk_mhz = 1250.0, 400 .dppclk_mhz = 1250.0, 401 .phyclk_mhz = 810.0, 402 .phyclk_d18_mhz = 667.0, 403 .dscclk_mhz = 417.0, 404 .dtbclk_mhz = 625.0, 405 }, 406 }, 407 .num_states = 5, 408 .sr_exit_time_us = 9.0, 409 .sr_enter_plus_exit_time_us = 11.0, 410 .sr_exit_z8_time_us = 442.0, 411 .sr_enter_plus_exit_z8_time_us = 560.0, 412 .writeback_latency_us = 12.0, 413 .dram_channel_width_bytes = 4, 414 .round_trip_ping_latency_dcfclk_cycles = 106, 415 .urgent_latency_pixel_data_only_us = 4.0, 416 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 417 .urgent_latency_vm_data_only_us = 4.0, 418 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 419 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 420 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 421 .pct_ideal_sdp_bw_after_urgent = 80.0, 422 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 423 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 424 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 425 .max_avg_sdp_bw_use_normal_percent = 60.0, 426 .max_avg_dram_bw_use_normal_percent = 60.0, 427 .fabric_datapath_to_dcn_data_return_bytes = 32, 428 .return_bus_width_bytes = 64, 429 .downspread_percent = 0.38, 430 .dcn_downspread_percent = 0.5, 431 .gpuvm_min_page_size_bytes = 4096, 432 .hostvm_min_page_size_bytes = 4096, 433 .do_urgent_latency_adjustment = false, 434 .urgent_latency_adjustment_fabric_clock_component_us = 0, 435 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 436 }; 437 438 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 439 int pipe_cnt) 440 { 441 dc_assert_fp_enabled(); 442 443 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 444 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 445 } 446 447 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 448 { 449 dc_assert_fp_enabled(); 450 451 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 452 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 453 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 454 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 455 } 456 } 457 458 void dcn31_calculate_wm_and_dlg_fp( 459 struct dc *dc, struct dc_state *context, 460 display_e2e_pipe_params_st *pipes, 461 int pipe_cnt, 462 int vlevel) 463 { 464 int i, pipe_idx; 465 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 466 467 dc_assert_fp_enabled(); 468 469 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 470 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 471 472 /* We don't recalculate clocks for 0 pipe configs, which can block 473 * S0i3 as high clocks will block low power states 474 * Override any clocks that can block S0i3 to min here 475 */ 476 if (pipe_cnt == 0) { 477 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 478 return; 479 } 480 481 pipes[0].clks_cfg.voltage = vlevel; 482 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 483 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 484 485 #if 0 // TODO 486 /* Set B: 487 * TODO 488 */ 489 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 490 if (vlevel == 0) { 491 pipes[0].clks_cfg.voltage = 1; 492 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 493 } 494 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 495 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 496 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 497 } 498 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 499 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 500 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 501 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 502 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 503 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 504 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 505 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 506 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 507 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 508 509 pipes[0].clks_cfg.voltage = vlevel; 510 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 511 512 /* Set C: 513 * TODO 514 */ 515 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 516 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 517 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 518 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 519 } 520 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 521 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 522 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 523 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 524 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 525 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 526 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 527 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 528 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 529 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 530 531 /* Set D: 532 * TODO 533 */ 534 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 535 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 536 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 537 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 538 } 539 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 540 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 541 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 542 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 543 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 544 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 545 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 546 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 547 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 548 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 549 #endif 550 551 /* Set A: 552 * All clocks min required 553 * 554 * Set A calculated last so that following calculations are based on Set A 555 */ 556 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 557 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 558 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 559 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 560 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 561 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 562 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 563 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 564 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 565 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 566 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 567 /* TODO: remove: */ 568 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 569 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 570 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 571 /* end remove*/ 572 573 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 574 if (!context->res_ctx.pipe_ctx[i].stream) 575 continue; 576 577 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 578 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 579 580 if (dc->config.forced_clocks || dc->debug.max_disp_clk) { 581 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 582 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 583 } 584 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 585 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 586 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 587 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 588 589 pipe_idx++; 590 } 591 592 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 593 } 594 595 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 596 { 597 struct clk_limit_table *clk_table = &bw_params->clk_table; 598 unsigned int i, closest_clk_lvl; 599 int j; 600 601 dc_assert_fp_enabled(); 602 603 memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits, 604 sizeof(dcn3_1_soc.clock_limits)); 605 606 // Default clock levels are used for diags, which may lead to overclocking. 607 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 608 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 609 610 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 611 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; 612 dcn3_1_soc.num_chans = bw_params->num_channels; 613 614 ASSERT(clk_table->num_entries); 615 616 /* Prepass to find max clocks independent of voltage level. */ 617 for (i = 0; i < clk_table->num_entries; ++i) { 618 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 619 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 620 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 621 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 622 } 623 624 for (i = 0; i < clk_table->num_entries; i++) { 625 /* loop backwards*/ 626 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 627 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 628 closest_clk_lvl = j; 629 break; 630 } 631 } 632 633 dcn3_1_soc._clock_tmp[i].state = i; 634 635 /* Clocks dependent on voltage level. */ 636 dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 637 dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 638 dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 639 dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 640 641 /* Clocks independent of voltage level. */ 642 dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 643 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 644 645 dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 646 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 647 648 dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 649 dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 650 dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 651 dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 652 dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 653 } 654 if (clk_table->num_entries) { 655 dcn3_1_soc.num_states = clk_table->num_entries; 656 } 657 } 658 659 memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp, 660 sizeof(dcn3_1_soc.clock_limits)); 661 662 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 663 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 664 665 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 666 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); 667 else 668 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); 669 } 670 671 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 672 { 673 struct clk_limit_table *clk_table = &bw_params->clk_table; 674 int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; 675 676 dc_assert_fp_enabled(); 677 678 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 679 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; 680 dcn3_15_soc.num_chans = bw_params->num_channels; 681 682 ASSERT(clk_table->num_entries); 683 684 /* Setup soc to always use max dispclk/dppclk to avoid odm-to-lower-voltage */ 685 for (i = 0; i < clk_table->num_entries; ++i) { 686 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 687 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 688 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 689 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 690 } 691 692 for (i = 0; i < clk_table->num_entries; i++) { 693 dcn3_15_soc.clock_limits[i].state = i; 694 695 /* Clocks dependent on voltage level. */ 696 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 697 dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 698 dcn3_15_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 699 dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 700 701 /* These aren't actually read from smu, but rather set in clk_mgr defaults */ 702 dcn3_15_soc.clock_limits[i].dtbclk_mhz = clk_table->entries[i].dtbclk_mhz; 703 dcn3_15_soc.clock_limits[i].phyclk_d18_mhz = clk_table->entries[i].phyclk_d18_mhz; 704 dcn3_15_soc.clock_limits[i].phyclk_mhz = clk_table->entries[i].phyclk_mhz; 705 706 /* Clocks independent of voltage level. */ 707 dcn3_15_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 708 dcn3_15_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 709 dcn3_15_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3.0; 710 } 711 dcn3_15_soc.num_states = clk_table->num_entries; 712 713 714 /* Set vco to max_dispclk * 2 to make sure the highest dispclk is always available for dml calcs, 715 * no impact outside of dml validation 716 */ 717 dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 718 719 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 720 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31); 721 else 722 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA); 723 } 724 725 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 726 { 727 struct clk_limit_table *clk_table = &bw_params->clk_table; 728 unsigned int i, closest_clk_lvl; 729 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 730 int j; 731 732 dc_assert_fp_enabled(); 733 734 memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits, 735 sizeof(dcn3_16_soc.clock_limits)); 736 737 // Default clock levels are used for diags, which may lead to overclocking. 738 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 739 740 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 741 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; 742 dcn3_16_soc.num_chans = bw_params->num_channels; 743 744 ASSERT(clk_table->num_entries); 745 746 /* Prepass to find max clocks independent of voltage level. */ 747 for (i = 0; i < clk_table->num_entries; ++i) { 748 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 749 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 750 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 751 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 752 } 753 754 for (i = 0; i < clk_table->num_entries; i++) { 755 /* loop backwards*/ 756 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { 757 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 758 closest_clk_lvl = j; 759 break; 760 } 761 } 762 // Ported from DCN315 763 if (clk_table->num_entries == 1) { 764 /*smu gives one DPM level, let's take the highest one*/ 765 closest_clk_lvl = dcn3_16_soc.num_states - 1; 766 } 767 768 dcn3_16_soc._clock_tmp[i].state = i; 769 770 /* Clocks dependent on voltage level. */ 771 dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 772 if (clk_table->num_entries == 1 && 773 dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 774 /*SMU fix not released yet*/ 775 dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 776 } 777 dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 778 dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 779 dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 780 781 /* Clocks independent of voltage level. */ 782 dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 783 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 784 785 dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 786 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 787 788 dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 789 dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 790 dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 791 dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 792 dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 793 } 794 if (clk_table->num_entries) { 795 dcn3_16_soc.num_states = clk_table->num_entries; 796 } 797 } 798 799 memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp, 800 sizeof(dcn3_16_soc.clock_limits)); 801 802 if (max_dispclk_mhz) { 803 dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 804 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 805 } 806 807 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 808 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31); 809 else 810 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA); 811 } 812