1*31484207SQingqing Zhuo /* 2*31484207SQingqing Zhuo * Copyright 2019-2021 Advanced Micro Devices, Inc. 3*31484207SQingqing Zhuo * 4*31484207SQingqing Zhuo * Permission is hereby granted, free of charge, to any person obtaining a 5*31484207SQingqing Zhuo * copy of this software and associated documentation files (the "Software"), 6*31484207SQingqing Zhuo * to deal in the Software without restriction, including without limitation 7*31484207SQingqing Zhuo * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*31484207SQingqing Zhuo * and/or sell copies of the Software, and to permit persons to whom the 9*31484207SQingqing Zhuo * Software is furnished to do so, subject to the following conditions: 10*31484207SQingqing Zhuo * 11*31484207SQingqing Zhuo * The above copyright notice and this permission notice shall be included in 12*31484207SQingqing Zhuo * all copies or substantial portions of the Software. 13*31484207SQingqing Zhuo * 14*31484207SQingqing Zhuo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*31484207SQingqing Zhuo * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*31484207SQingqing Zhuo * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*31484207SQingqing Zhuo * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*31484207SQingqing Zhuo * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*31484207SQingqing Zhuo * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*31484207SQingqing Zhuo * OTHER DEALINGS IN THE SOFTWARE. 21*31484207SQingqing Zhuo * 22*31484207SQingqing Zhuo * Authors: AMD 23*31484207SQingqing Zhuo * 24*31484207SQingqing Zhuo */ 25*31484207SQingqing Zhuo 26*31484207SQingqing Zhuo #ifndef __DCN301_FPU_H__ 27*31484207SQingqing Zhuo #define __DCN301_FPU_H__ 28*31484207SQingqing Zhuo 29*31484207SQingqing Zhuo void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 30*31484207SQingqing Zhuo 31*31484207SQingqing Zhuo void dcn301_fpu_set_wm_ranges(int i, 32*31484207SQingqing Zhuo struct pp_smu_wm_range_sets *ranges, 33*31484207SQingqing Zhuo struct _vcs_dpi_soc_bounding_box_st *loaded_bb); 34*31484207SQingqing Zhuo 35*31484207SQingqing Zhuo void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info); 36*31484207SQingqing Zhuo 37*31484207SQingqing Zhuo void dcn301_calculate_wm_and_dlg(struct dc *dc, 38*31484207SQingqing Zhuo struct dc_state *context, 39*31484207SQingqing Zhuo display_e2e_pipe_params_st *pipes, 40*31484207SQingqing Zhuo int pipe_cnt, 41*31484207SQingqing Zhuo int vlevel_req); 42*31484207SQingqing Zhuo #endif /* __DCN301_FPU_H__*/ 43