1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../display_mode_lib.h" 27 #include "../display_mode_vba.h" 28 #include "display_rq_dlg_calc_20v2.h" 29 30 // Function: dml20v2_rq_dlg_get_rq_params 31 // Calculate requestor related parameters that register definition agnostic 32 // (i.e. this layer does try to separate real values from register definition) 33 // Input: 34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) 35 // Output: 36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) 37 // 38 static void dml20v2_rq_dlg_get_rq_params( 39 struct display_mode_lib *mode_lib, 40 display_rq_params_st * rq_param, 41 const display_pipe_source_params_st pipe_src_param); 42 43 // Function: dml20v2_rq_dlg_get_dlg_params 44 // Calculate deadline related parameters 45 // 46 static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 47 const display_e2e_pipe_params_st *e2e_pipe_param, 48 const unsigned int num_pipes, 49 const unsigned int pipe_idx, 50 display_dlg_regs_st *disp_dlg_regs, 51 display_ttu_regs_st *disp_ttu_regs, 52 const display_rq_dlg_params_st rq_dlg_param, 53 const display_dlg_sys_params_st dlg_sys_param, 54 const bool cstate_en, 55 const bool pstate_en); 56 /* 57 * NOTE: 58 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 59 * 60 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 61 * ways. Unless there is something clearly wrong with it the code should 62 * remain as-is as it provides us with a guarantee from HW that it is correct. 63 */ 64 65 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 66 double *refcyc_per_req_delivery_pre_cur, 67 double *refcyc_per_req_delivery_cur, 68 double refclk_freq_in_mhz, 69 double ref_freq_to_pix_freq, 70 double hscale_pixel_rate_l, 71 double hscl_ratio, 72 double vratio_pre_l, 73 double vratio_l, 74 unsigned int cur_width, 75 enum cursor_bpp cur_bpp); 76 77 #include "../dml_inline_defs.h" 78 79 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 80 { 81 unsigned int ret_val = 0; 82 83 if (source_format == dm_444_16) { 84 if (!is_chroma) 85 ret_val = 2; 86 } else if (source_format == dm_444_32) { 87 if (!is_chroma) 88 ret_val = 4; 89 } else if (source_format == dm_444_64) { 90 if (!is_chroma) 91 ret_val = 8; 92 } else if (source_format == dm_420_8) { 93 if (is_chroma) 94 ret_val = 2; 95 else 96 ret_val = 1; 97 } else if (source_format == dm_420_10) { 98 if (is_chroma) 99 ret_val = 4; 100 else 101 ret_val = 2; 102 } else if (source_format == dm_444_8) { 103 ret_val = 1; 104 } 105 return ret_val; 106 } 107 108 static bool is_dual_plane(enum source_format_class source_format) 109 { 110 bool ret_val = false; 111 112 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 113 ret_val = true; 114 115 return ret_val; 116 } 117 118 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, 119 double refclk_freq_in_mhz, 120 double pclk_freq_in_mhz, 121 bool odm_combine, 122 unsigned int recout_width, 123 unsigned int hactive, 124 double vratio, 125 double hscale_pixel_rate, 126 unsigned int delivery_width, 127 unsigned int req_per_swath_ub) 128 { 129 double refcyc_per_delivery = 0.0; 130 131 if (vratio <= 1.0) { 132 if (odm_combine) 133 refcyc_per_delivery = (double) refclk_freq_in_mhz 134 * dml_min((double) recout_width, (double) hactive / 2.0) 135 / pclk_freq_in_mhz / (double) req_per_swath_ub; 136 else 137 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 138 / pclk_freq_in_mhz / (double) req_per_swath_ub; 139 } else { 140 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 141 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 142 } 143 144 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 145 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 146 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 147 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 148 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 149 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 150 151 return refcyc_per_delivery; 152 153 } 154 155 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 156 { 157 if (tile_size == dm_256k_tile) 158 return (256 * 1024); 159 else if (tile_size == dm_64k_tile) 160 return (64 * 1024); 161 else 162 return (4 * 1024); 163 } 164 165 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 166 display_data_rq_regs_st *rq_regs, 167 const display_data_rq_sizing_params_st rq_sizing) 168 { 169 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 170 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 171 172 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; 173 174 if (rq_sizing.min_chunk_bytes == 0) 175 rq_regs->min_chunk_size = 0; 176 else 177 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; 178 179 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; 180 if (rq_sizing.min_meta_chunk_bytes == 0) 181 rq_regs->min_meta_chunk_size = 0; 182 else 183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; 184 185 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; 186 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; 187 } 188 189 static void extract_rq_regs(struct display_mode_lib *mode_lib, 190 display_rq_regs_st *rq_regs, 191 const display_rq_params_st rq_param) 192 { 193 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 194 unsigned int detile_buf_plane1_addr = 0; 195 196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); 197 198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 199 1) - 3; 200 201 if (rq_param.yuv420) { 202 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); 203 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 204 1) - 3; 205 } 206 207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 208 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 209 210 // TODO: take the max between luma, chroma chunk size? 211 // okay for now, as we are setting chunk_bytes to 8kb anyways 212 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 213 rq_regs->drq_expansion_mode = 0; 214 } else { 215 rq_regs->drq_expansion_mode = 2; 216 } 217 rq_regs->prq_expansion_mode = 1; 218 rq_regs->mrq_expansion_mode = 1; 219 rq_regs->crq_expansion_mode = 1; 220 221 if (rq_param.yuv420) { 222 if ((double) rq_param.misc.rq_l.stored_swath_bytes 223 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 224 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 225 } else { 226 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 227 256, 228 0) / 64.0; // 2/3 to chroma 229 } 230 } 231 rq_regs->plane1_base_address = detile_buf_plane1_addr; 232 } 233 234 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 235 display_rq_params_st *rq_param, 236 const display_pipe_source_params_st pipe_src_param) 237 { 238 unsigned int total_swath_bytes = 0; 239 unsigned int swath_bytes_l = 0; 240 unsigned int swath_bytes_c = 0; 241 unsigned int full_swath_bytes_packed_l = 0; 242 unsigned int full_swath_bytes_packed_c = 0; 243 bool req128_l = false; 244 bool req128_c = false; 245 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 246 bool surf_vert = (pipe_src_param.source_scan == dm_vert); 247 unsigned int log2_swath_height_l = 0; 248 unsigned int log2_swath_height_c = 0; 249 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 250 251 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 252 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 253 254 if (rq_param->yuv420_10bpc) { 255 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 256 256, 257 1) + 256; 258 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 259 256, 260 1) + 256; 261 } 262 263 if (rq_param->yuv420) { 264 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 265 266 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 267 req128_l = false; 268 req128_c = false; 269 swath_bytes_l = full_swath_bytes_packed_l; 270 swath_bytes_c = full_swath_bytes_packed_c; 271 } else { //128b request (for luma only for yuv420 8bpc) 272 req128_l = true; 273 req128_c = false; 274 swath_bytes_l = full_swath_bytes_packed_l / 2; 275 swath_bytes_c = full_swath_bytes_packed_c; 276 } 277 // Note: assumption, the config that pass in will fit into 278 // the detiled buffer. 279 } else { 280 total_swath_bytes = 2 * full_swath_bytes_packed_l; 281 282 if (total_swath_bytes <= detile_buf_size_in_bytes) 283 req128_l = false; 284 else 285 req128_l = true; 286 287 swath_bytes_l = total_swath_bytes; 288 swath_bytes_c = 0; 289 } 290 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 291 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 292 293 if (surf_linear) { 294 log2_swath_height_l = 0; 295 log2_swath_height_c = 0; 296 } else if (!surf_vert) { 297 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; 298 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; 299 } else { 300 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; 301 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; 302 } 303 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 304 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 305 306 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 307 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 308 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 309 __func__, 310 full_swath_bytes_packed_l); 311 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 312 __func__, 313 full_swath_bytes_packed_c); 314 } 315 316 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, 317 display_data_rq_dlg_params_st *rq_dlg_param, 318 display_data_rq_misc_params_st *rq_misc_param, 319 display_data_rq_sizing_params_st *rq_sizing_param, 320 unsigned int vp_width, 321 unsigned int vp_height, 322 unsigned int data_pitch, 323 unsigned int meta_pitch, 324 unsigned int source_format, 325 unsigned int tiling, 326 unsigned int macro_tile_size, 327 unsigned int source_scan, 328 unsigned int is_chroma) 329 { 330 bool surf_linear = (tiling == dm_sw_linear); 331 bool surf_vert = (source_scan == dm_vert); 332 333 unsigned int bytes_per_element; 334 unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), 335 false); 336 unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), 337 true); 338 339 unsigned int blk256_width = 0; 340 unsigned int blk256_height = 0; 341 342 unsigned int blk256_width_y = 0; 343 unsigned int blk256_height_y = 0; 344 unsigned int blk256_width_c = 0; 345 unsigned int blk256_height_c = 0; 346 unsigned int log2_bytes_per_element; 347 unsigned int log2_blk256_width; 348 unsigned int log2_blk256_height; 349 unsigned int blk_bytes; 350 unsigned int log2_blk_bytes; 351 unsigned int log2_blk_height; 352 unsigned int log2_blk_width; 353 unsigned int log2_meta_req_bytes; 354 unsigned int log2_meta_req_height; 355 unsigned int log2_meta_req_width; 356 unsigned int meta_req_width; 357 unsigned int meta_req_height; 358 unsigned int log2_meta_row_height; 359 unsigned int meta_row_width_ub; 360 unsigned int log2_meta_chunk_bytes; 361 unsigned int log2_meta_chunk_height; 362 363 //full sized meta chunk width in unit of data elements 364 unsigned int log2_meta_chunk_width; 365 unsigned int log2_min_meta_chunk_bytes; 366 unsigned int min_meta_chunk_width; 367 unsigned int meta_chunk_width; 368 unsigned int meta_chunk_per_row_int; 369 unsigned int meta_row_remainder; 370 unsigned int meta_chunk_threshold; 371 unsigned int meta_blk_bytes; 372 unsigned int meta_blk_height; 373 unsigned int meta_blk_width; 374 unsigned int meta_surface_bytes; 375 unsigned int vmpg_bytes; 376 unsigned int meta_pte_req_per_frame_ub; 377 unsigned int meta_pte_bytes_per_frame_ub; 378 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 379 const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 380 const unsigned int pde_proc_buffer_size_64k_reqs = 381 mode_lib->ip.pde_proc_buffer_size_64k_reqs; 382 383 unsigned int log2_vmpg_height = 0; 384 unsigned int log2_vmpg_width = 0; 385 unsigned int log2_dpte_req_height_ptes = 0; 386 unsigned int log2_dpte_req_height = 0; 387 unsigned int log2_dpte_req_width = 0; 388 unsigned int log2_dpte_row_height_linear = 0; 389 unsigned int log2_dpte_row_height = 0; 390 unsigned int log2_dpte_group_width = 0; 391 unsigned int dpte_row_width_ub = 0; 392 unsigned int dpte_req_height = 0; 393 unsigned int dpte_req_width = 0; 394 unsigned int dpte_group_width = 0; 395 unsigned int log2_dpte_group_bytes = 0; 396 unsigned int log2_dpte_group_length = 0; 397 unsigned int pde_buf_entries; 398 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); 399 400 Calculate256BBlockSizes((enum source_format_class)(source_format), 401 (enum dm_swizzle_mode)(tiling), 402 bytes_per_element_y, 403 bytes_per_element_c, 404 &blk256_height_y, 405 &blk256_height_c, 406 &blk256_width_y, 407 &blk256_width_c); 408 409 if (!is_chroma) { 410 blk256_width = blk256_width_y; 411 blk256_height = blk256_height_y; 412 bytes_per_element = bytes_per_element_y; 413 } else { 414 blk256_width = blk256_width_c; 415 blk256_height = blk256_height_c; 416 bytes_per_element = bytes_per_element_c; 417 } 418 419 log2_bytes_per_element = dml_log2(bytes_per_element); 420 421 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 422 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 423 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 424 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 425 426 log2_blk256_width = dml_log2((double) blk256_width); 427 log2_blk256_height = dml_log2((double) blk256_height); 428 blk_bytes = surf_linear ? 429 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 430 log2_blk_bytes = dml_log2((double) blk_bytes); 431 log2_blk_height = 0; 432 log2_blk_width = 0; 433 434 // remember log rule 435 // "+" in log is multiply 436 // "-" in log is divide 437 // "/2" is like square root 438 // blk is vertical biased 439 if (tiling != dm_sw_linear) 440 log2_blk_height = log2_blk256_height 441 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 442 else 443 log2_blk_height = 0; // blk height of 1 444 445 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 446 447 if (!surf_vert) { 448 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 449 + blk256_width; 450 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 451 } else { 452 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) 453 + blk256_height; 454 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 455 } 456 457 if (!surf_vert) 458 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 459 * bytes_per_element; 460 else 461 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 462 * bytes_per_element; 463 464 rq_misc_param->blk256_height = blk256_height; 465 rq_misc_param->blk256_width = blk256_width; 466 467 // ------- 468 // meta 469 // ------- 470 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 471 472 // each 64b meta request for dcn is 8x8 meta elements and 473 // a meta element covers one 256b block of the the data surface. 474 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 475 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 476 - log2_meta_req_height; 477 meta_req_width = 1 << log2_meta_req_width; 478 meta_req_height = 1 << log2_meta_req_height; 479 log2_meta_row_height = 0; 480 meta_row_width_ub = 0; 481 482 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 483 // calculate upper bound of the meta_row_width 484 if (!surf_vert) { 485 log2_meta_row_height = log2_meta_req_height; 486 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 487 + meta_req_width; 488 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 489 } else { 490 log2_meta_row_height = log2_meta_req_width; 491 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 492 + meta_req_height; 493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 494 } 495 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 496 497 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 498 499 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 500 log2_meta_chunk_height = log2_meta_row_height; 501 502 //full sized meta chunk width in unit of data elements 503 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 504 - log2_meta_chunk_height; 505 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 506 min_meta_chunk_width = 1 507 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 508 - log2_meta_chunk_height); 509 meta_chunk_width = 1 << log2_meta_chunk_width; 510 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 511 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 512 meta_chunk_threshold = 0; 513 meta_blk_bytes = 4096; 514 meta_blk_height = blk256_height * 64; 515 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 516 meta_surface_bytes = meta_pitch 517 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) 518 * bytes_per_element / 256; 519 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 520 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 521 8 * vmpg_bytes, 522 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 523 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 524 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 525 526 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 527 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 528 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 529 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 530 __func__, 531 meta_pte_req_per_frame_ub); 532 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 533 __func__, 534 meta_pte_bytes_per_frame_ub); 535 536 if (!surf_vert) 537 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 538 else 539 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 540 541 if (meta_row_remainder <= meta_chunk_threshold) 542 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 543 else 544 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 545 546 // ------ 547 // dpte 548 // ------ 549 if (surf_linear) { 550 log2_vmpg_height = 0; // one line high 551 } else { 552 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 553 } 554 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 555 556 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 557 if (surf_linear) { //one 64B PTE request returns 8 PTEs 558 log2_dpte_req_height_ptes = 0; 559 log2_dpte_req_width = log2_vmpg_width + 3; 560 log2_dpte_req_height = 0; 561 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 562 //one 64B req gives 8x1 PTEs for 4KB tile 563 log2_dpte_req_height_ptes = 0; 564 log2_dpte_req_width = log2_blk_width + 3; 565 log2_dpte_req_height = log2_blk_height + 0; 566 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 567 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 568 log2_dpte_req_height_ptes = 4; 569 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 570 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 571 } else { //64KB page size and must 64KB tile block 572 //one 64B req gives 8x1 PTEs for 64KB tile 573 log2_dpte_req_height_ptes = 0; 574 log2_dpte_req_width = log2_blk_width + 3; 575 log2_dpte_req_height = log2_blk_height + 0; 576 } 577 578 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 579 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 580 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 581 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 582 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 583 dpte_req_height = 1 << log2_dpte_req_height; 584 dpte_req_width = 1 << log2_dpte_req_width; 585 586 // calculate pitch dpte row buffer can hold 587 // round the result down to a power of two. 588 pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; 589 if (surf_linear) { 590 unsigned int dpte_row_height; 591 592 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries 593 / bytes_per_element, 594 dpte_buf_in_pte_reqs 595 * dpte_req_width) 596 / data_pitch), 597 1); 598 599 ASSERT(log2_dpte_row_height_linear >= 3); 600 601 if (log2_dpte_row_height_linear > 7) 602 log2_dpte_row_height_linear = 7; 603 604 log2_dpte_row_height = log2_dpte_row_height_linear; 605 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 606 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 607 dpte_row_height = 1 << log2_dpte_row_height; 608 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, 609 dpte_req_width, 610 1) + dpte_req_width; 611 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 612 } else { 613 // the upper bound of the dpte_row_width without dependency on viewport position follows. 614 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 615 if (!surf_vert) { 616 log2_dpte_row_height = log2_dpte_req_height; 617 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 618 + dpte_req_width; 619 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 620 } else { 621 log2_dpte_row_height = 622 (log2_blk_width < log2_dpte_req_width) ? 623 log2_blk_width : log2_dpte_req_width; 624 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 625 + dpte_req_height; 626 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 627 } 628 } 629 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 630 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 631 else 632 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 633 634 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 635 636 // the dpte_group_bytes is reduced for the specific case of vertical 637 // access of a tile surface that has dpte request of 8x1 ptes. 638 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group 639 rq_sizing_param->dpte_group_bytes = 512; 640 else 641 //full size 642 rq_sizing_param->dpte_group_bytes = 2048; 643 644 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 645 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 646 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 647 648 // full sized data pte group width in elements 649 if (!surf_vert) 650 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 651 else 652 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 653 654 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 655 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 656 log2_dpte_group_width = log2_dpte_group_width - 1; 657 658 dpte_group_width = 1 << log2_dpte_group_width; 659 660 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 661 // the upper bound for the dpte groups per row is as follows. 662 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 663 1); 664 } 665 666 static void get_surf_rq_param(struct display_mode_lib *mode_lib, 667 display_data_rq_sizing_params_st *rq_sizing_param, 668 display_data_rq_dlg_params_st *rq_dlg_param, 669 display_data_rq_misc_params_st *rq_misc_param, 670 const display_pipe_source_params_st pipe_src_param, 671 bool is_chroma) 672 { 673 bool mode_422 = false; 674 unsigned int vp_width = 0; 675 unsigned int vp_height = 0; 676 unsigned int data_pitch = 0; 677 unsigned int meta_pitch = 0; 678 unsigned int ppe = mode_422 ? 2 : 1; 679 680 // TODO check if ppe apply for both luma and chroma in 422 case 681 if (is_chroma) { 682 vp_width = pipe_src_param.viewport_width_c / ppe; 683 vp_height = pipe_src_param.viewport_height_c; 684 data_pitch = pipe_src_param.data_pitch_c; 685 meta_pitch = pipe_src_param.meta_pitch_c; 686 } else { 687 vp_width = pipe_src_param.viewport_width / ppe; 688 vp_height = pipe_src_param.viewport_height; 689 data_pitch = pipe_src_param.data_pitch; 690 meta_pitch = pipe_src_param.meta_pitch; 691 } 692 693 rq_sizing_param->chunk_bytes = 8192; 694 695 if (rq_sizing_param->chunk_bytes == 64 * 1024) 696 rq_sizing_param->min_chunk_bytes = 0; 697 else 698 rq_sizing_param->min_chunk_bytes = 1024; 699 700 rq_sizing_param->meta_chunk_bytes = 2048; 701 rq_sizing_param->min_meta_chunk_bytes = 256; 702 703 rq_sizing_param->mpte_group_bytes = 2048; 704 705 get_meta_and_pte_attr(mode_lib, 706 rq_dlg_param, 707 rq_misc_param, 708 rq_sizing_param, 709 vp_width, 710 vp_height, 711 data_pitch, 712 meta_pitch, 713 pipe_src_param.source_format, 714 pipe_src_param.sw_mode, 715 pipe_src_param.macro_tile_size, 716 pipe_src_param.source_scan, 717 is_chroma); 718 } 719 720 static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 721 display_rq_params_st *rq_param, 722 const display_pipe_source_params_st pipe_src_param) 723 { 724 // get param for luma surface 725 rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 726 || pipe_src_param.source_format == dm_420_10; 727 rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 728 729 get_surf_rq_param(mode_lib, 730 &(rq_param->sizing.rq_l), 731 &(rq_param->dlg.rq_l), 732 &(rq_param->misc.rq_l), 733 pipe_src_param, 734 0); 735 736 if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { 737 // get param for chroma surface 738 get_surf_rq_param(mode_lib, 739 &(rq_param->sizing.rq_c), 740 &(rq_param->dlg.rq_c), 741 &(rq_param->misc.rq_c), 742 pipe_src_param, 743 1); 744 } 745 746 // calculate how to split the det buffer space between luma and chroma 747 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 748 print__rq_params_st(mode_lib, *rq_param); 749 } 750 751 void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 752 display_rq_regs_st *rq_regs, 753 const display_pipe_params_st pipe_param) 754 { 755 display_rq_params_st rq_param = {0}; 756 757 memset(rq_regs, 0, sizeof(*rq_regs)); 758 dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src); 759 extract_rq_regs(mode_lib, rq_regs, rq_param); 760 761 print__rq_regs_st(mode_lib, *rq_regs); 762 } 763 764 // Note: currently taken in as is. 765 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 766 static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 767 const display_e2e_pipe_params_st *e2e_pipe_param, 768 const unsigned int num_pipes, 769 const unsigned int pipe_idx, 770 display_dlg_regs_st *disp_dlg_regs, 771 display_ttu_regs_st *disp_ttu_regs, 772 const display_rq_dlg_params_st rq_dlg_param, 773 const display_dlg_sys_params_st dlg_sys_param, 774 const bool cstate_en, 775 const bool pstate_en) 776 { 777 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 778 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 779 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 781 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 782 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 783 784 // ------------------------- 785 // Section 1.15.2.1: OTG dependent Params 786 // ------------------------- 787 // Timing 788 unsigned int htotal = dst->htotal; 789 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove 790 unsigned int hblank_end = dst->hblank_end; 791 unsigned int vblank_start = dst->vblank_start; 792 unsigned int vblank_end = dst->vblank_end; 793 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 794 795 double dppclk_freq_in_mhz = clks->dppclk_mhz; 796 double dispclk_freq_in_mhz = clks->dispclk_mhz; 797 double refclk_freq_in_mhz = clks->refclk_mhz; 798 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 799 bool interlaced = dst->interlaced; 800 801 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 802 803 double min_dcfclk_mhz; 804 double t_calc_us; 805 double min_ttu_vblank; 806 807 double min_dst_y_ttu_vblank; 808 unsigned int dlg_vblank_start; 809 bool dual_plane; 810 bool mode_422; 811 unsigned int access_dir; 812 unsigned int vp_height_l; 813 unsigned int vp_width_l; 814 unsigned int vp_height_c; 815 unsigned int vp_width_c; 816 817 // Scaling 818 unsigned int htaps_l; 819 unsigned int htaps_c; 820 double hratio_l; 821 double hratio_c; 822 double vratio_l; 823 double vratio_c; 824 bool scl_enable; 825 826 double line_time_in_us; 827 // double vinit_l; 828 // double vinit_c; 829 // double vinit_bot_l; 830 // double vinit_bot_c; 831 832 // unsigned int swath_height_l; 833 unsigned int swath_width_ub_l; 834 // unsigned int dpte_bytes_per_row_ub_l; 835 unsigned int dpte_groups_per_row_ub_l; 836 // unsigned int meta_pte_bytes_per_frame_ub_l; 837 // unsigned int meta_bytes_per_row_ub_l; 838 839 // unsigned int swath_height_c; 840 unsigned int swath_width_ub_c; 841 // unsigned int dpte_bytes_per_row_ub_c; 842 unsigned int dpte_groups_per_row_ub_c; 843 844 unsigned int meta_chunks_per_row_ub_l; 845 unsigned int meta_chunks_per_row_ub_c; 846 unsigned int vupdate_offset; 847 unsigned int vupdate_width; 848 unsigned int vready_offset; 849 850 unsigned int dppclk_delay_subtotal; 851 unsigned int dispclk_delay_subtotal; 852 unsigned int pixel_rate_delay_subtotal; 853 854 unsigned int vstartup_start; 855 unsigned int dst_x_after_scaler; 856 unsigned int dst_y_after_scaler; 857 double line_wait; 858 double dst_y_prefetch; 859 double dst_y_per_vm_vblank; 860 double dst_y_per_row_vblank; 861 double dst_y_per_vm_flip; 862 double dst_y_per_row_flip; 863 double min_dst_y_per_vm_vblank; 864 double min_dst_y_per_row_vblank; 865 double lsw; 866 double vratio_pre_l; 867 double vratio_pre_c; 868 unsigned int req_per_swath_ub_l; 869 unsigned int req_per_swath_ub_c; 870 unsigned int meta_row_height_l; 871 unsigned int meta_row_height_c; 872 unsigned int swath_width_pixels_ub_l; 873 unsigned int swath_width_pixels_ub_c; 874 unsigned int scaler_rec_in_width_l; 875 unsigned int scaler_rec_in_width_c; 876 unsigned int dpte_row_height_l; 877 unsigned int dpte_row_height_c; 878 double hscale_pixel_rate_l; 879 double hscale_pixel_rate_c; 880 double min_hratio_fact_l; 881 double min_hratio_fact_c; 882 double refcyc_per_line_delivery_pre_l; 883 double refcyc_per_line_delivery_pre_c; 884 double refcyc_per_line_delivery_l; 885 double refcyc_per_line_delivery_c; 886 887 double refcyc_per_req_delivery_pre_l; 888 double refcyc_per_req_delivery_pre_c; 889 double refcyc_per_req_delivery_l; 890 double refcyc_per_req_delivery_c; 891 892 unsigned int full_recout_width; 893 double refcyc_per_req_delivery_pre_cur0; 894 double refcyc_per_req_delivery_cur0; 895 double refcyc_per_req_delivery_pre_cur1; 896 double refcyc_per_req_delivery_cur1; 897 898 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 899 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 900 901 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 902 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 903 904 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 905 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 906 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 907 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 908 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 909 ASSERT(ref_freq_to_pix_freq < 4.0); 910 911 disp_dlg_regs->ref_freq_to_pix_freq = 912 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 913 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 914 * dml_pow(2, 8)); 915 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 916 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 917 * (double) ref_freq_to_pix_freq); 918 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 919 920 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 921 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 922 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 923 924 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 925 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 926 927 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start 928 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 929 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 930 931 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 932 __func__, 933 min_dcfclk_mhz); 934 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", 935 __func__, 936 min_ttu_vblank); 937 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 938 __func__, 939 min_dst_y_ttu_vblank); 940 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", 941 __func__, 942 t_calc_us); 943 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 944 __func__, 945 disp_dlg_regs->min_dst_y_next_start); 946 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 947 __func__, 948 ref_freq_to_pix_freq); 949 950 // ------------------------- 951 // Section 1.15.2.2: Prefetch, Active and TTU 952 // ------------------------- 953 // Prefetch Calc 954 // Source 955 // dcc_en = src.dcc; 956 dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); 957 mode_422 = false; // TODO 958 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 959 // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); 960 // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); 961 vp_height_l = src->viewport_height; 962 vp_width_l = src->viewport_width; 963 vp_height_c = src->viewport_height_c; 964 vp_width_c = src->viewport_width_c; 965 966 // Scaling 967 htaps_l = taps->htaps; 968 htaps_c = taps->htaps_c; 969 hratio_l = scl->hscl_ratio; 970 hratio_c = scl->hscl_ratio_c; 971 vratio_l = scl->vscl_ratio; 972 vratio_c = scl->vscl_ratio_c; 973 scl_enable = scl->scl_enable; 974 975 line_time_in_us = (htotal / pclk_freq_in_mhz); 976 // vinit_l = scl.vinit; 977 // vinit_c = scl.vinit_c; 978 // vinit_bot_l = scl.vinit_bot; 979 // vinit_bot_c = scl.vinit_bot_c; 980 981 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; 982 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 983 // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 984 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 985 // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 986 // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 987 988 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; 989 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 990 // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 991 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 992 993 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 994 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 995 vupdate_offset = dst->vupdate_offset; 996 vupdate_width = dst->vupdate_width; 997 vready_offset = dst->vready_offset; 998 999 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1000 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1001 1002 if (scl_enable) 1003 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1004 else 1005 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1006 1007 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1008 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1009 1010 if (dout->dsc_enable) { 1011 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1012 1013 dispclk_delay_subtotal += dsc_delay; 1014 } 1015 1016 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1017 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1018 1019 vstartup_start = dst->vstartup_start; 1020 if (interlaced) { 1021 if (vstartup_start / 2.0 1022 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1023 <= vblank_end / 2.0) 1024 disp_dlg_regs->vready_after_vcount0 = 1; 1025 else 1026 disp_dlg_regs->vready_after_vcount0 = 0; 1027 } else { 1028 if (vstartup_start 1029 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1030 <= vblank_end) 1031 disp_dlg_regs->vready_after_vcount0 = 1; 1032 else 1033 disp_dlg_regs->vready_after_vcount0 = 0; 1034 } 1035 1036 // TODO: Where is this coming from? 1037 if (interlaced) 1038 vstartup_start = vstartup_start / 2; 1039 1040 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1041 if (vstartup_start >= min_vblank) { 1042 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1043 __func__, 1044 vblank_start, 1045 vblank_end); 1046 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1047 __func__, 1048 vstartup_start, 1049 min_vblank); 1050 min_vblank = vstartup_start + 1; 1051 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1052 __func__, 1053 vstartup_start, 1054 min_vblank); 1055 } 1056 1057 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1058 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1059 1060 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1061 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1062 __func__, 1063 pixel_rate_delay_subtotal); 1064 dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n", 1065 __func__, 1066 dst_x_after_scaler); 1067 dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n", 1068 __func__, 1069 dst_y_after_scaler); 1070 1071 // Lwait 1072 line_wait = mode_lib->soc.urgent_latency_us; 1073 if (cstate_en) 1074 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1075 if (pstate_en) 1076 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us 1077 + mode_lib->soc.urgent_latency_us, 1078 line_wait); 1079 line_wait = line_wait / line_time_in_us; 1080 1081 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1082 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1083 1084 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, 1085 e2e_pipe_param, 1086 num_pipes, 1087 pipe_idx); 1088 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, 1089 e2e_pipe_param, 1090 num_pipes, 1091 pipe_idx); 1092 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1093 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1094 1095 min_dst_y_per_vm_vblank = 8.0; 1096 min_dst_y_per_row_vblank = 16.0; 1097 1098 // magic! 1099 if (htotal <= 75) { 1100 min_vblank = 300; 1101 min_dst_y_per_vm_vblank = 100.0; 1102 min_dst_y_per_row_vblank = 100.0; 1103 } 1104 1105 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1106 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1107 1108 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1109 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1110 1111 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1112 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1113 1114 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1115 1116 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1117 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1118 1119 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1120 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1121 1122 // Active 1123 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1124 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1125 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1126 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1127 swath_width_pixels_ub_l = 0; 1128 swath_width_pixels_ub_c = 0; 1129 scaler_rec_in_width_l = 0; 1130 scaler_rec_in_width_c = 0; 1131 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1132 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1133 1134 if (mode_422) { 1135 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element 1136 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1137 } else { 1138 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1139 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1140 } 1141 1142 hscale_pixel_rate_l = 0.; 1143 hscale_pixel_rate_c = 0.; 1144 min_hratio_fact_l = 1.0; 1145 min_hratio_fact_c = 1.0; 1146 1147 if (htaps_l <= 1) 1148 min_hratio_fact_l = 2.0; 1149 else if (htaps_l <= 6) { 1150 if ((hratio_l * 2.0) > 4.0) 1151 min_hratio_fact_l = 4.0; 1152 else 1153 min_hratio_fact_l = hratio_l * 2.0; 1154 } else { 1155 if (hratio_l > 4.0) 1156 min_hratio_fact_l = 4.0; 1157 else 1158 min_hratio_fact_l = hratio_l; 1159 } 1160 1161 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1162 1163 if (htaps_c <= 1) 1164 min_hratio_fact_c = 2.0; 1165 else if (htaps_c <= 6) { 1166 if ((hratio_c * 2.0) > 4.0) 1167 min_hratio_fact_c = 4.0; 1168 else 1169 min_hratio_fact_c = hratio_c * 2.0; 1170 } else { 1171 if (hratio_c > 4.0) 1172 min_hratio_fact_c = 4.0; 1173 else 1174 min_hratio_fact_c = hratio_c; 1175 } 1176 1177 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1178 1179 refcyc_per_line_delivery_pre_l = 0.; 1180 refcyc_per_line_delivery_pre_c = 0.; 1181 refcyc_per_line_delivery_l = 0.; 1182 refcyc_per_line_delivery_c = 0.; 1183 1184 refcyc_per_req_delivery_pre_l = 0.; 1185 refcyc_per_req_delivery_pre_c = 0.; 1186 refcyc_per_req_delivery_l = 0.; 1187 refcyc_per_req_delivery_c = 0.; 1188 1189 full_recout_width = 0; 1190 // In ODM 1191 if (src->is_hsplit) { 1192 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1193 // combine, you MUST specify the full_recout_width...according to Oswin 1194 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1195 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1196 __func__); 1197 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1198 } else 1199 full_recout_width = dst->full_recout_width; 1200 } else 1201 full_recout_width = dst->recout_width; 1202 1203 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1204 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1205 refclk_freq_in_mhz, 1206 pclk_freq_in_mhz, 1207 dst->odm_combine, 1208 full_recout_width, 1209 dst->hactive, 1210 vratio_pre_l, 1211 hscale_pixel_rate_l, 1212 swath_width_pixels_ub_l, 1213 1); // per line 1214 1215 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, 1216 refclk_freq_in_mhz, 1217 pclk_freq_in_mhz, 1218 dst->odm_combine, 1219 full_recout_width, 1220 dst->hactive, 1221 vratio_l, 1222 hscale_pixel_rate_l, 1223 swath_width_pixels_ub_l, 1224 1); // per line 1225 1226 dml_print("DML_DLG: %s: full_recout_width = %d\n", 1227 __func__, 1228 full_recout_width); 1229 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1230 __func__, 1231 hscale_pixel_rate_l); 1232 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1233 __func__, 1234 refcyc_per_line_delivery_pre_l); 1235 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1236 __func__, 1237 refcyc_per_line_delivery_l); 1238 1239 if (dual_plane) { 1240 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1241 refclk_freq_in_mhz, 1242 pclk_freq_in_mhz, 1243 dst->odm_combine, 1244 full_recout_width, 1245 dst->hactive, 1246 vratio_pre_c, 1247 hscale_pixel_rate_c, 1248 swath_width_pixels_ub_c, 1249 1); // per line 1250 1251 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, 1252 refclk_freq_in_mhz, 1253 pclk_freq_in_mhz, 1254 dst->odm_combine, 1255 full_recout_width, 1256 dst->hactive, 1257 vratio_c, 1258 hscale_pixel_rate_c, 1259 swath_width_pixels_ub_c, 1260 1); // per line 1261 1262 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1263 __func__, 1264 refcyc_per_line_delivery_pre_c); 1265 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1266 __func__, 1267 refcyc_per_line_delivery_c); 1268 } 1269 1270 // TTU - Luma / Chroma 1271 if (access_dir) { // vertical access 1272 scaler_rec_in_width_l = vp_height_l; 1273 scaler_rec_in_width_c = vp_height_c; 1274 } else { 1275 scaler_rec_in_width_l = vp_width_l; 1276 scaler_rec_in_width_c = vp_width_c; 1277 } 1278 1279 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1280 refclk_freq_in_mhz, 1281 pclk_freq_in_mhz, 1282 dst->odm_combine, 1283 full_recout_width, 1284 dst->hactive, 1285 vratio_pre_l, 1286 hscale_pixel_rate_l, 1287 scaler_rec_in_width_l, 1288 req_per_swath_ub_l); // per req 1289 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, 1290 refclk_freq_in_mhz, 1291 pclk_freq_in_mhz, 1292 dst->odm_combine, 1293 full_recout_width, 1294 dst->hactive, 1295 vratio_l, 1296 hscale_pixel_rate_l, 1297 scaler_rec_in_width_l, 1298 req_per_swath_ub_l); // per req 1299 1300 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1301 __func__, 1302 refcyc_per_req_delivery_pre_l); 1303 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1304 __func__, 1305 refcyc_per_req_delivery_l); 1306 1307 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1308 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1309 1310 if (dual_plane) { 1311 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1312 refclk_freq_in_mhz, 1313 pclk_freq_in_mhz, 1314 dst->odm_combine, 1315 full_recout_width, 1316 dst->hactive, 1317 vratio_pre_c, 1318 hscale_pixel_rate_c, 1319 scaler_rec_in_width_c, 1320 req_per_swath_ub_c); // per req 1321 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, 1322 refclk_freq_in_mhz, 1323 pclk_freq_in_mhz, 1324 dst->odm_combine, 1325 full_recout_width, 1326 dst->hactive, 1327 vratio_c, 1328 hscale_pixel_rate_c, 1329 scaler_rec_in_width_c, 1330 req_per_swath_ub_c); // per req 1331 1332 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1333 __func__, 1334 refcyc_per_req_delivery_pre_c); 1335 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1336 __func__, 1337 refcyc_per_req_delivery_c); 1338 1339 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1340 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1341 } 1342 1343 // TTU - Cursor 1344 refcyc_per_req_delivery_pre_cur0 = 0.0; 1345 refcyc_per_req_delivery_cur0 = 0.0; 1346 if (src->num_cursors > 0) { 1347 calculate_ttu_cursor(mode_lib, 1348 &refcyc_per_req_delivery_pre_cur0, 1349 &refcyc_per_req_delivery_cur0, 1350 refclk_freq_in_mhz, 1351 ref_freq_to_pix_freq, 1352 hscale_pixel_rate_l, 1353 scl->hscl_ratio, 1354 vratio_pre_l, 1355 vratio_l, 1356 src->cur0_src_width, 1357 (enum cursor_bpp)(src->cur0_bpp)); 1358 } 1359 1360 refcyc_per_req_delivery_pre_cur1 = 0.0; 1361 refcyc_per_req_delivery_cur1 = 0.0; 1362 if (src->num_cursors > 1) { 1363 calculate_ttu_cursor(mode_lib, 1364 &refcyc_per_req_delivery_pre_cur1, 1365 &refcyc_per_req_delivery_cur1, 1366 refclk_freq_in_mhz, 1367 ref_freq_to_pix_freq, 1368 hscale_pixel_rate_l, 1369 scl->hscl_ratio, 1370 vratio_pre_l, 1371 vratio_l, 1372 src->cur1_src_width, 1373 (enum cursor_bpp)(src->cur1_bpp)); 1374 } 1375 1376 // TTU - Misc 1377 // all hard-coded 1378 1379 // Assignment to register structures 1380 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1381 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1382 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1383 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1384 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1385 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1386 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1387 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1388 1389 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1390 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1391 1392 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1393 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1394 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1395 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1396 1397 if (dual_plane) { 1398 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank 1399 * (double) htotal * ref_freq_to_pix_freq 1400 / (double) dpte_groups_per_row_ub_c); 1401 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1402 < (unsigned int) dml_pow(2, 13)); 1403 } 1404 1405 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1406 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1407 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1408 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1409 1410 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1411 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1412 1413 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1414 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1415 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1416 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1417 1418 if (dual_plane) { 1419 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip 1420 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1421 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip 1422 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1423 } 1424 1425 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1426 / (double) vratio_l * dml_pow(2, 2)); 1427 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1428 1429 if (dual_plane) { 1430 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1431 / (double) vratio_c * dml_pow(2, 2)); 1432 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1433 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1434 __func__, 1435 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1436 (unsigned int) dml_pow(2, 17) - 1); 1437 } 1438 } 1439 1440 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1441 / (double) vratio_l * dml_pow(2, 2)); 1442 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1443 1444 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1445 1446 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1447 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1448 / (double) dpte_groups_per_row_ub_l); 1449 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1450 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1451 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1452 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1453 / (double) meta_chunks_per_row_ub_l); 1454 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1455 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1456 1457 if (dual_plane) { 1458 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1459 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c 1460 * (double) htotal * ref_freq_to_pix_freq 1461 / (double) dpte_groups_per_row_ub_c); 1462 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1463 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1464 1465 // TODO: Is this the right calculation? Does htotal need to be halved? 1466 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1467 (unsigned int) ((double) meta_row_height_c / (double) vratio_c 1468 * (double) htotal * ref_freq_to_pix_freq 1469 / (double) meta_chunks_per_row_ub_c); 1470 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1471 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1472 } 1473 1474 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1475 1); 1476 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1477 1); 1478 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1479 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1480 1481 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1482 1); 1483 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1484 1); 1485 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1486 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1487 1488 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1489 disp_dlg_regs->dst_y_offset_cur0 = 0; 1490 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1491 disp_dlg_regs->dst_y_offset_cur1 = 0; 1492 1493 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1494 1495 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1496 * dml_pow(2, 10)); 1497 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1498 * dml_pow(2, 10)); 1499 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c 1500 * dml_pow(2, 10)); 1501 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1502 * dml_pow(2, 10)); 1503 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1504 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1505 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 1506 * dml_pow(2, 10)); 1507 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1508 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1509 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 1510 * dml_pow(2, 10)); 1511 disp_ttu_regs->qos_level_low_wm = 0; 1512 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1513 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1514 * ref_freq_to_pix_freq); 1515 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ 1516 1517 disp_ttu_regs->qos_level_flip = 14; 1518 disp_ttu_regs->qos_level_fixed_l = 8; 1519 disp_ttu_regs->qos_level_fixed_c = 8; 1520 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1521 disp_ttu_regs->qos_ramp_disable_l = 0; 1522 disp_ttu_regs->qos_ramp_disable_c = 0; 1523 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1524 1525 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1526 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1527 1528 print__ttu_regs_st(mode_lib, *disp_ttu_regs); 1529 print__dlg_regs_st(mode_lib, *disp_dlg_regs); 1530 } 1531 1532 void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 1533 display_dlg_regs_st *dlg_regs, 1534 display_ttu_regs_st *ttu_regs, 1535 display_e2e_pipe_params_st *e2e_pipe_param, 1536 const unsigned int num_pipes, 1537 const unsigned int pipe_idx, 1538 const bool cstate_en, 1539 const bool pstate_en, 1540 const bool vm_en, 1541 const bool ignore_viewport_pos, 1542 const bool immediate_flip_support) 1543 { 1544 display_rq_params_st rq_param = {0}; 1545 display_dlg_sys_params_st dlg_sys_param = {0}; 1546 1547 // Get watermark and Tex. 1548 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1549 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, 1550 e2e_pipe_param, 1551 num_pipes); 1552 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1553 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1554 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1555 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1556 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, 1557 e2e_pipe_param, 1558 num_pipes); 1559 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, 1560 e2e_pipe_param, 1561 num_pipes); 1562 dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency 1563 / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated 1564 1565 print__dlg_sys_params_st(mode_lib, dlg_sys_param); 1566 1567 // system parameter calculation done 1568 1569 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1570 dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); 1571 dml20v2_rq_dlg_get_dlg_params(mode_lib, 1572 e2e_pipe_param, 1573 num_pipes, 1574 pipe_idx, 1575 dlg_regs, 1576 ttu_regs, 1577 rq_param.dlg, 1578 dlg_sys_param, 1579 cstate_en, 1580 pstate_en); 1581 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1582 } 1583 1584 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 1585 double *refcyc_per_req_delivery_pre_cur, 1586 double *refcyc_per_req_delivery_cur, 1587 double refclk_freq_in_mhz, 1588 double ref_freq_to_pix_freq, 1589 double hscale_pixel_rate_l, 1590 double hscl_ratio, 1591 double vratio_pre_l, 1592 double vratio_l, 1593 unsigned int cur_width, 1594 enum cursor_bpp cur_bpp) 1595 { 1596 unsigned int cur_src_width = cur_width; 1597 unsigned int cur_req_size = 0; 1598 unsigned int cur_req_width = 0; 1599 double cur_width_ub = 0.0; 1600 double cur_req_per_width = 0.0; 1601 double hactive_cur = 0.0; 1602 1603 ASSERT(cur_src_width <= 256); 1604 1605 *refcyc_per_req_delivery_pre_cur = 0.0; 1606 *refcyc_per_req_delivery_cur = 0.0; 1607 if (cur_src_width > 0) { 1608 unsigned int cur_bit_per_pixel = 0; 1609 1610 if (cur_bpp == dm_cur_2bit) { 1611 cur_req_size = 64; // byte 1612 cur_bit_per_pixel = 2; 1613 } else { // 32bit 1614 cur_bit_per_pixel = 32; 1615 if (cur_src_width >= 1 && cur_src_width <= 16) 1616 cur_req_size = 64; 1617 else if (cur_src_width >= 17 && cur_src_width <= 31) 1618 cur_req_size = 128; 1619 else 1620 cur_req_size = 256; 1621 } 1622 1623 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 1624 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) 1625 * (double) cur_req_width; 1626 cur_req_per_width = cur_width_ub / (double) cur_req_width; 1627 hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor 1628 1629 if (vratio_pre_l <= 1.0) { 1630 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 1631 / (double) cur_req_per_width; 1632 } else { 1633 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz 1634 * (double) cur_src_width / hscale_pixel_rate_l 1635 / (double) cur_req_per_width; 1636 } 1637 1638 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 1639 1640 if (vratio_l <= 1.0) { 1641 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 1642 / (double) cur_req_per_width; 1643 } else { 1644 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz 1645 * (double) cur_src_width / hscale_pixel_rate_l 1646 / (double) cur_req_per_width; 1647 } 1648 1649 dml_print("DML_DLG: %s: cur_req_width = %d\n", 1650 __func__, 1651 cur_req_width); 1652 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", 1653 __func__, 1654 cur_width_ub); 1655 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", 1656 __func__, 1657 cur_req_per_width); 1658 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", 1659 __func__, 1660 hactive_cur); 1661 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 1662 __func__, 1663 *refcyc_per_req_delivery_pre_cur); 1664 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 1665 __func__, 1666 *refcyc_per_req_delivery_cur); 1667 1668 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1669 } 1670 } 1671