1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2021 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "resource.h" 28 #include "clk_mgr.h" 29 #include "dc_link_dp.h" 30 #include "dchubbub.h" 31 #include "dcn20/dcn20_resource.h" 32 #include "dcn21/dcn21_resource.h" 33 34 #include "dcn20_fpu.h" 35 36 #define DC_LOGGER_INIT(logger) 37 38 #ifndef MAX 39 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 40 #endif 41 #ifndef MIN 42 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 43 #endif 44 45 /** 46 * DOC: DCN2x FPU manipulation Overview 47 * 48 * The DCN architecture relies on FPU operations, which require special 49 * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we 50 * want to avoid spreading FPU access across multiple files. With this idea in 51 * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions 52 * that require FPU access in a single place. Code in this file follows the 53 * following code pattern: 54 * 55 * 1. Functions that use FPU operations should be isolated in static functions. 56 * 2. The FPU functions should have the noinline attribute to ensure anything 57 * that deals with FP register is contained within this call. 58 * 3. All function that needs to be accessed outside this file requires a 59 * public interface that not uses any FPU reference. 60 * 4. Developers **must not** use DC_FP_START/END in this file, but they need 61 * to ensure that the caller invokes it before access any function available 62 * in this file. For this reason, public functions in this file must invoke 63 * dc_assert_fp_enabled(); 64 * 65 * Let's expand a little bit more the idea in the code pattern. To fully 66 * isolate FPU operations in a single place, we must avoid situations where 67 * compilers spill FP values to registers due to FP enable in a specific C 68 * file. Note that even if we isolate all FPU functions in a single file and 69 * call its interface from other files, the compiler might enable the use of 70 * FPU before we call DC_FP_START. Nevertheless, it is the programmer's 71 * responsibility to invoke DC_FP_START/END in the correct place. To highlight 72 * situations where developers forgot to use the FP protection before calling 73 * the DC FPU interface functions, we introduce a helper that checks if the 74 * function is invoked under FP protection. If not, it will trigger a kernel 75 * warning. 76 */ 77 78 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 79 .odm_capable = 1, 80 .gpuvm_enable = 0, 81 .hostvm_enable = 0, 82 .gpuvm_max_page_table_levels = 4, 83 .hostvm_max_page_table_levels = 4, 84 .hostvm_cached_page_table_levels = 0, 85 .pte_group_size_bytes = 2048, 86 .num_dsc = 6, 87 .rob_buffer_size_kbytes = 168, 88 .det_buffer_size_kbytes = 164, 89 .dpte_buffer_size_in_pte_reqs_luma = 84, 90 .pde_proc_buffer_size_64k_reqs = 48, 91 .dpp_output_buffer_pixels = 2560, 92 .opp_output_buffer_lines = 1, 93 .pixel_chunk_size_kbytes = 8, 94 .pte_chunk_size_kbytes = 2, 95 .meta_chunk_size_kbytes = 2, 96 .writeback_chunk_size_kbytes = 2, 97 .line_buffer_size_bits = 789504, 98 .is_line_buffer_bpp_fixed = 0, 99 .line_buffer_fixed_bpp = 0, 100 .dcc_supported = true, 101 .max_line_buffer_lines = 12, 102 .writeback_luma_buffer_size_kbytes = 12, 103 .writeback_chroma_buffer_size_kbytes = 8, 104 .writeback_chroma_line_buffer_width_pixels = 4, 105 .writeback_max_hscl_ratio = 1, 106 .writeback_max_vscl_ratio = 1, 107 .writeback_min_hscl_ratio = 1, 108 .writeback_min_vscl_ratio = 1, 109 .writeback_max_hscl_taps = 12, 110 .writeback_max_vscl_taps = 12, 111 .writeback_line_buffer_luma_buffer_size = 0, 112 .writeback_line_buffer_chroma_buffer_size = 14643, 113 .cursor_buffer_size = 8, 114 .cursor_chunk_size = 2, 115 .max_num_otg = 6, 116 .max_num_dpp = 6, 117 .max_num_wb = 1, 118 .max_dchub_pscl_bw_pix_per_clk = 4, 119 .max_pscl_lb_bw_pix_per_clk = 2, 120 .max_lb_vscl_bw_pix_per_clk = 4, 121 .max_vscl_hscl_bw_pix_per_clk = 4, 122 .max_hscl_ratio = 8, 123 .max_vscl_ratio = 8, 124 .hscl_mults = 4, 125 .vscl_mults = 4, 126 .max_hscl_taps = 8, 127 .max_vscl_taps = 8, 128 .dispclk_ramp_margin_percent = 1, 129 .underscan_factor = 1.10, 130 .min_vblank_lines = 32, // 131 .dppclk_delay_subtotal = 77, // 132 .dppclk_delay_scl_lb_only = 16, 133 .dppclk_delay_scl = 50, 134 .dppclk_delay_cnvc_formatter = 8, 135 .dppclk_delay_cnvc_cursor = 6, 136 .dispclk_delay_subtotal = 87, // 137 .dcfclk_cstate_latency = 10, // SRExitTime 138 .max_inter_dcn_tile_repeaters = 8, 139 .xfc_supported = true, 140 .xfc_fill_bw_overhead_percent = 10.0, 141 .xfc_fill_constant_bytes = 0, 142 .number_of_cursors = 1, 143 }; 144 145 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 146 .odm_capable = 1, 147 .gpuvm_enable = 0, 148 .hostvm_enable = 0, 149 .gpuvm_max_page_table_levels = 4, 150 .hostvm_max_page_table_levels = 4, 151 .hostvm_cached_page_table_levels = 0, 152 .num_dsc = 5, 153 .rob_buffer_size_kbytes = 168, 154 .det_buffer_size_kbytes = 164, 155 .dpte_buffer_size_in_pte_reqs_luma = 84, 156 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 157 .dpp_output_buffer_pixels = 2560, 158 .opp_output_buffer_lines = 1, 159 .pixel_chunk_size_kbytes = 8, 160 .pte_enable = 1, 161 .max_page_table_levels = 4, 162 .pte_chunk_size_kbytes = 2, 163 .meta_chunk_size_kbytes = 2, 164 .writeback_chunk_size_kbytes = 2, 165 .line_buffer_size_bits = 789504, 166 .is_line_buffer_bpp_fixed = 0, 167 .line_buffer_fixed_bpp = 0, 168 .dcc_supported = true, 169 .max_line_buffer_lines = 12, 170 .writeback_luma_buffer_size_kbytes = 12, 171 .writeback_chroma_buffer_size_kbytes = 8, 172 .writeback_chroma_line_buffer_width_pixels = 4, 173 .writeback_max_hscl_ratio = 1, 174 .writeback_max_vscl_ratio = 1, 175 .writeback_min_hscl_ratio = 1, 176 .writeback_min_vscl_ratio = 1, 177 .writeback_max_hscl_taps = 12, 178 .writeback_max_vscl_taps = 12, 179 .writeback_line_buffer_luma_buffer_size = 0, 180 .writeback_line_buffer_chroma_buffer_size = 14643, 181 .cursor_buffer_size = 8, 182 .cursor_chunk_size = 2, 183 .max_num_otg = 5, 184 .max_num_dpp = 5, 185 .max_num_wb = 1, 186 .max_dchub_pscl_bw_pix_per_clk = 4, 187 .max_pscl_lb_bw_pix_per_clk = 2, 188 .max_lb_vscl_bw_pix_per_clk = 4, 189 .max_vscl_hscl_bw_pix_per_clk = 4, 190 .max_hscl_ratio = 8, 191 .max_vscl_ratio = 8, 192 .hscl_mults = 4, 193 .vscl_mults = 4, 194 .max_hscl_taps = 8, 195 .max_vscl_taps = 8, 196 .dispclk_ramp_margin_percent = 1, 197 .underscan_factor = 1.10, 198 .min_vblank_lines = 32, // 199 .dppclk_delay_subtotal = 77, // 200 .dppclk_delay_scl_lb_only = 16, 201 .dppclk_delay_scl = 50, 202 .dppclk_delay_cnvc_formatter = 8, 203 .dppclk_delay_cnvc_cursor = 6, 204 .dispclk_delay_subtotal = 87, // 205 .dcfclk_cstate_latency = 10, // SRExitTime 206 .max_inter_dcn_tile_repeaters = 8, 207 .xfc_supported = true, 208 .xfc_fill_bw_overhead_percent = 10.0, 209 .xfc_fill_constant_bytes = 0, 210 .ptoi_supported = 0, 211 .number_of_cursors = 1, 212 }; 213 214 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 215 /* Defaults that get patched on driver load from firmware. */ 216 .clock_limits = { 217 { 218 .state = 0, 219 .dcfclk_mhz = 560.0, 220 .fabricclk_mhz = 560.0, 221 .dispclk_mhz = 513.0, 222 .dppclk_mhz = 513.0, 223 .phyclk_mhz = 540.0, 224 .socclk_mhz = 560.0, 225 .dscclk_mhz = 171.0, 226 .dram_speed_mts = 8960.0, 227 }, 228 { 229 .state = 1, 230 .dcfclk_mhz = 694.0, 231 .fabricclk_mhz = 694.0, 232 .dispclk_mhz = 642.0, 233 .dppclk_mhz = 642.0, 234 .phyclk_mhz = 600.0, 235 .socclk_mhz = 694.0, 236 .dscclk_mhz = 214.0, 237 .dram_speed_mts = 11104.0, 238 }, 239 { 240 .state = 2, 241 .dcfclk_mhz = 875.0, 242 .fabricclk_mhz = 875.0, 243 .dispclk_mhz = 734.0, 244 .dppclk_mhz = 734.0, 245 .phyclk_mhz = 810.0, 246 .socclk_mhz = 875.0, 247 .dscclk_mhz = 245.0, 248 .dram_speed_mts = 14000.0, 249 }, 250 { 251 .state = 3, 252 .dcfclk_mhz = 1000.0, 253 .fabricclk_mhz = 1000.0, 254 .dispclk_mhz = 1100.0, 255 .dppclk_mhz = 1100.0, 256 .phyclk_mhz = 810.0, 257 .socclk_mhz = 1000.0, 258 .dscclk_mhz = 367.0, 259 .dram_speed_mts = 16000.0, 260 }, 261 { 262 .state = 4, 263 .dcfclk_mhz = 1200.0, 264 .fabricclk_mhz = 1200.0, 265 .dispclk_mhz = 1284.0, 266 .dppclk_mhz = 1284.0, 267 .phyclk_mhz = 810.0, 268 .socclk_mhz = 1200.0, 269 .dscclk_mhz = 428.0, 270 .dram_speed_mts = 16000.0, 271 }, 272 /*Extra state, no dispclk ramping*/ 273 { 274 .state = 5, 275 .dcfclk_mhz = 1200.0, 276 .fabricclk_mhz = 1200.0, 277 .dispclk_mhz = 1284.0, 278 .dppclk_mhz = 1284.0, 279 .phyclk_mhz = 810.0, 280 .socclk_mhz = 1200.0, 281 .dscclk_mhz = 428.0, 282 .dram_speed_mts = 16000.0, 283 }, 284 }, 285 .num_states = 5, 286 .sr_exit_time_us = 8.6, 287 .sr_enter_plus_exit_time_us = 10.9, 288 .urgent_latency_us = 4.0, 289 .urgent_latency_pixel_data_only_us = 4.0, 290 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 291 .urgent_latency_vm_data_only_us = 4.0, 292 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 293 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 294 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 295 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 296 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 297 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 298 .max_avg_sdp_bw_use_normal_percent = 40.0, 299 .max_avg_dram_bw_use_normal_percent = 40.0, 300 .writeback_latency_us = 12.0, 301 .ideal_dram_bw_after_urgent_percent = 40.0, 302 .max_request_size_bytes = 256, 303 .dram_channel_width_bytes = 2, 304 .fabric_datapath_to_dcn_data_return_bytes = 64, 305 .dcn_downspread_percent = 0.5, 306 .downspread_percent = 0.38, 307 .dram_page_open_time_ns = 50.0, 308 .dram_rw_turnaround_time_ns = 17.5, 309 .dram_return_buffer_per_channel_bytes = 8192, 310 .round_trip_ping_latency_dcfclk_cycles = 131, 311 .urgent_out_of_order_return_per_channel_bytes = 256, 312 .channel_interleave_bytes = 256, 313 .num_banks = 8, 314 .num_chans = 16, 315 .vmm_page_size_bytes = 4096, 316 .dram_clock_change_latency_us = 404.0, 317 .dummy_pstate_latency_us = 5.0, 318 .writeback_dram_clock_change_latency_us = 23.0, 319 .return_bus_width_bytes = 64, 320 .dispclk_dppclk_vco_speed_mhz = 3850, 321 .xfc_bus_transport_time_us = 20, 322 .xfc_xbuf_latency_tolerance_us = 4, 323 .use_urgent_burst_bw = 0 324 }; 325 326 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 327 .clock_limits = { 328 { 329 .state = 0, 330 .dcfclk_mhz = 560.0, 331 .fabricclk_mhz = 560.0, 332 .dispclk_mhz = 513.0, 333 .dppclk_mhz = 513.0, 334 .phyclk_mhz = 540.0, 335 .socclk_mhz = 560.0, 336 .dscclk_mhz = 171.0, 337 .dram_speed_mts = 8960.0, 338 }, 339 { 340 .state = 1, 341 .dcfclk_mhz = 694.0, 342 .fabricclk_mhz = 694.0, 343 .dispclk_mhz = 642.0, 344 .dppclk_mhz = 642.0, 345 .phyclk_mhz = 600.0, 346 .socclk_mhz = 694.0, 347 .dscclk_mhz = 214.0, 348 .dram_speed_mts = 11104.0, 349 }, 350 { 351 .state = 2, 352 .dcfclk_mhz = 875.0, 353 .fabricclk_mhz = 875.0, 354 .dispclk_mhz = 734.0, 355 .dppclk_mhz = 734.0, 356 .phyclk_mhz = 810.0, 357 .socclk_mhz = 875.0, 358 .dscclk_mhz = 245.0, 359 .dram_speed_mts = 14000.0, 360 }, 361 { 362 .state = 3, 363 .dcfclk_mhz = 1000.0, 364 .fabricclk_mhz = 1000.0, 365 .dispclk_mhz = 1100.0, 366 .dppclk_mhz = 1100.0, 367 .phyclk_mhz = 810.0, 368 .socclk_mhz = 1000.0, 369 .dscclk_mhz = 367.0, 370 .dram_speed_mts = 16000.0, 371 }, 372 { 373 .state = 4, 374 .dcfclk_mhz = 1200.0, 375 .fabricclk_mhz = 1200.0, 376 .dispclk_mhz = 1284.0, 377 .dppclk_mhz = 1284.0, 378 .phyclk_mhz = 810.0, 379 .socclk_mhz = 1200.0, 380 .dscclk_mhz = 428.0, 381 .dram_speed_mts = 16000.0, 382 }, 383 /*Extra state, no dispclk ramping*/ 384 { 385 .state = 5, 386 .dcfclk_mhz = 1200.0, 387 .fabricclk_mhz = 1200.0, 388 .dispclk_mhz = 1284.0, 389 .dppclk_mhz = 1284.0, 390 .phyclk_mhz = 810.0, 391 .socclk_mhz = 1200.0, 392 .dscclk_mhz = 428.0, 393 .dram_speed_mts = 16000.0, 394 }, 395 }, 396 .num_states = 5, 397 .sr_exit_time_us = 11.6, 398 .sr_enter_plus_exit_time_us = 13.9, 399 .urgent_latency_us = 4.0, 400 .urgent_latency_pixel_data_only_us = 4.0, 401 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 402 .urgent_latency_vm_data_only_us = 4.0, 403 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 404 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 405 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 406 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 407 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 408 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 409 .max_avg_sdp_bw_use_normal_percent = 40.0, 410 .max_avg_dram_bw_use_normal_percent = 40.0, 411 .writeback_latency_us = 12.0, 412 .ideal_dram_bw_after_urgent_percent = 40.0, 413 .max_request_size_bytes = 256, 414 .dram_channel_width_bytes = 2, 415 .fabric_datapath_to_dcn_data_return_bytes = 64, 416 .dcn_downspread_percent = 0.5, 417 .downspread_percent = 0.38, 418 .dram_page_open_time_ns = 50.0, 419 .dram_rw_turnaround_time_ns = 17.5, 420 .dram_return_buffer_per_channel_bytes = 8192, 421 .round_trip_ping_latency_dcfclk_cycles = 131, 422 .urgent_out_of_order_return_per_channel_bytes = 256, 423 .channel_interleave_bytes = 256, 424 .num_banks = 8, 425 .num_chans = 8, 426 .vmm_page_size_bytes = 4096, 427 .dram_clock_change_latency_us = 404.0, 428 .dummy_pstate_latency_us = 5.0, 429 .writeback_dram_clock_change_latency_us = 23.0, 430 .return_bus_width_bytes = 64, 431 .dispclk_dppclk_vco_speed_mhz = 3850, 432 .xfc_bus_transport_time_us = 20, 433 .xfc_xbuf_latency_tolerance_us = 4, 434 .use_urgent_burst_bw = 0 435 }; 436 437 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 438 439 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 440 .odm_capable = 1, 441 .gpuvm_enable = 1, 442 .hostvm_enable = 1, 443 .gpuvm_max_page_table_levels = 1, 444 .hostvm_max_page_table_levels = 4, 445 .hostvm_cached_page_table_levels = 2, 446 .num_dsc = 3, 447 .rob_buffer_size_kbytes = 168, 448 .det_buffer_size_kbytes = 164, 449 .dpte_buffer_size_in_pte_reqs_luma = 44, 450 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 451 .dpp_output_buffer_pixels = 2560, 452 .opp_output_buffer_lines = 1, 453 .pixel_chunk_size_kbytes = 8, 454 .pte_enable = 1, 455 .max_page_table_levels = 4, 456 .pte_chunk_size_kbytes = 2, 457 .meta_chunk_size_kbytes = 2, 458 .min_meta_chunk_size_bytes = 256, 459 .writeback_chunk_size_kbytes = 2, 460 .line_buffer_size_bits = 789504, 461 .is_line_buffer_bpp_fixed = 0, 462 .line_buffer_fixed_bpp = 0, 463 .dcc_supported = true, 464 .max_line_buffer_lines = 12, 465 .writeback_luma_buffer_size_kbytes = 12, 466 .writeback_chroma_buffer_size_kbytes = 8, 467 .writeback_chroma_line_buffer_width_pixels = 4, 468 .writeback_max_hscl_ratio = 1, 469 .writeback_max_vscl_ratio = 1, 470 .writeback_min_hscl_ratio = 1, 471 .writeback_min_vscl_ratio = 1, 472 .writeback_max_hscl_taps = 12, 473 .writeback_max_vscl_taps = 12, 474 .writeback_line_buffer_luma_buffer_size = 0, 475 .writeback_line_buffer_chroma_buffer_size = 14643, 476 .cursor_buffer_size = 8, 477 .cursor_chunk_size = 2, 478 .max_num_otg = 4, 479 .max_num_dpp = 4, 480 .max_num_wb = 1, 481 .max_dchub_pscl_bw_pix_per_clk = 4, 482 .max_pscl_lb_bw_pix_per_clk = 2, 483 .max_lb_vscl_bw_pix_per_clk = 4, 484 .max_vscl_hscl_bw_pix_per_clk = 4, 485 .max_hscl_ratio = 4, 486 .max_vscl_ratio = 4, 487 .hscl_mults = 4, 488 .vscl_mults = 4, 489 .max_hscl_taps = 8, 490 .max_vscl_taps = 8, 491 .dispclk_ramp_margin_percent = 1, 492 .underscan_factor = 1.10, 493 .min_vblank_lines = 32, // 494 .dppclk_delay_subtotal = 77, // 495 .dppclk_delay_scl_lb_only = 16, 496 .dppclk_delay_scl = 50, 497 .dppclk_delay_cnvc_formatter = 8, 498 .dppclk_delay_cnvc_cursor = 6, 499 .dispclk_delay_subtotal = 87, // 500 .dcfclk_cstate_latency = 10, // SRExitTime 501 .max_inter_dcn_tile_repeaters = 8, 502 503 .xfc_supported = false, 504 .xfc_fill_bw_overhead_percent = 10.0, 505 .xfc_fill_constant_bytes = 0, 506 .ptoi_supported = 0, 507 .number_of_cursors = 1, 508 }; 509 510 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 511 .clock_limits = { 512 { 513 .state = 0, 514 .dcfclk_mhz = 400.0, 515 .fabricclk_mhz = 400.0, 516 .dispclk_mhz = 600.0, 517 .dppclk_mhz = 400.00, 518 .phyclk_mhz = 600.0, 519 .socclk_mhz = 278.0, 520 .dscclk_mhz = 205.67, 521 .dram_speed_mts = 1600.0, 522 }, 523 { 524 .state = 1, 525 .dcfclk_mhz = 464.52, 526 .fabricclk_mhz = 800.0, 527 .dispclk_mhz = 654.55, 528 .dppclk_mhz = 626.09, 529 .phyclk_mhz = 600.0, 530 .socclk_mhz = 278.0, 531 .dscclk_mhz = 205.67, 532 .dram_speed_mts = 1600.0, 533 }, 534 { 535 .state = 2, 536 .dcfclk_mhz = 514.29, 537 .fabricclk_mhz = 933.0, 538 .dispclk_mhz = 757.89, 539 .dppclk_mhz = 685.71, 540 .phyclk_mhz = 600.0, 541 .socclk_mhz = 278.0, 542 .dscclk_mhz = 287.67, 543 .dram_speed_mts = 1866.0, 544 }, 545 { 546 .state = 3, 547 .dcfclk_mhz = 576.00, 548 .fabricclk_mhz = 1067.0, 549 .dispclk_mhz = 847.06, 550 .dppclk_mhz = 757.89, 551 .phyclk_mhz = 600.0, 552 .socclk_mhz = 715.0, 553 .dscclk_mhz = 318.334, 554 .dram_speed_mts = 2134.0, 555 }, 556 { 557 .state = 4, 558 .dcfclk_mhz = 626.09, 559 .fabricclk_mhz = 1200.0, 560 .dispclk_mhz = 900.00, 561 .dppclk_mhz = 847.06, 562 .phyclk_mhz = 810.0, 563 .socclk_mhz = 953.0, 564 .dscclk_mhz = 489.0, 565 .dram_speed_mts = 2400.0, 566 }, 567 { 568 .state = 5, 569 .dcfclk_mhz = 685.71, 570 .fabricclk_mhz = 1333.0, 571 .dispclk_mhz = 1028.57, 572 .dppclk_mhz = 960.00, 573 .phyclk_mhz = 810.0, 574 .socclk_mhz = 278.0, 575 .dscclk_mhz = 287.67, 576 .dram_speed_mts = 2666.0, 577 }, 578 { 579 .state = 6, 580 .dcfclk_mhz = 757.89, 581 .fabricclk_mhz = 1467.0, 582 .dispclk_mhz = 1107.69, 583 .dppclk_mhz = 1028.57, 584 .phyclk_mhz = 810.0, 585 .socclk_mhz = 715.0, 586 .dscclk_mhz = 318.334, 587 .dram_speed_mts = 3200.0, 588 }, 589 { 590 .state = 7, 591 .dcfclk_mhz = 847.06, 592 .fabricclk_mhz = 1600.0, 593 .dispclk_mhz = 1395.0, 594 .dppclk_mhz = 1285.00, 595 .phyclk_mhz = 1325.0, 596 .socclk_mhz = 953.0, 597 .dscclk_mhz = 489.0, 598 .dram_speed_mts = 4266.0, 599 }, 600 /*Extra state, no dispclk ramping*/ 601 { 602 .state = 8, 603 .dcfclk_mhz = 847.06, 604 .fabricclk_mhz = 1600.0, 605 .dispclk_mhz = 1395.0, 606 .dppclk_mhz = 1285.0, 607 .phyclk_mhz = 1325.0, 608 .socclk_mhz = 953.0, 609 .dscclk_mhz = 489.0, 610 .dram_speed_mts = 4266.0, 611 }, 612 613 }, 614 615 .sr_exit_time_us = 12.5, 616 .sr_enter_plus_exit_time_us = 17.0, 617 .urgent_latency_us = 4.0, 618 .urgent_latency_pixel_data_only_us = 4.0, 619 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 620 .urgent_latency_vm_data_only_us = 4.0, 621 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 622 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 623 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 624 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 625 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 626 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 627 .max_avg_sdp_bw_use_normal_percent = 60.0, 628 .max_avg_dram_bw_use_normal_percent = 100.0, 629 .writeback_latency_us = 12.0, 630 .max_request_size_bytes = 256, 631 .dram_channel_width_bytes = 4, 632 .fabric_datapath_to_dcn_data_return_bytes = 32, 633 .dcn_downspread_percent = 0.5, 634 .downspread_percent = 0.38, 635 .dram_page_open_time_ns = 50.0, 636 .dram_rw_turnaround_time_ns = 17.5, 637 .dram_return_buffer_per_channel_bytes = 8192, 638 .round_trip_ping_latency_dcfclk_cycles = 128, 639 .urgent_out_of_order_return_per_channel_bytes = 4096, 640 .channel_interleave_bytes = 256, 641 .num_banks = 8, 642 .num_chans = 4, 643 .vmm_page_size_bytes = 4096, 644 .dram_clock_change_latency_us = 23.84, 645 .return_bus_width_bytes = 64, 646 .dispclk_dppclk_vco_speed_mhz = 3600, 647 .xfc_bus_transport_time_us = 4, 648 .xfc_xbuf_latency_tolerance_us = 4, 649 .use_urgent_burst_bw = 1, 650 .num_states = 8 651 }; 652 653 void dcn20_populate_dml_writeback_from_context(struct dc *dc, 654 struct resource_context *res_ctx, 655 display_e2e_pipe_params_st *pipes) 656 { 657 int pipe_cnt, i; 658 659 dc_assert_fp_enabled(); 660 661 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 662 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 663 664 if (!res_ctx->pipe_ctx[i].stream) 665 continue; 666 667 /* Set writeback information */ 668 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 669 pipes[pipe_cnt].dout.num_active_wb++; 670 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 671 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 672 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 673 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 674 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 675 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 676 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 677 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 678 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 679 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 680 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 681 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 682 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 683 else 684 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 685 } else { 686 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 687 } 688 689 pipe_cnt++; 690 } 691 } 692 693 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, 694 struct dc_state *context, 695 display_e2e_pipe_params_st *pipes, 696 int pipe_cnt, int i) 697 { 698 int k; 699 700 dc_assert_fp_enabled(); 701 702 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 703 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 704 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 705 } 706 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ 707 } 708 709 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 710 { 711 int i; 712 for (i = 0; i < dc->res_pool->pipe_count; i++) { 713 if (!context->res_ctx.pipe_ctx[i].stream) 714 continue; 715 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 716 return true; 717 } 718 return false; 719 } 720 721 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context) 722 { 723 int plane_count; 724 int i; 725 726 plane_count = 0; 727 for (i = 0; i < dc->res_pool->pipe_count; i++) { 728 if (context->res_ctx.pipe_ctx[i].plane_state) 729 plane_count++; 730 } 731 732 /* 733 * Z9 and Z10 allowed cases: 734 * 1. 0 Planes enabled 735 * 2. single eDP, on link 0, 1 plane and stutter period > 5ms 736 * Z10 only cases: 737 * 1. single eDP, on link 0, 1 plane and stutter period >= 5ms 738 * Zstate not allowed cases: 739 * 1. Everything else 740 */ 741 if (plane_count == 0) 742 return DCN_ZSTATE_SUPPORT_ALLOW; 743 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { 744 struct dc_link *link = context->streams[0]->sink->link; 745 struct dc_stream_status *stream_status = &context->stream_status[0]; 746 747 /* zstate only supported on PWRSEQ0 and when there's <2 planes*/ 748 if (link->link_index != 0 || stream_status->plane_count > 1) 749 return DCN_ZSTATE_SUPPORT_DISALLOW; 750 751 if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) 752 return DCN_ZSTATE_SUPPORT_ALLOW; 753 else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr) 754 return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY; 755 else 756 return DCN_ZSTATE_SUPPORT_DISALLOW; 757 } else 758 return DCN_ZSTATE_SUPPORT_DISALLOW; 759 } 760 761 void dcn20_calculate_dlg_params( 762 struct dc *dc, struct dc_state *context, 763 display_e2e_pipe_params_st *pipes, 764 int pipe_cnt, 765 int vlevel) 766 { 767 int i, pipe_idx; 768 769 dc_assert_fp_enabled(); 770 771 /* Writeback MCIF_WB arbitration parameters */ 772 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 773 774 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 775 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 776 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 777 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 778 779 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) 780 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; 781 782 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 783 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 784 context->bw_ctx.bw.dcn.clk.p_state_change_support = 785 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 786 != dm_dram_clock_change_unsupported; 787 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 788 789 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context); 790 791 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 792 793 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 794 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 795 796 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 797 if (!context->res_ctx.pipe_ctx[i].stream) 798 continue; 799 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 800 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 801 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 802 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 803 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 804 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 805 806 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 807 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 808 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 809 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 810 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 811 pipe_idx++; 812 } 813 /*save a original dppclock copy*/ 814 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 815 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 816 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 817 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 818 819 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes 820 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; 821 822 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 823 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 824 825 if (!context->res_ctx.pipe_ctx[i].stream) 826 continue; 827 828 if (dc->ctx->dce_version == DCN_VERSION_2_01) 829 cstate_en = false; 830 831 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 832 &context->res_ctx.pipe_ctx[i].dlg_regs, 833 &context->res_ctx.pipe_ctx[i].ttu_regs, 834 pipes, 835 pipe_cnt, 836 pipe_idx, 837 cstate_en, 838 context->bw_ctx.bw.dcn.clk.p_state_change_support, 839 false, false, true); 840 841 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 842 &context->res_ctx.pipe_ctx[i].rq_regs, 843 &pipes[pipe_idx].pipe); 844 pipe_idx++; 845 } 846 } 847 848 static void swizzle_to_dml_params( 849 enum swizzle_mode_values swizzle, 850 unsigned int *sw_mode) 851 { 852 switch (swizzle) { 853 case DC_SW_LINEAR: 854 *sw_mode = dm_sw_linear; 855 break; 856 case DC_SW_4KB_S: 857 *sw_mode = dm_sw_4kb_s; 858 break; 859 case DC_SW_4KB_S_X: 860 *sw_mode = dm_sw_4kb_s_x; 861 break; 862 case DC_SW_4KB_D: 863 *sw_mode = dm_sw_4kb_d; 864 break; 865 case DC_SW_4KB_D_X: 866 *sw_mode = dm_sw_4kb_d_x; 867 break; 868 case DC_SW_64KB_S: 869 *sw_mode = dm_sw_64kb_s; 870 break; 871 case DC_SW_64KB_S_X: 872 *sw_mode = dm_sw_64kb_s_x; 873 break; 874 case DC_SW_64KB_S_T: 875 *sw_mode = dm_sw_64kb_s_t; 876 break; 877 case DC_SW_64KB_D: 878 *sw_mode = dm_sw_64kb_d; 879 break; 880 case DC_SW_64KB_D_X: 881 *sw_mode = dm_sw_64kb_d_x; 882 break; 883 case DC_SW_64KB_D_T: 884 *sw_mode = dm_sw_64kb_d_t; 885 break; 886 case DC_SW_64KB_R_X: 887 *sw_mode = dm_sw_64kb_r_x; 888 break; 889 case DC_SW_VAR_S: 890 *sw_mode = dm_sw_var_s; 891 break; 892 case DC_SW_VAR_S_X: 893 *sw_mode = dm_sw_var_s_x; 894 break; 895 case DC_SW_VAR_D: 896 *sw_mode = dm_sw_var_d; 897 break; 898 case DC_SW_VAR_D_X: 899 *sw_mode = dm_sw_var_d_x; 900 break; 901 case DC_SW_VAR_R_X: 902 *sw_mode = dm_sw_var_r_x; 903 break; 904 default: 905 ASSERT(0); /* Not supported */ 906 break; 907 } 908 } 909 910 int dcn20_populate_dml_pipes_from_context( 911 struct dc *dc, 912 struct dc_state *context, 913 display_e2e_pipe_params_st *pipes, 914 bool fast_validate) 915 { 916 int pipe_cnt, i; 917 bool synchronized_vblank = true; 918 struct resource_context *res_ctx = &context->res_ctx; 919 920 dc_assert_fp_enabled(); 921 922 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 923 if (!res_ctx->pipe_ctx[i].stream) 924 continue; 925 926 if (pipe_cnt < 0) { 927 pipe_cnt = i; 928 continue; 929 } 930 931 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) 932 continue; 933 934 if (dc->debug.disable_timing_sync || 935 (!resource_are_streams_timing_synchronizable( 936 res_ctx->pipe_ctx[pipe_cnt].stream, 937 res_ctx->pipe_ctx[i].stream) && 938 !resource_are_vblanks_synchronizable( 939 res_ctx->pipe_ctx[pipe_cnt].stream, 940 res_ctx->pipe_ctx[i].stream))) { 941 synchronized_vblank = false; 942 break; 943 } 944 } 945 946 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 947 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 948 unsigned int v_total; 949 unsigned int front_porch; 950 int output_bpc; 951 struct audio_check aud_check = {0}; 952 953 if (!res_ctx->pipe_ctx[i].stream) 954 continue; 955 956 v_total = timing->v_total; 957 front_porch = timing->v_front_porch; 958 959 /* todo: 960 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 961 pipes[pipe_cnt].pipe.src.dcc = 0; 962 pipes[pipe_cnt].pipe.src.vm = 0;*/ 963 964 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 965 966 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 967 /* todo: rotation?*/ 968 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 969 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 970 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 971 /* 1/2 vblank */ 972 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 973 (v_total - timing->v_addressable 974 - timing->v_border_top - timing->v_border_bottom) / 2; 975 /* 36 bytes dp, 32 hdmi */ 976 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 977 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 978 } 979 pipes[pipe_cnt].pipe.src.dcc = false; 980 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 981 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 982 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 983 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 984 - timing->h_addressable 985 - timing->h_border_left 986 - timing->h_border_right; 987 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 988 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 989 - timing->v_addressable 990 - timing->v_border_top 991 - timing->v_border_bottom; 992 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 993 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 994 pipes[pipe_cnt].pipe.dest.hactive = 995 timing->h_addressable + timing->h_border_left + timing->h_border_right; 996 pipes[pipe_cnt].pipe.dest.vactive = 997 timing->v_addressable + timing->v_border_top + timing->v_border_bottom; 998 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 999 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 1000 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1001 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 1002 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 1003 pipes[pipe_cnt].dout.dp_lanes = 4; 1004 pipes[pipe_cnt].dout.is_virtual = 0; 1005 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 1006 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 1007 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 1008 case 1: 1009 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 1010 break; 1011 case 3: 1012 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1; 1013 break; 1014 default: 1015 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 1016 } 1017 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1018 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 1019 == res_ctx->pipe_ctx[i].plane_state) { 1020 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 1021 int split_idx = 0; 1022 1023 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 1024 == res_ctx->pipe_ctx[i].plane_state) { 1025 first_pipe = first_pipe->top_pipe; 1026 split_idx++; 1027 } 1028 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */ 1029 if (split_idx == 0) 1030 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1031 else if (split_idx == 1) 1032 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1033 else if (split_idx == 2) 1034 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 1035 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 1036 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 1037 1038 while (first_pipe->prev_odm_pipe) 1039 first_pipe = first_pipe->prev_odm_pipe; 1040 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1041 } 1042 1043 switch (res_ctx->pipe_ctx[i].stream->signal) { 1044 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1045 case SIGNAL_TYPE_DISPLAY_PORT: 1046 pipes[pipe_cnt].dout.output_type = dm_dp; 1047 break; 1048 case SIGNAL_TYPE_EDP: 1049 pipes[pipe_cnt].dout.output_type = dm_edp; 1050 break; 1051 case SIGNAL_TYPE_HDMI_TYPE_A: 1052 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1053 case SIGNAL_TYPE_DVI_DUAL_LINK: 1054 pipes[pipe_cnt].dout.output_type = dm_hdmi; 1055 break; 1056 default: 1057 /* In case there is no signal, set dp with 4 lanes to allow max config */ 1058 pipes[pipe_cnt].dout.is_virtual = 1; 1059 pipes[pipe_cnt].dout.output_type = dm_dp; 1060 pipes[pipe_cnt].dout.dp_lanes = 4; 1061 } 1062 1063 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 1064 case COLOR_DEPTH_666: 1065 output_bpc = 6; 1066 break; 1067 case COLOR_DEPTH_888: 1068 output_bpc = 8; 1069 break; 1070 case COLOR_DEPTH_101010: 1071 output_bpc = 10; 1072 break; 1073 case COLOR_DEPTH_121212: 1074 output_bpc = 12; 1075 break; 1076 case COLOR_DEPTH_141414: 1077 output_bpc = 14; 1078 break; 1079 case COLOR_DEPTH_161616: 1080 output_bpc = 16; 1081 break; 1082 case COLOR_DEPTH_999: 1083 output_bpc = 9; 1084 break; 1085 case COLOR_DEPTH_111111: 1086 output_bpc = 11; 1087 break; 1088 default: 1089 output_bpc = 8; 1090 break; 1091 } 1092 1093 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 1094 case PIXEL_ENCODING_RGB: 1095 case PIXEL_ENCODING_YCBCR444: 1096 pipes[pipe_cnt].dout.output_format = dm_444; 1097 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 1098 break; 1099 case PIXEL_ENCODING_YCBCR420: 1100 pipes[pipe_cnt].dout.output_format = dm_420; 1101 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 1102 break; 1103 case PIXEL_ENCODING_YCBCR422: 1104 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC && 1105 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) 1106 pipes[pipe_cnt].dout.output_format = dm_n422; 1107 else 1108 pipes[pipe_cnt].dout.output_format = dm_s422; 1109 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 1110 break; 1111 default: 1112 pipes[pipe_cnt].dout.output_format = dm_444; 1113 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 1114 } 1115 1116 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 1117 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 1118 1119 /* todo: default max for now, until there is logic reflecting this in dc*/ 1120 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1121 /*fill up the audio sample rate (unit in kHz)*/ 1122 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check); 1123 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000; 1124 /* 1125 * For graphic plane, cursor number is 1, nv12 is 0 1126 * bw calculations due to cursor on/off 1127 */ 1128 if (res_ctx->pipe_ctx[i].plane_state && 1129 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 1130 pipes[pipe_cnt].pipe.src.num_cursors = 0; 1131 else 1132 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 1133 1134 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 1135 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 1136 1137 if (!res_ctx->pipe_ctx[i].plane_state) { 1138 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 1139 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 1140 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s; 1141 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 1142 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 1143 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 1144 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 1145 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 1146 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 1147 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 1148 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 1149 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 1150 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 1151 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 1152 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256; 1153 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 1154 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 1155 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 1156 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 1157 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 1158 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 1159 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 1160 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 1161 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 1162 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 1163 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 1164 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 1165 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 1166 1167 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 1168 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 1169 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 1170 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) { 1171 pipes[pipe_cnt].pipe.src.viewport_width /= 4; 1172 pipes[pipe_cnt].pipe.dest.recout_width /= 4; 1173 } 1174 } else { 1175 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 1176 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 1177 1178 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 1179 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 1180 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 1181 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 1182 1183 /* stereo is not split */ 1184 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || 1185 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { 1186 pipes[pipe_cnt].pipe.src.is_hsplit = false; 1187 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1188 } 1189 1190 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 1191 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 1192 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 1193 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 1194 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 1195 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 1196 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 1197 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 1198 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width; 1199 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height; 1200 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 1201 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 1202 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 1203 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 1204 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA 1205 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1206 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 1207 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 1208 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 1209 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 1210 } else { 1211 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 1212 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 1213 } 1214 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 1215 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 1216 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 1217 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 1218 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 1219 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 1220 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 1221 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) 1222 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; 1223 else { 1224 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 1225 1226 while (split_pipe && split_pipe->plane_state == pln) { 1227 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 1228 split_pipe = split_pipe->bottom_pipe; 1229 } 1230 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 1231 while (split_pipe && split_pipe->plane_state == pln) { 1232 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 1233 split_pipe = split_pipe->top_pipe; 1234 } 1235 } 1236 1237 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 1238 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 1239 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 1240 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 1241 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 1242 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 1243 scl->ratios.vert.value != dc_fixpt_one.value 1244 || scl->ratios.horz.value != dc_fixpt_one.value 1245 || scl->ratios.vert_c.value != dc_fixpt_one.value 1246 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 1247 || dc->debug.always_scale; /*support always scale*/ 1248 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 1249 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 1250 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 1251 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 1252 1253 pipes[pipe_cnt].pipe.src.macro_tile_size = 1254 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 1255 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 1256 &pipes[pipe_cnt].pipe.src.sw_mode); 1257 1258 switch (pln->format) { 1259 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 1260 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 1261 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 1262 break; 1263 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 1264 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 1265 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 1266 break; 1267 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 1268 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 1269 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 1270 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 1271 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 1272 break; 1273 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 1274 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 1275 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 1276 break; 1277 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 1278 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 1279 break; 1280 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 1281 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha; 1282 break; 1283 default: 1284 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 1285 break; 1286 } 1287 } 1288 1289 pipe_cnt++; 1290 } 1291 1292 /* populate writeback information */ 1293 DC_FP_START(); 1294 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 1295 DC_FP_END(); 1296 1297 return pipe_cnt; 1298 } 1299 1300 void dcn20_calculate_wm( 1301 struct dc *dc, struct dc_state *context, 1302 display_e2e_pipe_params_st *pipes, 1303 int *out_pipe_cnt, 1304 int *pipe_split_from, 1305 int vlevel, 1306 bool fast_validate) 1307 { 1308 int pipe_cnt, i, pipe_idx; 1309 1310 dc_assert_fp_enabled(); 1311 1312 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1313 if (!context->res_ctx.pipe_ctx[i].stream) 1314 continue; 1315 1316 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1317 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1318 1319 if (pipe_split_from[i] < 0) { 1320 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1321 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1322 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1323 pipes[pipe_cnt].pipe.dest.odm_combine = 1324 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 1325 else 1326 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1327 pipe_idx++; 1328 } else { 1329 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1330 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1331 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1332 pipes[pipe_cnt].pipe.dest.odm_combine = 1333 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 1334 else 1335 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1336 } 1337 1338 if (dc->config.forced_clocks) { 1339 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1340 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1341 } 1342 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 1343 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1344 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 1345 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1346 1347 pipe_cnt++; 1348 } 1349 1350 if (pipe_cnt != pipe_idx) { 1351 if (dc->res_pool->funcs->populate_dml_pipes) 1352 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1353 context, pipes, fast_validate); 1354 else 1355 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 1356 context, pipes, fast_validate); 1357 } 1358 1359 *out_pipe_cnt = pipe_cnt; 1360 1361 pipes[0].clks_cfg.voltage = vlevel; 1362 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 1363 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1364 1365 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1366 if (vlevel < 1) { 1367 pipes[0].clks_cfg.voltage = 1; 1368 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 1369 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 1370 } 1371 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1372 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1373 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1374 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1375 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1376 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1377 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1378 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1379 1380 if (vlevel < 2) { 1381 pipes[0].clks_cfg.voltage = 2; 1382 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 1383 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 1384 } 1385 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1386 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1387 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1388 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1389 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1390 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1391 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1392 1393 if (vlevel < 3) { 1394 pipes[0].clks_cfg.voltage = 3; 1395 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 1396 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 1397 } 1398 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1399 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1400 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1401 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1402 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1403 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1404 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1405 1406 pipes[0].clks_cfg.voltage = vlevel; 1407 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 1408 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1409 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1410 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1411 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1412 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1413 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1414 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1415 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1416 } 1417 1418 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 1419 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 1420 { 1421 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; 1422 int i; 1423 int num_calculated_states = 0; 1424 int min_dcfclk = 0; 1425 1426 dc_assert_fp_enabled(); 1427 1428 if (num_states == 0) 1429 return; 1430 1431 memset(calculated_states, 0, sizeof(calculated_states)); 1432 1433 if (dc->bb_overrides.min_dcfclk_mhz > 0) 1434 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 1435 else { 1436 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 1437 min_dcfclk = 310; 1438 else 1439 // Accounting for SOC/DCF relationship, we can go as high as 1440 // 506Mhz in Vmin. 1441 min_dcfclk = 506; 1442 } 1443 1444 for (i = 0; i < num_states; i++) { 1445 int min_fclk_required_by_uclk; 1446 calculated_states[i].state = i; 1447 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 1448 1449 // FCLK:UCLK ratio is 1.08 1450 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, 1451 1000000); 1452 1453 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 1454 min_dcfclk : min_fclk_required_by_uclk; 1455 1456 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 1457 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 1458 1459 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 1460 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 1461 1462 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 1463 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 1464 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 1465 1466 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 1467 1468 num_calculated_states++; 1469 } 1470 1471 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 1472 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 1473 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 1474 1475 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 1476 bb->num_states = num_calculated_states; 1477 1478 // Duplicate the last state, DML always an extra state identical to max state to work 1479 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 1480 bb->clock_limits[num_calculated_states].state = bb->num_states; 1481 } 1482 1483 void dcn20_cap_soc_clocks( 1484 struct _vcs_dpi_soc_bounding_box_st *bb, 1485 struct pp_smu_nv_clock_table max_clocks) 1486 { 1487 int i; 1488 1489 dc_assert_fp_enabled(); 1490 1491 // First pass - cap all clocks higher than the reported max 1492 for (i = 0; i < bb->num_states; i++) { 1493 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 1494 && max_clocks.dcfClockInKhz != 0) 1495 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 1496 1497 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 1498 && max_clocks.uClockInKhz != 0) 1499 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 1500 1501 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 1502 && max_clocks.fabricClockInKhz != 0) 1503 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 1504 1505 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 1506 && max_clocks.displayClockInKhz != 0) 1507 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 1508 1509 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 1510 && max_clocks.dppClockInKhz != 0) 1511 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 1512 1513 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 1514 && max_clocks.phyClockInKhz != 0) 1515 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 1516 1517 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 1518 && max_clocks.socClockInKhz != 0) 1519 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 1520 1521 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 1522 && max_clocks.dscClockInKhz != 0) 1523 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 1524 } 1525 1526 // Second pass - remove all duplicate clock states 1527 for (i = bb->num_states - 1; i > 1; i--) { 1528 bool duplicate = true; 1529 1530 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 1531 duplicate = false; 1532 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 1533 duplicate = false; 1534 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 1535 duplicate = false; 1536 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 1537 duplicate = false; 1538 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 1539 duplicate = false; 1540 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 1541 duplicate = false; 1542 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 1543 duplicate = false; 1544 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 1545 duplicate = false; 1546 1547 if (duplicate) 1548 bb->num_states--; 1549 } 1550 } 1551 1552 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1553 { 1554 dc_assert_fp_enabled(); 1555 1556 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 1557 && dc->bb_overrides.sr_exit_time_ns) { 1558 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 1559 } 1560 1561 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 1562 != dc->bb_overrides.sr_enter_plus_exit_time_ns 1563 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1564 bb->sr_enter_plus_exit_time_us = 1565 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1566 } 1567 1568 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 1569 && dc->bb_overrides.urgent_latency_ns) { 1570 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1571 } 1572 1573 if ((int)(bb->dram_clock_change_latency_us * 1000) 1574 != dc->bb_overrides.dram_clock_change_latency_ns 1575 && dc->bb_overrides.dram_clock_change_latency_ns) { 1576 bb->dram_clock_change_latency_us = 1577 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1578 } 1579 1580 if ((int)(bb->dummy_pstate_latency_us * 1000) 1581 != dc->bb_overrides.dummy_clock_change_latency_ns 1582 && dc->bb_overrides.dummy_clock_change_latency_ns) { 1583 bb->dummy_pstate_latency_us = 1584 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 1585 } 1586 } 1587 1588 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 1589 bool fast_validate) 1590 { 1591 bool out = false; 1592 1593 BW_VAL_TRACE_SETUP(); 1594 1595 int vlevel = 0; 1596 int pipe_split_from[MAX_PIPES]; 1597 int pipe_cnt = 0; 1598 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 1599 DC_LOGGER_INIT(dc->ctx->logger); 1600 1601 BW_VAL_TRACE_COUNT(); 1602 1603 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1604 1605 if (pipe_cnt == 0) 1606 goto validate_out; 1607 1608 if (!out) 1609 goto validate_fail; 1610 1611 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1612 1613 if (fast_validate) { 1614 BW_VAL_TRACE_SKIP(fast); 1615 goto validate_out; 1616 } 1617 1618 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1619 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1620 1621 BW_VAL_TRACE_END_WATERMARKS(); 1622 1623 goto validate_out; 1624 1625 validate_fail: 1626 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1627 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1628 1629 BW_VAL_TRACE_SKIP(fail); 1630 out = false; 1631 1632 validate_out: 1633 kfree(pipes); 1634 1635 BW_VAL_TRACE_FINISH(); 1636 1637 return out; 1638 } 1639 1640 bool dcn20_validate_bandwidth_fp(struct dc *dc, 1641 struct dc_state *context, 1642 bool fast_validate) 1643 { 1644 bool voltage_supported = false; 1645 bool full_pstate_supported = false; 1646 bool dummy_pstate_supported = false; 1647 double p_state_latency_us; 1648 1649 dc_assert_fp_enabled(); 1650 1651 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 1652 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 1653 dc->debug.disable_dram_clock_change_vactive_support; 1654 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 1655 dc->debug.enable_dram_clock_change_one_display_vactive; 1656 1657 /*Unsafe due to current pipe merge and split logic*/ 1658 ASSERT(context != dc->current_state); 1659 1660 if (fast_validate) { 1661 return dcn20_validate_bandwidth_internal(dc, context, true); 1662 } 1663 1664 // Best case, we support full UCLK switch latency 1665 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1666 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1667 1668 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 1669 (voltage_supported && full_pstate_supported)) { 1670 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 1671 goto restore_dml_state; 1672 } 1673 1674 // Fallback: Try to only support G6 temperature read latency 1675 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 1676 1677 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1678 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1679 1680 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 1681 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 1682 goto restore_dml_state; 1683 } 1684 1685 // ERROR: fallback is supposed to always work. 1686 ASSERT(false); 1687 1688 restore_dml_state: 1689 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 1690 return voltage_supported; 1691 } 1692 1693 void dcn20_fpu_set_wm_ranges(int i, 1694 struct pp_smu_wm_range_sets *ranges, 1695 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1696 { 1697 dc_assert_fp_enabled(); 1698 1699 ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 1700 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 1701 } 1702 1703 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, 1704 int vlevel, 1705 int max_mpc_comb, 1706 int pipe_idx, 1707 bool is_validating_bw) 1708 { 1709 dc_assert_fp_enabled(); 1710 1711 if (is_validating_bw) 1712 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2; 1713 else 1714 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 1715 } 1716 1717 int dcn21_populate_dml_pipes_from_context(struct dc *dc, 1718 struct dc_state *context, 1719 display_e2e_pipe_params_st *pipes, 1720 bool fast_validate) 1721 { 1722 uint32_t pipe_cnt; 1723 int i; 1724 1725 dc_assert_fp_enabled(); 1726 1727 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1728 1729 for (i = 0; i < pipe_cnt; i++) { 1730 1731 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1732 pipes[i].pipe.src.gpuvm = 1; 1733 } 1734 1735 return pipe_cnt; 1736 } 1737 1738 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1739 { 1740 int i; 1741 1742 if (dc->bb_overrides.sr_exit_time_ns) { 1743 for (i = 0; i < WM_SET_COUNT; i++) { 1744 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1745 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1746 } 1747 } 1748 1749 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1750 for (i = 0; i < WM_SET_COUNT; i++) { 1751 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1752 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1753 } 1754 } 1755 1756 if (dc->bb_overrides.urgent_latency_ns) { 1757 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1758 } 1759 1760 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1761 for (i = 0; i < WM_SET_COUNT; i++) { 1762 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1763 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1764 } 1765 } 1766 } 1767 1768 static void calculate_wm_set_for_vlevel(int vlevel, 1769 struct wm_range_table_entry *table_entry, 1770 struct dcn_watermarks *wm_set, 1771 struct display_mode_lib *dml, 1772 display_e2e_pipe_params_st *pipes, 1773 int pipe_cnt) 1774 { 1775 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1776 1777 ASSERT(vlevel < dml->soc.num_states); 1778 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1779 pipes[0].clks_cfg.voltage = vlevel; 1780 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1781 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1782 1783 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1784 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1785 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1786 1787 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1788 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1789 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1790 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1791 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1792 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1793 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1794 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1795 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1796 } 1797 1798 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context, 1799 display_e2e_pipe_params_st *pipes, 1800 int *out_pipe_cnt, 1801 int *pipe_split_from, 1802 int vlevel_req, 1803 bool fast_validate) 1804 { 1805 int pipe_cnt, i, pipe_idx; 1806 int vlevel, vlevel_max; 1807 struct wm_range_table_entry *table_entry; 1808 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1809 1810 ASSERT(bw_params); 1811 1812 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1813 1814 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1815 if (!context->res_ctx.pipe_ctx[i].stream) 1816 continue; 1817 1818 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1819 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1820 1821 if (pipe_split_from[i] < 0) { 1822 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1823 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1824 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1825 pipes[pipe_cnt].pipe.dest.odm_combine = 1826 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1827 else 1828 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1829 pipe_idx++; 1830 } else { 1831 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1832 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1833 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1834 pipes[pipe_cnt].pipe.dest.odm_combine = 1835 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1836 else 1837 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1838 } 1839 pipe_cnt++; 1840 } 1841 1842 if (pipe_cnt != pipe_idx) { 1843 if (dc->res_pool->funcs->populate_dml_pipes) 1844 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1845 context, pipes, fast_validate); 1846 else 1847 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1848 context, pipes, fast_validate); 1849 } 1850 1851 *out_pipe_cnt = pipe_cnt; 1852 1853 vlevel_max = bw_params->clk_table.num_entries - 1; 1854 1855 1856 /* WM Set D */ 1857 table_entry = &bw_params->wm_table.entries[WM_D]; 1858 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1859 vlevel = 0; 1860 else 1861 vlevel = vlevel_max; 1862 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1863 &context->bw_ctx.dml, pipes, pipe_cnt); 1864 /* WM Set C */ 1865 table_entry = &bw_params->wm_table.entries[WM_C]; 1866 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max); 1867 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1868 &context->bw_ctx.dml, pipes, pipe_cnt); 1869 /* WM Set B */ 1870 table_entry = &bw_params->wm_table.entries[WM_B]; 1871 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1872 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1873 &context->bw_ctx.dml, pipes, pipe_cnt); 1874 1875 /* WM Set A */ 1876 table_entry = &bw_params->wm_table.entries[WM_A]; 1877 vlevel = MIN(vlevel_req, vlevel_max); 1878 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1879 &context->bw_ctx.dml, pipes, pipe_cnt); 1880 } 1881 1882 bool dcn21_validate_bandwidth_fp(struct dc *dc, 1883 struct dc_state *context, 1884 bool fast_validate) 1885 { 1886 bool out = false; 1887 1888 BW_VAL_TRACE_SETUP(); 1889 1890 int vlevel = 0; 1891 int pipe_split_from[MAX_PIPES]; 1892 int pipe_cnt = 0; 1893 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 1894 DC_LOGGER_INIT(dc->ctx->logger); 1895 1896 BW_VAL_TRACE_COUNT(); 1897 1898 dc_assert_fp_enabled(); 1899 1900 /*Unsafe due to current pipe merge and split logic*/ 1901 ASSERT(context != dc->current_state); 1902 1903 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1904 1905 if (pipe_cnt == 0) 1906 goto validate_out; 1907 1908 if (!out) 1909 goto validate_fail; 1910 1911 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1912 1913 if (fast_validate) { 1914 BW_VAL_TRACE_SKIP(fast); 1915 goto validate_out; 1916 } 1917 1918 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1919 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1920 1921 BW_VAL_TRACE_END_WATERMARKS(); 1922 1923 goto validate_out; 1924 1925 validate_fail: 1926 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1927 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1928 1929 BW_VAL_TRACE_SKIP(fail); 1930 out = false; 1931 1932 validate_out: 1933 kfree(pipes); 1934 1935 BW_VAL_TRACE_FINISH(); 1936 1937 return out; 1938 } 1939 1940 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl) 1941 { 1942 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl; 1943 int i; 1944 1945 low_pstate_lvl.state = 1; 1946 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1947 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1948 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; 1949 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1950 1951 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; 1952 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; 1953 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps; 1954 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; 1955 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; 1956 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; 1957 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; 1958 1959 for (i = clk_table->num_entries; i > 1; i--) 1960 clk_table->entries[i] = clk_table->entries[i-1]; 1961 clk_table->entries[1] = clk_table->entries[0]; 1962 clk_table->num_entries++; 1963 1964 return low_pstate_lvl; 1965 } 1966 1967 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1968 { 1969 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1970 struct clk_limit_table *clk_table = &bw_params->clk_table; 1971 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1972 unsigned int i, closest_clk_lvl = 0, k = 0; 1973 int j; 1974 1975 dc_assert_fp_enabled(); 1976 1977 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1978 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1979 dcn2_1_soc.num_chans = bw_params->num_channels; 1980 1981 ASSERT(clk_table->num_entries); 1982 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ 1983 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { 1984 clock_limits[i] = dcn2_1_soc.clock_limits[i]; 1985 } 1986 1987 for (i = 0; i < clk_table->num_entries; i++) { 1988 /* loop backwards*/ 1989 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1990 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1991 closest_clk_lvl = j; 1992 break; 1993 } 1994 } 1995 1996 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */ 1997 if (i == 1) 1998 k++; 1999 2000 clock_limits[k].state = k; 2001 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 2002 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 2003 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 2004 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 2005 2006 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 2007 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 2008 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 2009 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 2010 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 2011 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 2012 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 2013 2014 k++; 2015 } 2016 for (i = 0; i < clk_table->num_entries + 1; i++) 2017 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 2018 if (clk_table->num_entries) { 2019 dcn2_1_soc.num_states = clk_table->num_entries + 1; 2020 /* fill in min DF PState */ 2021 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); 2022 /* duplicate last level */ 2023 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 2024 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 2025 } 2026 2027 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 2028 } 2029