1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DM_PP_SMU_IF__H 27 #define DM_PP_SMU_IF__H 28 29 /* 30 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC 31 */ 32 33 typedef bool BOOLEAN; 34 35 enum pp_smu_ver { 36 /* 37 * PP_SMU_INTERFACE_X should be interpreted as the interface defined 38 * starting from X, where X is some family of ASICs. This is as 39 * opposed to interfaces used only for X. There will be some degree 40 * of interface sharing between families of ASIcs. 41 */ 42 PP_SMU_UNSUPPORTED, 43 PP_SMU_VER_RV, 44 45 PP_SMU_VER_MAX 46 }; 47 48 struct pp_smu { 49 enum pp_smu_ver ver; 50 const void *pp; 51 52 /* 53 * interim extra handle for backwards compatibility 54 * as some existing functionality not yet implemented 55 * by ppsmu 56 */ 57 const void *dm; 58 }; 59 60 enum pp_smu_status { 61 PP_SMU_RESULT_UNDEFINED = 0, 62 PP_SMU_RESULT_OK = 1, 63 PP_SMU_RESULT_FAIL, 64 PP_SMU_RESULT_UNSUPPORTED 65 }; 66 67 68 #define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN 0x0 69 #define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX 0xFFFF 70 71 enum wm_type { 72 WM_TYPE_PSTATE_CHG = 0, 73 WM_TYPE_RETRAINING = 1, 74 }; 75 76 /* This structure is a copy of WatermarkRowGeneric_t defined by smuxx_driver_if.h*/ 77 struct pp_smu_wm_set_range { 78 uint16_t min_fill_clk_mhz; 79 uint16_t max_fill_clk_mhz; 80 uint16_t min_drain_clk_mhz; 81 uint16_t max_drain_clk_mhz; 82 83 uint8_t wm_inst; 84 uint8_t wm_type; 85 }; 86 87 #define MAX_WATERMARK_SETS 4 88 89 struct pp_smu_wm_range_sets { 90 unsigned int num_reader_wm_sets; 91 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS]; 92 93 unsigned int num_writer_wm_sets; 94 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS]; 95 }; 96 97 struct pp_smu_funcs_rv { 98 struct pp_smu pp_smu; 99 100 /* PPSMC_MSG_SetDisplayCount 101 * 0 triggers S0i2 optimization 102 */ 103 104 void (*set_display_count)(struct pp_smu *pp, int count); 105 106 /* reader and writer WM's are sent together as part of one table*/ 107 /* 108 * PPSMC_MSG_SetDriverDramAddrHigh 109 * PPSMC_MSG_SetDriverDramAddrLow 110 * PPSMC_MSG_TransferTableDram2Smu 111 * 112 * */ 113 void (*set_wm_ranges)(struct pp_smu *pp, 114 struct pp_smu_wm_range_sets *ranges); 115 116 /* PPSMC_MSG_SetHardMinDcfclkByFreq 117 * fixed clock at requested freq, either from FCH bypass or DFS 118 */ 119 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz); 120 121 /* PPSMC_MSG_SetMinDeepSleepDcfclk 122 * when DF is in cstate, dcf clock is further divided down 123 * to just above given frequency 124 */ 125 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz); 126 127 /* PPSMC_MSG_SetHardMinFclkByFreq 128 * FCLK will vary with DPM, but never below requested hard min 129 */ 130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz); 131 132 /* PPSMC_MSG_SetHardMinSocclkByFreq 133 * Needed for DWB support 134 */ 135 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz); 136 137 /* PME w/a */ 138 void (*set_pme_wa_enable)(struct pp_smu *pp); 139 }; 140 141 struct pp_smu_funcs { 142 struct pp_smu ctx; 143 union { 144 struct pp_smu_funcs_rv rv_funcs; 145 146 }; 147 }; 148 149 #endif /* DM_PP_SMU_IF__H */ 150