1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DM_PP_SMU_IF__H
27 #define DM_PP_SMU_IF__H
28 
29 /*
30  * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
31  */
32 
33 enum pp_smu_ver {
34 	/*
35 	 * PP_SMU_INTERFACE_X should be interpreted as the interface defined
36 	 * starting from X, where X is some family of ASICs.  This is as
37 	 * opposed to interfaces used only for X.  There will be some degree
38 	 * of interface sharing between families of ASIcs.
39 	 */
40 	PP_SMU_UNSUPPORTED,
41 	PP_SMU_VER_RV
42 };
43 
44 struct pp_smu {
45 	enum pp_smu_ver ver;
46 	const void *pp;
47 
48 	/*
49 	 * interim extra handle for backwards compatibility
50 	 * as some existing functionality not yet implemented
51 	 * by ppsmu
52 	 */
53 	const void *dm;
54 };
55 
56 struct pp_smu_wm_set_range {
57 	unsigned int wm_inst;
58 	uint32_t min_fill_clk_mhz;
59 	uint32_t max_fill_clk_mhz;
60 	uint32_t min_drain_clk_mhz;
61 	uint32_t max_drain_clk_mhz;
62 };
63 
64 #define MAX_WATERMARK_SETS 4
65 
66 struct pp_smu_wm_range_sets {
67 	unsigned int num_reader_wm_sets;
68 	struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];
69 
70 	unsigned int num_writer_wm_sets;
71 	struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS];
72 };
73 
74 struct pp_smu_display_requirement_rv {
75 	/* PPSMC_MSG_SetDisplayCount: count
76 	 *  0 triggers S0i2 optimization
77 	 */
78 	unsigned int display_count;
79 
80 	/* PPSMC_MSG_SetHardMinFclkByFreq: mhz
81 	 *  FCLK will vary with DPM, but never below requested hard min
82 	 */
83 	unsigned int hard_min_fclk_mhz;
84 
85 	/* PPSMC_MSG_SetHardMinDcefclkByFreq: mhz
86 	 *  fixed clock at requested freq, either from FCH bypass or DFS
87 	 */
88 	unsigned int hard_min_dcefclk_mhz;
89 
90 	/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
91 	 *  when DF is in cstate, dcf clock is further divided down
92 	 *  to just above given frequency
93 	 */
94 	unsigned int min_deep_sleep_dcefclk_mhz;
95 };
96 
97 struct pp_smu_funcs_rv {
98 	struct pp_smu pp_smu;
99 
100 	/* PPSMC_MSG_SetDisplayCount
101 	 * 0 triggers S0i2 optimization
102 	 */
103 	void (*set_display_count)(struct pp_smu *pp, int count);
104 
105 	/* reader and writer WM's are sent together as part of one table*/
106 	/*
107 	 * PPSMC_MSG_SetDriverDramAddrHigh
108 	 * PPSMC_MSG_SetDriverDramAddrLow
109 	 * PPSMC_MSG_TransferTableDram2Smu
110 	 *
111 	 * */
112 	void (*set_wm_ranges)(struct pp_smu *pp,
113 			struct pp_smu_wm_range_sets *ranges);
114 
115 	/* PPSMC_MSG_SetHardMinDcfclkByFreq
116 	 * fixed clock at requested freq, either from FCH bypass or DFS
117 	 */
118 	void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
119 
120 	/* PPSMC_MSG_SetMinDeepSleepDcfclk
121 	 * when DF is in cstate, dcf clock is further divided down
122 	 * to just above given frequency
123 	 */
124 	void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
125 
126 	/* PPSMC_MSG_SetHardMinFclkByFreq
127 	 * FCLK will vary with DPM, but never below requested hard min
128 	 */
129 	void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
130 
131 	/* PPSMC_MSG_SetHardMinSocclkByFreq
132 	 * Needed for DWB support
133 	 */
134 	void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
135 
136 	/* PME w/a */
137 	void (*set_pme_wa_enable)(struct pp_smu *pp);
138 
139 	/*
140 	 * Legacy functions.  Used for backwards comp. with existing
141 	 * PPlib code.
142 	 */
143 	void (*set_display_requirement)(struct pp_smu *pp,
144 			struct pp_smu_display_requirement_rv *req);
145 };
146 
147 struct pp_smu_funcs {
148 	struct pp_smu ctx;
149 	union {
150 		struct pp_smu_funcs_rv rv_funcs;
151 	};
152 };
153 
154 #endif /* DM_PP_SMU_IF__H */
155