1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DM_PP_SMU_IF__H 27 #define DM_PP_SMU_IF__H 28 29 /* 30 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC 31 */ 32 33 typedef bool BOOLEAN; 34 35 enum pp_smu_ver { 36 /* 37 * PP_SMU_INTERFACE_X should be interpreted as the interface defined 38 * starting from X, where X is some family of ASICs. This is as 39 * opposed to interfaces used only for X. There will be some degree 40 * of interface sharing between families of ASIcs. 41 */ 42 PP_SMU_UNSUPPORTED, 43 PP_SMU_VER_RV, 44 PP_SMU_VER_MAX 45 }; 46 47 struct pp_smu { 48 enum pp_smu_ver ver; 49 const void *pp; 50 51 /* 52 * interim extra handle for backwards compatibility 53 * as some existing functionality not yet implemented 54 * by ppsmu 55 */ 56 const void *dm; 57 }; 58 59 struct pp_smu_wm_set_range { 60 unsigned int wm_inst; 61 uint32_t min_fill_clk_mhz; 62 uint32_t max_fill_clk_mhz; 63 uint32_t min_drain_clk_mhz; 64 uint32_t max_drain_clk_mhz; 65 }; 66 67 #define MAX_WATERMARK_SETS 4 68 69 struct pp_smu_wm_range_sets { 70 unsigned int num_reader_wm_sets; 71 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS]; 72 73 unsigned int num_writer_wm_sets; 74 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS]; 75 }; 76 77 struct pp_smu_funcs_rv { 78 struct pp_smu pp_smu; 79 80 /* PPSMC_MSG_SetDisplayCount 81 * 0 triggers S0i2 optimization 82 */ 83 void (*set_display_count)(struct pp_smu *pp, int count); 84 85 /* reader and writer WM's are sent together as part of one table*/ 86 /* 87 * PPSMC_MSG_SetDriverDramAddrHigh 88 * PPSMC_MSG_SetDriverDramAddrLow 89 * PPSMC_MSG_TransferTableDram2Smu 90 * 91 * */ 92 void (*set_wm_ranges)(struct pp_smu *pp, 93 struct pp_smu_wm_range_sets *ranges); 94 95 /* PPSMC_MSG_SetHardMinDcfclkByFreq 96 * fixed clock at requested freq, either from FCH bypass or DFS 97 */ 98 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz); 99 100 /* PPSMC_MSG_SetMinDeepSleepDcfclk 101 * when DF is in cstate, dcf clock is further divided down 102 * to just above given frequency 103 */ 104 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz); 105 106 /* PPSMC_MSG_SetHardMinFclkByFreq 107 * FCLK will vary with DPM, but never below requested hard min 108 */ 109 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz); 110 111 /* PPSMC_MSG_SetHardMinSocclkByFreq 112 * Needed for DWB support 113 */ 114 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz); 115 116 /* PME w/a */ 117 void (*set_pme_wa_enable)(struct pp_smu *pp); 118 119 }; 120 121 struct pp_smu_funcs { 122 struct pp_smu ctx; 123 union { 124 struct pp_smu_funcs_rv rv_funcs; 125 }; 126 }; 127 128 #endif /* DM_PP_SMU_IF__H */ 129