1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dcn31/dcn31_apg.h" 64 #include "dcn31/dcn31_dio_link_encoder.h" 65 #include "dcn32/dcn32_dio_link_encoder.h" 66 #include "dcn321_dio_link_encoder.h" 67 #include "dce/dce_clock_source.h" 68 #include "dce/dce_audio.h" 69 #include "dce/dce_hwseq.h" 70 #include "clk_mgr.h" 71 #include "virtual/virtual_stream_encoder.h" 72 #include "dml/display_mode_vba.h" 73 #include "dcn32/dcn32_dccg.h" 74 #include "dcn10/dcn10_resource.h" 75 #include "link.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 78 #include "dcn30/dcn30_dwb.h" 79 #include "dcn32/dcn32_mmhubbub.h" 80 81 #include "dcn/dcn_3_2_1_offset.h" 82 #include "dcn/dcn_3_2_1_sh_mask.h" 83 #include "nbio/nbio_4_3_0_offset.h" 84 85 #include "reg_helper.h" 86 #include "dce/dmub_abm.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dce_aux.h" 89 #include "dce/dce_i2c.h" 90 91 #include "dml/dcn30/display_mode_vba_30.h" 92 #include "vm_helper.h" 93 #include "dcn20/dcn20_vmid.h" 94 95 #define DC_LOGGER_INIT(logger) 96 97 enum dcn321_clk_src_array_id { 98 DCN321_CLK_SRC_PLL0, 99 DCN321_CLK_SRC_PLL1, 100 DCN321_CLK_SRC_PLL2, 101 DCN321_CLK_SRC_PLL3, 102 DCN321_CLK_SRC_PLL4, 103 DCN321_CLK_SRC_TOTAL 104 }; 105 106 /* begin ********************* 107 * macros to expend register list macro defined in HW object header file 108 */ 109 110 /* DCN */ 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id)\ 119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR_INIT(reg_name, id, value)\ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 175 .field_name = reg_name ## __ ## field_name ## post_fix 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 183 184 #define NBIO_BASE(seg) \ 185 NBIO_BASE_INNER(seg) 186 187 #define NBIO_SR(reg_name)\ 188 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 #define NBIO_SR_ARR(reg_name, id)\ 191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 192 regBIF_BX0_ ## reg_name 193 194 #define CTX ctx 195 #define REG(reg_name) \ 196 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 197 198 static struct bios_registers bios_regs; 199 200 #define bios_regs_init() \ 201 ( \ 202 NBIO_SR(BIOS_SCRATCH_3),\ 203 NBIO_SR(BIOS_SCRATCH_6)\ 204 ) 205 206 #define clk_src_regs_init(index, pllid)\ 207 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 208 209 static struct dce110_clk_src_regs clk_src_regs[5]; 210 211 static const struct dce110_clk_src_shift cs_shift = { 212 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 213 }; 214 215 static const struct dce110_clk_src_mask cs_mask = { 216 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 217 }; 218 219 #define abm_regs_init(id)\ 220 ABM_DCN32_REG_LIST_RI(id) 221 222 static struct dce_abm_registers abm_regs[4]; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN32(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN32(_MASK) 230 }; 231 232 #define audio_regs_init(id)\ 233 AUD_COMMON_REG_LIST_RI(id) 234 235 static struct dce_audio_registers audio_regs[5]; 236 237 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 238 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 240 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 241 242 static const struct dce_audio_shift audio_shift = { 243 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 244 }; 245 246 static const struct dce_audio_mask audio_mask = { 247 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 248 }; 249 250 #define vpg_regs_init(id)\ 251 VPG_DCN3_REG_LIST_RI(id) 252 253 static struct dcn30_vpg_registers vpg_regs[10]; 254 255 static const struct dcn30_vpg_shift vpg_shift = { 256 DCN3_VPG_MASK_SH_LIST(__SHIFT) 257 }; 258 259 static const struct dcn30_vpg_mask vpg_mask = { 260 DCN3_VPG_MASK_SH_LIST(_MASK) 261 }; 262 263 #define afmt_regs_init(id)\ 264 AFMT_DCN3_REG_LIST_RI(id) 265 266 static struct dcn30_afmt_registers afmt_regs[6]; 267 268 static const struct dcn30_afmt_shift afmt_shift = { 269 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 270 }; 271 272 static const struct dcn30_afmt_mask afmt_mask = { 273 DCN3_AFMT_MASK_SH_LIST(_MASK) 274 }; 275 276 #define apg_regs_init(id)\ 277 APG_DCN31_REG_LIST_RI(id) 278 279 static struct dcn31_apg_registers apg_regs[4]; 280 281 static const struct dcn31_apg_shift apg_shift = { 282 DCN31_APG_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dcn31_apg_mask apg_mask = { 286 DCN31_APG_MASK_SH_LIST(_MASK) 287 }; 288 289 #define stream_enc_regs_init(id)\ 290 SE_DCN32_REG_LIST_RI(id) 291 292 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 293 294 static const struct dcn10_stream_encoder_shift se_shift = { 295 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 296 }; 297 298 static const struct dcn10_stream_encoder_mask se_mask = { 299 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 300 }; 301 302 303 #define aux_regs_init(id)\ 304 DCN2_AUX_REG_LIST_RI(id) 305 306 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 307 308 #define hpd_regs_init(id)\ 309 HPD_REG_LIST_RI(id) 310 311 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 312 313 #define link_regs_init(id, phyid)\ 314 ( \ 315 LE_DCN31_REG_LIST_RI(id), \ 316 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 317 ) 318 /*DPCS_DCN31_REG_LIST(id),*/ \ 319 320 static struct dcn10_link_enc_registers link_enc_regs[5]; 321 322 static const struct dcn10_link_enc_shift le_shift = { 323 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 324 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dcn10_link_enc_mask le_mask = { 328 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 329 // DPCS_DCN31_MASK_SH_LIST(_MASK) 330 }; 331 332 #define hpo_dp_stream_encoder_reg_init(id)\ 333 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 334 335 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 336 337 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 338 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 343 }; 344 345 346 #define hpo_dp_link_encoder_reg_init(id)\ 347 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 352 353 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 354 355 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 356 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 361 }; 362 363 #define dpp_regs_init(id)\ 364 DPP_REG_LIST_DCN30_COMMON_RI(id) 365 366 static struct dcn3_dpp_registers dpp_regs[4]; 367 368 static const struct dcn3_dpp_shift tf_shift = { 369 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 370 }; 371 372 static const struct dcn3_dpp_mask tf_mask = { 373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 374 }; 375 376 377 #define opp_regs_init(id)\ 378 OPP_REG_LIST_DCN30_RI(id) 379 380 static struct dcn20_opp_registers opp_regs[4]; 381 382 static const struct dcn20_opp_shift opp_shift = { 383 OPP_MASK_SH_LIST_DCN20(__SHIFT) 384 }; 385 386 static const struct dcn20_opp_mask opp_mask = { 387 OPP_MASK_SH_LIST_DCN20(_MASK) 388 }; 389 390 #define aux_engine_regs_init(id) \ 391 ( \ 392 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 #define dcn_mpc_regs_init()\ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id) \ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 static const struct dcn_hubp2_shift hubp_shift = { 486 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 487 }; 488 489 static const struct dcn_hubp2_mask hubp_mask = { 490 HUBP_MASK_SH_LIST_DCN32(_MASK) 491 }; 492 493 static struct dcn_hubbub_registers hubbub_reg; 494 #define hubbub_reg_init()\ 495 HUBBUB_REG_LIST_DCN32_RI(0) 496 497 static const struct dcn_hubbub_shift hubbub_shift = { 498 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 499 }; 500 501 static const struct dcn_hubbub_mask hubbub_mask = { 502 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 503 }; 504 505 static struct dccg_registers dccg_regs; 506 507 #define dccg_regs_init()\ 508 DCCG_REG_LIST_DCN32_RI() 509 510 static const struct dccg_shift dccg_shift = { 511 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 512 }; 513 514 static const struct dccg_mask dccg_mask = { 515 DCCG_MASK_SH_LIST_DCN32(_MASK) 516 }; 517 518 519 #define SRII2(reg_name_pre, reg_name_post, id)\ 520 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 521 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 522 reg ## reg_name_pre ## id ## _ ## reg_name_post 523 524 525 #define HWSEQ_DCN32_REG_LIST()\ 526 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 527 SR(DIO_MEM_PWR_CTRL), \ 528 SR(ODM_MEM_PWR_CTRL3), \ 529 SR(MMHUBBUB_MEM_PWR_CNTL), \ 530 SR(DCCG_GATE_DISABLE_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL2), \ 532 SR(DCFCLK_CNTL),\ 533 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 534 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 536 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 542 SR(MICROSECOND_TIME_BASE_DIV), \ 543 SR(MILLISECOND_TIME_BASE_DIV), \ 544 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 545 SR(RBBMIF_TIMEOUT_DIS), \ 546 SR(RBBMIF_TIMEOUT_DIS_2), \ 547 SR(DCHUBBUB_CRC_CTRL), \ 548 SR(DPP_TOP0_DPP_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 551 SR(MPC_CRC_CTRL), \ 552 SR(MPC_CRC_RESULT_GB), \ 553 SR(MPC_CRC_RESULT_C), \ 554 SR(MPC_CRC_RESULT_AR), \ 555 SR(DOMAIN0_PG_CONFIG), \ 556 SR(DOMAIN1_PG_CONFIG), \ 557 SR(DOMAIN2_PG_CONFIG), \ 558 SR(DOMAIN3_PG_CONFIG), \ 559 SR(DOMAIN16_PG_CONFIG), \ 560 SR(DOMAIN17_PG_CONFIG), \ 561 SR(DOMAIN18_PG_CONFIG), \ 562 SR(DOMAIN19_PG_CONFIG), \ 563 SR(DOMAIN0_PG_STATUS), \ 564 SR(DOMAIN1_PG_STATUS), \ 565 SR(DOMAIN2_PG_STATUS), \ 566 SR(DOMAIN3_PG_STATUS), \ 567 SR(DOMAIN16_PG_STATUS), \ 568 SR(DOMAIN17_PG_STATUS), \ 569 SR(DOMAIN18_PG_STATUS), \ 570 SR(DOMAIN19_PG_STATUS), \ 571 SR(D1VGA_CONTROL), \ 572 SR(D2VGA_CONTROL), \ 573 SR(D3VGA_CONTROL), \ 574 SR(D4VGA_CONTROL), \ 575 SR(D5VGA_CONTROL), \ 576 SR(D6VGA_CONTROL), \ 577 SR(DC_IP_REQUEST_CNTL), \ 578 SR(AZALIA_AUDIO_DTO), \ 579 SR(AZALIA_CONTROLLER_CLOCK_GATING) 580 581 static struct dce_hwseq_registers hwseq_reg; 582 583 #define hwseq_reg_init()\ 584 HWSEQ_DCN32_REG_LIST() 585 586 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 587 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 588 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 589 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 591 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 606 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 616 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 618 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 619 620 static const struct dce_hwseq_shift hwseq_shift = { 621 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 622 }; 623 624 static const struct dce_hwseq_mask hwseq_mask = { 625 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 626 }; 627 #define vmid_regs_init(id)\ 628 DCN20_VMID_REG_LIST_RI(id) 629 630 static struct dcn_vmid_registers vmid_regs[16]; 631 632 static const struct dcn20_vmid_shift vmid_shifts = { 633 DCN20_VMID_MASK_SH_LIST(__SHIFT) 634 }; 635 636 static const struct dcn20_vmid_mask vmid_masks = { 637 DCN20_VMID_MASK_SH_LIST(_MASK) 638 }; 639 640 static const struct resource_caps res_cap_dcn321 = { 641 .num_timing_generator = 4, 642 .num_opp = 4, 643 .num_video_plane = 4, 644 .num_audio = 5, 645 .num_stream_encoder = 5, 646 .num_hpo_dp_stream_encoder = 4, 647 .num_hpo_dp_link_encoder = 2, 648 .num_pll = 5, 649 .num_dwb = 1, 650 .num_ddc = 5, 651 .num_vmid = 16, 652 .num_mpc_3dlut = 4, 653 .num_dsc = 4, 654 }; 655 656 static const struct dc_plane_cap plane_cap = { 657 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 658 .per_pixel_alpha = true, 659 660 .pixel_format_support = { 661 .argb8888 = true, 662 .nv12 = true, 663 .fp16 = true, 664 .p010 = true, 665 .ayuv = false, 666 }, 667 668 .max_upscale_factor = { 669 .argb8888 = 16000, 670 .nv12 = 16000, 671 .fp16 = 16000 672 }, 673 674 // 6:1 downscaling ratio: 1000/6 = 166.666 675 .max_downscale_factor = { 676 .argb8888 = 167, 677 .nv12 = 167, 678 .fp16 = 167 679 }, 680 64, 681 64 682 }; 683 684 static const struct dc_debug_options debug_defaults_drv = { 685 .disable_dmcu = true, 686 .force_abm_enable = false, 687 .timing_trace = false, 688 .clock_trace = true, 689 .disable_pplib_clock_request = false, 690 .pipe_split_policy = MPC_SPLIT_AVOID, 691 .force_single_disp_pipe_split = false, 692 .disable_dcc = DCC_ENABLE, 693 .vsr_support = true, 694 .performance_trace = false, 695 .max_downscale_src_width = 7680,/*upto 8K*/ 696 .disable_pplib_wm_range = false, 697 .scl_reset_length10 = true, 698 .sanity_checks = false, 699 .underflow_assert_delay_us = 0xFFFFFFFF, 700 .dwb_fi_phase = -1, // -1 = disable, 701 .dmub_command_table = true, 702 .enable_mem_low_power = { 703 .bits = { 704 .vga = false, 705 .i2c = false, 706 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 707 .dscl = false, 708 .cm = false, 709 .mpc = false, 710 .optc = true, 711 } 712 }, 713 .use_max_lb = true, 714 .force_disable_subvp = false, 715 .exit_idle_opt_for_cursor_updates = true, 716 .enable_single_display_2to1_odm_policy = true, 717 718 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 719 .enable_double_buffered_dsc_pg_support = true, 720 .enable_dp_dig_pixel_rate_div_policy = 1, 721 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 722 .alloc_extra_way_for_cursor = true, 723 .min_prefetch_in_strobe_ns = 60000, // 60us 724 .disable_unbounded_requesting = false, 725 .override_dispclk_programming = true, 726 .disable_fpo_optimizations = false, 727 .fpo_vactive_margin_us = 2000, // 2000us 728 .disable_fpo_vactive = true, 729 .disable_boot_optimizations = false, 730 }; 731 732 static const struct dc_debug_options debug_defaults_diags = { 733 .disable_dmcu = true, 734 .force_abm_enable = false, 735 .timing_trace = true, 736 .clock_trace = true, 737 .disable_dpp_power_gate = true, 738 .disable_hubp_power_gate = true, 739 .disable_dsc_power_gate = true, 740 .disable_clock_gate = true, 741 .disable_pplib_clock_request = true, 742 .disable_pplib_wm_range = true, 743 .disable_stutter = false, 744 .scl_reset_length10 = true, 745 .dwb_fi_phase = -1, // -1 = disable 746 .dmub_command_table = true, 747 .enable_tri_buf = true, 748 .use_max_lb = true, 749 .force_disable_subvp = true, 750 }; 751 752 753 static struct dce_aux *dcn321_aux_engine_create( 754 struct dc_context *ctx, 755 uint32_t inst) 756 { 757 struct aux_engine_dce110 *aux_engine = 758 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 759 760 if (!aux_engine) 761 return NULL; 762 763 #undef REG_STRUCT 764 #define REG_STRUCT aux_engine_regs 765 aux_engine_regs_init(0), 766 aux_engine_regs_init(1), 767 aux_engine_regs_init(2), 768 aux_engine_regs_init(3), 769 aux_engine_regs_init(4); 770 771 dce110_aux_engine_construct(aux_engine, ctx, inst, 772 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 773 &aux_engine_regs[inst], 774 &aux_mask, 775 &aux_shift, 776 ctx->dc->caps.extended_aux_timeout_support); 777 778 return &aux_engine->base; 779 } 780 #define i2c_inst_regs_init(id)\ 781 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 782 783 static struct dce_i2c_registers i2c_hw_regs[5]; 784 785 static const struct dce_i2c_shift i2c_shifts = { 786 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 787 }; 788 789 static const struct dce_i2c_mask i2c_masks = { 790 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 791 }; 792 793 static struct dce_i2c_hw *dcn321_i2c_hw_create( 794 struct dc_context *ctx, 795 uint32_t inst) 796 { 797 struct dce_i2c_hw *dce_i2c_hw = 798 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 799 800 if (!dce_i2c_hw) 801 return NULL; 802 803 #undef REG_STRUCT 804 #define REG_STRUCT i2c_hw_regs 805 i2c_inst_regs_init(1), 806 i2c_inst_regs_init(2), 807 i2c_inst_regs_init(3), 808 i2c_inst_regs_init(4), 809 i2c_inst_regs_init(5); 810 811 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 812 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 813 814 return dce_i2c_hw; 815 } 816 817 static struct clock_source *dcn321_clock_source_create( 818 struct dc_context *ctx, 819 struct dc_bios *bios, 820 enum clock_source_id id, 821 const struct dce110_clk_src_regs *regs, 822 bool dp_clk_src) 823 { 824 struct dce110_clk_src *clk_src = 825 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 826 827 if (!clk_src) 828 return NULL; 829 830 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 831 regs, &cs_shift, &cs_mask)) { 832 clk_src->base.dp_clk_src = dp_clk_src; 833 return &clk_src->base; 834 } 835 836 kfree(clk_src); 837 BREAK_TO_DEBUGGER(); 838 return NULL; 839 } 840 841 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 842 { 843 int i; 844 845 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 846 GFP_KERNEL); 847 848 if (!hubbub2) 849 return NULL; 850 851 #undef REG_STRUCT 852 #define REG_STRUCT hubbub_reg 853 hubbub_reg_init(); 854 855 #undef REG_STRUCT 856 #define REG_STRUCT vmid_regs 857 vmid_regs_init(0), 858 vmid_regs_init(1), 859 vmid_regs_init(2), 860 vmid_regs_init(3), 861 vmid_regs_init(4), 862 vmid_regs_init(5), 863 vmid_regs_init(6), 864 vmid_regs_init(7), 865 vmid_regs_init(8), 866 vmid_regs_init(9), 867 vmid_regs_init(10), 868 vmid_regs_init(11), 869 vmid_regs_init(12), 870 vmid_regs_init(13), 871 vmid_regs_init(14), 872 vmid_regs_init(15); 873 874 hubbub32_construct(hubbub2, ctx, 875 &hubbub_reg, 876 &hubbub_shift, 877 &hubbub_mask, 878 ctx->dc->dml.ip.det_buffer_size_kbytes, 879 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 880 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 881 882 883 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 884 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 885 886 vmid->ctx = ctx; 887 888 vmid->regs = &vmid_regs[i]; 889 vmid->shifts = &vmid_shifts; 890 vmid->masks = &vmid_masks; 891 } 892 893 return &hubbub2->base; 894 } 895 896 static struct hubp *dcn321_hubp_create( 897 struct dc_context *ctx, 898 uint32_t inst) 899 { 900 struct dcn20_hubp *hubp2 = 901 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 902 903 if (!hubp2) 904 return NULL; 905 906 #undef REG_STRUCT 907 #define REG_STRUCT hubp_regs 908 hubp_regs_init(0), 909 hubp_regs_init(1), 910 hubp_regs_init(2), 911 hubp_regs_init(3); 912 913 if (hubp32_construct(hubp2, ctx, inst, 914 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 915 return &hubp2->base; 916 917 BREAK_TO_DEBUGGER(); 918 kfree(hubp2); 919 return NULL; 920 } 921 922 static void dcn321_dpp_destroy(struct dpp **dpp) 923 { 924 kfree(TO_DCN30_DPP(*dpp)); 925 *dpp = NULL; 926 } 927 928 static struct dpp *dcn321_dpp_create( 929 struct dc_context *ctx, 930 uint32_t inst) 931 { 932 struct dcn3_dpp *dpp3 = 933 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 934 935 if (!dpp3) 936 return NULL; 937 938 #undef REG_STRUCT 939 #define REG_STRUCT dpp_regs 940 dpp_regs_init(0), 941 dpp_regs_init(1), 942 dpp_regs_init(2), 943 dpp_regs_init(3); 944 945 if (dpp32_construct(dpp3, ctx, inst, 946 &dpp_regs[inst], &tf_shift, &tf_mask)) 947 return &dpp3->base; 948 949 BREAK_TO_DEBUGGER(); 950 kfree(dpp3); 951 return NULL; 952 } 953 954 static struct mpc *dcn321_mpc_create( 955 struct dc_context *ctx, 956 int num_mpcc, 957 int num_rmu) 958 { 959 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 960 GFP_KERNEL); 961 962 if (!mpc30) 963 return NULL; 964 965 #undef REG_STRUCT 966 #define REG_STRUCT mpc_regs 967 dcn_mpc_regs_init(); 968 969 dcn32_mpc_construct(mpc30, ctx, 970 &mpc_regs, 971 &mpc_shift, 972 &mpc_mask, 973 num_mpcc, 974 num_rmu); 975 976 return &mpc30->base; 977 } 978 979 static struct output_pixel_processor *dcn321_opp_create( 980 struct dc_context *ctx, uint32_t inst) 981 { 982 struct dcn20_opp *opp2 = 983 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 984 985 if (!opp2) { 986 BREAK_TO_DEBUGGER(); 987 return NULL; 988 } 989 990 #undef REG_STRUCT 991 #define REG_STRUCT opp_regs 992 opp_regs_init(0), 993 opp_regs_init(1), 994 opp_regs_init(2), 995 opp_regs_init(3); 996 997 dcn20_opp_construct(opp2, ctx, inst, 998 &opp_regs[inst], &opp_shift, &opp_mask); 999 return &opp2->base; 1000 } 1001 1002 1003 static struct timing_generator *dcn321_timing_generator_create( 1004 struct dc_context *ctx, 1005 uint32_t instance) 1006 { 1007 struct optc *tgn10 = 1008 kzalloc(sizeof(struct optc), GFP_KERNEL); 1009 1010 if (!tgn10) 1011 return NULL; 1012 1013 #undef REG_STRUCT 1014 #define REG_STRUCT optc_regs 1015 optc_regs_init(0), 1016 optc_regs_init(1), 1017 optc_regs_init(2), 1018 optc_regs_init(3); 1019 1020 tgn10->base.inst = instance; 1021 tgn10->base.ctx = ctx; 1022 1023 tgn10->tg_regs = &optc_regs[instance]; 1024 tgn10->tg_shift = &optc_shift; 1025 tgn10->tg_mask = &optc_mask; 1026 1027 dcn32_timing_generator_init(tgn10); 1028 1029 return &tgn10->base; 1030 } 1031 1032 static const struct encoder_feature_support link_enc_feature = { 1033 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1034 .max_hdmi_pixel_clock = 600000, 1035 .hdmi_ycbcr420_supported = true, 1036 .dp_ycbcr420_supported = true, 1037 .fec_supported = true, 1038 .flags.bits.IS_HBR2_CAPABLE = true, 1039 .flags.bits.IS_HBR3_CAPABLE = true, 1040 .flags.bits.IS_TPS3_CAPABLE = true, 1041 .flags.bits.IS_TPS4_CAPABLE = true 1042 }; 1043 1044 static struct link_encoder *dcn321_link_encoder_create( 1045 struct dc_context *ctx, 1046 const struct encoder_init_data *enc_init_data) 1047 { 1048 struct dcn20_link_encoder *enc20 = 1049 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1050 1051 if (!enc20) 1052 return NULL; 1053 1054 #undef REG_STRUCT 1055 #define REG_STRUCT link_enc_aux_regs 1056 aux_regs_init(0), 1057 aux_regs_init(1), 1058 aux_regs_init(2), 1059 aux_regs_init(3), 1060 aux_regs_init(4); 1061 1062 #undef REG_STRUCT 1063 #define REG_STRUCT link_enc_hpd_regs 1064 hpd_regs_init(0), 1065 hpd_regs_init(1), 1066 hpd_regs_init(2), 1067 hpd_regs_init(3), 1068 hpd_regs_init(4); 1069 1070 #undef REG_STRUCT 1071 #define REG_STRUCT link_enc_regs 1072 link_regs_init(0, A), 1073 link_regs_init(1, B), 1074 link_regs_init(2, C), 1075 link_regs_init(3, D), 1076 link_regs_init(4, E); 1077 1078 dcn321_link_encoder_construct(enc20, 1079 enc_init_data, 1080 &link_enc_feature, 1081 &link_enc_regs[enc_init_data->transmitter], 1082 &link_enc_aux_regs[enc_init_data->channel - 1], 1083 &link_enc_hpd_regs[enc_init_data->hpd_source], 1084 &le_shift, 1085 &le_mask); 1086 1087 return &enc20->enc10.base; 1088 } 1089 1090 static void read_dce_straps( 1091 struct dc_context *ctx, 1092 struct resource_straps *straps) 1093 { 1094 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1095 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1096 1097 } 1098 1099 static struct audio *dcn321_create_audio( 1100 struct dc_context *ctx, unsigned int inst) 1101 { 1102 1103 #undef REG_STRUCT 1104 #define REG_STRUCT audio_regs 1105 audio_regs_init(0), 1106 audio_regs_init(1), 1107 audio_regs_init(2), 1108 audio_regs_init(3), 1109 audio_regs_init(4); 1110 1111 return dce_audio_create(ctx, inst, 1112 &audio_regs[inst], &audio_shift, &audio_mask); 1113 } 1114 1115 static struct vpg *dcn321_vpg_create( 1116 struct dc_context *ctx, 1117 uint32_t inst) 1118 { 1119 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1120 1121 if (!vpg3) 1122 return NULL; 1123 1124 #undef REG_STRUCT 1125 #define REG_STRUCT vpg_regs 1126 vpg_regs_init(0), 1127 vpg_regs_init(1), 1128 vpg_regs_init(2), 1129 vpg_regs_init(3), 1130 vpg_regs_init(4), 1131 vpg_regs_init(5), 1132 vpg_regs_init(6), 1133 vpg_regs_init(7), 1134 vpg_regs_init(8), 1135 vpg_regs_init(9); 1136 1137 vpg3_construct(vpg3, ctx, inst, 1138 &vpg_regs[inst], 1139 &vpg_shift, 1140 &vpg_mask); 1141 1142 return &vpg3->base; 1143 } 1144 1145 static struct afmt *dcn321_afmt_create( 1146 struct dc_context *ctx, 1147 uint32_t inst) 1148 { 1149 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1150 1151 if (!afmt3) 1152 return NULL; 1153 1154 #undef REG_STRUCT 1155 #define REG_STRUCT afmt_regs 1156 afmt_regs_init(0), 1157 afmt_regs_init(1), 1158 afmt_regs_init(2), 1159 afmt_regs_init(3), 1160 afmt_regs_init(4), 1161 afmt_regs_init(5); 1162 1163 afmt3_construct(afmt3, ctx, inst, 1164 &afmt_regs[inst], 1165 &afmt_shift, 1166 &afmt_mask); 1167 1168 return &afmt3->base; 1169 } 1170 1171 static struct apg *dcn321_apg_create( 1172 struct dc_context *ctx, 1173 uint32_t inst) 1174 { 1175 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1176 1177 if (!apg31) 1178 return NULL; 1179 1180 #undef REG_STRUCT 1181 #define REG_STRUCT apg_regs 1182 apg_regs_init(0), 1183 apg_regs_init(1), 1184 apg_regs_init(2), 1185 apg_regs_init(3); 1186 1187 apg31_construct(apg31, ctx, inst, 1188 &apg_regs[inst], 1189 &apg_shift, 1190 &apg_mask); 1191 1192 return &apg31->base; 1193 } 1194 1195 static struct stream_encoder *dcn321_stream_encoder_create( 1196 enum engine_id eng_id, 1197 struct dc_context *ctx) 1198 { 1199 struct dcn10_stream_encoder *enc1; 1200 struct vpg *vpg; 1201 struct afmt *afmt; 1202 int vpg_inst; 1203 int afmt_inst; 1204 1205 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1206 if (eng_id <= ENGINE_ID_DIGF) { 1207 vpg_inst = eng_id; 1208 afmt_inst = eng_id; 1209 } else 1210 return NULL; 1211 1212 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1213 vpg = dcn321_vpg_create(ctx, vpg_inst); 1214 afmt = dcn321_afmt_create(ctx, afmt_inst); 1215 1216 if (!enc1 || !vpg || !afmt) { 1217 kfree(enc1); 1218 kfree(vpg); 1219 kfree(afmt); 1220 return NULL; 1221 } 1222 1223 #undef REG_STRUCT 1224 #define REG_STRUCT stream_enc_regs 1225 stream_enc_regs_init(0), 1226 stream_enc_regs_init(1), 1227 stream_enc_regs_init(2), 1228 stream_enc_regs_init(3), 1229 stream_enc_regs_init(4); 1230 1231 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1232 eng_id, vpg, afmt, 1233 &stream_enc_regs[eng_id], 1234 &se_shift, &se_mask); 1235 1236 return &enc1->base; 1237 } 1238 1239 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1240 enum engine_id eng_id, 1241 struct dc_context *ctx) 1242 { 1243 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1244 struct vpg *vpg; 1245 struct apg *apg; 1246 uint32_t hpo_dp_inst; 1247 uint32_t vpg_inst; 1248 uint32_t apg_inst; 1249 1250 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1251 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1252 1253 /* Mapping of VPG register blocks to HPO DP block instance: 1254 * VPG[6] -> HPO_DP[0] 1255 * VPG[7] -> HPO_DP[1] 1256 * VPG[8] -> HPO_DP[2] 1257 * VPG[9] -> HPO_DP[3] 1258 */ 1259 vpg_inst = hpo_dp_inst + 6; 1260 1261 /* Mapping of APG register blocks to HPO DP block instance: 1262 * APG[0] -> HPO_DP[0] 1263 * APG[1] -> HPO_DP[1] 1264 * APG[2] -> HPO_DP[2] 1265 * APG[3] -> HPO_DP[3] 1266 */ 1267 apg_inst = hpo_dp_inst; 1268 1269 /* allocate HPO stream encoder and create VPG sub-block */ 1270 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1271 vpg = dcn321_vpg_create(ctx, vpg_inst); 1272 apg = dcn321_apg_create(ctx, apg_inst); 1273 1274 if (!hpo_dp_enc31 || !vpg || !apg) { 1275 kfree(hpo_dp_enc31); 1276 kfree(vpg); 1277 kfree(apg); 1278 return NULL; 1279 } 1280 1281 #undef REG_STRUCT 1282 #define REG_STRUCT hpo_dp_stream_enc_regs 1283 hpo_dp_stream_encoder_reg_init(0), 1284 hpo_dp_stream_encoder_reg_init(1), 1285 hpo_dp_stream_encoder_reg_init(2), 1286 hpo_dp_stream_encoder_reg_init(3); 1287 1288 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1289 hpo_dp_inst, eng_id, vpg, apg, 1290 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1291 &hpo_dp_se_shift, &hpo_dp_se_mask); 1292 1293 return &hpo_dp_enc31->base; 1294 } 1295 1296 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1297 uint8_t inst, 1298 struct dc_context *ctx) 1299 { 1300 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1301 1302 /* allocate HPO link encoder */ 1303 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1304 1305 #undef REG_STRUCT 1306 #define REG_STRUCT hpo_dp_link_enc_regs 1307 hpo_dp_link_encoder_reg_init(0), 1308 hpo_dp_link_encoder_reg_init(1); 1309 1310 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1311 &hpo_dp_link_enc_regs[inst], 1312 &hpo_dp_le_shift, &hpo_dp_le_mask); 1313 1314 return &hpo_dp_enc31->base; 1315 } 1316 1317 static struct dce_hwseq *dcn321_hwseq_create( 1318 struct dc_context *ctx) 1319 { 1320 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1321 1322 #undef REG_STRUCT 1323 #define REG_STRUCT hwseq_reg 1324 hwseq_reg_init(); 1325 1326 if (hws) { 1327 hws->ctx = ctx; 1328 hws->regs = &hwseq_reg; 1329 hws->shifts = &hwseq_shift; 1330 hws->masks = &hwseq_mask; 1331 } 1332 return hws; 1333 } 1334 static const struct resource_create_funcs res_create_funcs = { 1335 .read_dce_straps = read_dce_straps, 1336 .create_audio = dcn321_create_audio, 1337 .create_stream_encoder = dcn321_stream_encoder_create, 1338 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1339 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1340 .create_hwseq = dcn321_hwseq_create, 1341 }; 1342 1343 static const struct resource_create_funcs res_create_maximus_funcs = { 1344 .read_dce_straps = NULL, 1345 .create_audio = NULL, 1346 .create_stream_encoder = NULL, 1347 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1348 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1349 .create_hwseq = dcn321_hwseq_create, 1350 }; 1351 1352 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1353 { 1354 unsigned int i; 1355 1356 for (i = 0; i < pool->base.stream_enc_count; i++) { 1357 if (pool->base.stream_enc[i] != NULL) { 1358 if (pool->base.stream_enc[i]->vpg != NULL) { 1359 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1360 pool->base.stream_enc[i]->vpg = NULL; 1361 } 1362 if (pool->base.stream_enc[i]->afmt != NULL) { 1363 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1364 pool->base.stream_enc[i]->afmt = NULL; 1365 } 1366 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1367 pool->base.stream_enc[i] = NULL; 1368 } 1369 } 1370 1371 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1372 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1373 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1374 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1375 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1376 } 1377 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1378 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1379 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1380 } 1381 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1382 pool->base.hpo_dp_stream_enc[i] = NULL; 1383 } 1384 } 1385 1386 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1387 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1388 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1389 pool->base.hpo_dp_link_enc[i] = NULL; 1390 } 1391 } 1392 1393 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1394 if (pool->base.dscs[i] != NULL) 1395 dcn20_dsc_destroy(&pool->base.dscs[i]); 1396 } 1397 1398 if (pool->base.mpc != NULL) { 1399 kfree(TO_DCN20_MPC(pool->base.mpc)); 1400 pool->base.mpc = NULL; 1401 } 1402 if (pool->base.hubbub != NULL) { 1403 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1404 pool->base.hubbub = NULL; 1405 } 1406 for (i = 0; i < pool->base.pipe_count; i++) { 1407 if (pool->base.dpps[i] != NULL) 1408 dcn321_dpp_destroy(&pool->base.dpps[i]); 1409 1410 if (pool->base.ipps[i] != NULL) 1411 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1412 1413 if (pool->base.hubps[i] != NULL) { 1414 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1415 pool->base.hubps[i] = NULL; 1416 } 1417 1418 if (pool->base.irqs != NULL) 1419 dal_irq_service_destroy(&pool->base.irqs); 1420 } 1421 1422 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1423 if (pool->base.engines[i] != NULL) 1424 dce110_engine_destroy(&pool->base.engines[i]); 1425 if (pool->base.hw_i2cs[i] != NULL) { 1426 kfree(pool->base.hw_i2cs[i]); 1427 pool->base.hw_i2cs[i] = NULL; 1428 } 1429 if (pool->base.sw_i2cs[i] != NULL) { 1430 kfree(pool->base.sw_i2cs[i]); 1431 pool->base.sw_i2cs[i] = NULL; 1432 } 1433 } 1434 1435 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1436 if (pool->base.opps[i] != NULL) 1437 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1438 } 1439 1440 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1441 if (pool->base.timing_generators[i] != NULL) { 1442 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1443 pool->base.timing_generators[i] = NULL; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1448 if (pool->base.dwbc[i] != NULL) { 1449 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1450 pool->base.dwbc[i] = NULL; 1451 } 1452 if (pool->base.mcif_wb[i] != NULL) { 1453 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1454 pool->base.mcif_wb[i] = NULL; 1455 } 1456 } 1457 1458 for (i = 0; i < pool->base.audio_count; i++) { 1459 if (pool->base.audios[i]) 1460 dce_aud_destroy(&pool->base.audios[i]); 1461 } 1462 1463 for (i = 0; i < pool->base.clk_src_count; i++) { 1464 if (pool->base.clock_sources[i] != NULL) { 1465 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1466 pool->base.clock_sources[i] = NULL; 1467 } 1468 } 1469 1470 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1471 if (pool->base.mpc_lut[i] != NULL) { 1472 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1473 pool->base.mpc_lut[i] = NULL; 1474 } 1475 if (pool->base.mpc_shaper[i] != NULL) { 1476 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1477 pool->base.mpc_shaper[i] = NULL; 1478 } 1479 } 1480 1481 if (pool->base.dp_clock_source != NULL) { 1482 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1483 pool->base.dp_clock_source = NULL; 1484 } 1485 1486 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1487 if (pool->base.multiple_abms[i] != NULL) 1488 dce_abm_destroy(&pool->base.multiple_abms[i]); 1489 } 1490 1491 if (pool->base.psr != NULL) 1492 dmub_psr_destroy(&pool->base.psr); 1493 1494 if (pool->base.dccg != NULL) 1495 dcn_dccg_destroy(&pool->base.dccg); 1496 1497 if (pool->base.oem_device != NULL) { 1498 struct dc *dc = pool->base.oem_device->ctx->dc; 1499 1500 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1501 } 1502 } 1503 1504 1505 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1506 { 1507 int i; 1508 uint32_t dwb_count = pool->res_cap->num_dwb; 1509 1510 for (i = 0; i < dwb_count; i++) { 1511 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1512 GFP_KERNEL); 1513 1514 if (!dwbc30) { 1515 dm_error("DC: failed to create dwbc30!\n"); 1516 return false; 1517 } 1518 1519 #undef REG_STRUCT 1520 #define REG_STRUCT dwbc30_regs 1521 dwbc_regs_dcn3_init(0); 1522 1523 dcn30_dwbc_construct(dwbc30, ctx, 1524 &dwbc30_regs[i], 1525 &dwbc30_shift, 1526 &dwbc30_mask, 1527 i); 1528 1529 pool->dwbc[i] = &dwbc30->base; 1530 } 1531 return true; 1532 } 1533 1534 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1535 { 1536 int i; 1537 uint32_t dwb_count = pool->res_cap->num_dwb; 1538 1539 for (i = 0; i < dwb_count; i++) { 1540 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1541 GFP_KERNEL); 1542 1543 if (!mcif_wb30) { 1544 dm_error("DC: failed to create mcif_wb30!\n"); 1545 return false; 1546 } 1547 1548 #undef REG_STRUCT 1549 #define REG_STRUCT mcif_wb30_regs 1550 mcif_wb_regs_dcn3_init(0); 1551 1552 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1553 &mcif_wb30_regs[i], 1554 &mcif_wb30_shift, 1555 &mcif_wb30_mask, 1556 i); 1557 1558 pool->mcif_wb[i] = &mcif_wb30->base; 1559 } 1560 return true; 1561 } 1562 1563 static struct display_stream_compressor *dcn321_dsc_create( 1564 struct dc_context *ctx, uint32_t inst) 1565 { 1566 struct dcn20_dsc *dsc = 1567 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1568 1569 if (!dsc) { 1570 BREAK_TO_DEBUGGER(); 1571 return NULL; 1572 } 1573 1574 #undef REG_STRUCT 1575 #define REG_STRUCT dsc_regs 1576 dsc_regsDCN20_init(0), 1577 dsc_regsDCN20_init(1), 1578 dsc_regsDCN20_init(2), 1579 dsc_regsDCN20_init(3); 1580 1581 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1582 1583 dsc->max_image_width = 6016; 1584 1585 return &dsc->base; 1586 } 1587 1588 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1589 { 1590 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1591 1592 dcn321_resource_destruct(dcn321_pool); 1593 kfree(dcn321_pool); 1594 *pool = NULL; 1595 } 1596 1597 static struct dc_cap_funcs cap_funcs = { 1598 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1599 }; 1600 1601 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1602 { 1603 DC_FP_START(); 1604 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1605 DC_FP_END(); 1606 } 1607 1608 static struct resource_funcs dcn321_res_pool_funcs = { 1609 .destroy = dcn321_destroy_resource_pool, 1610 .link_enc_create = dcn321_link_encoder_create, 1611 .link_enc_create_minimal = NULL, 1612 .panel_cntl_create = dcn32_panel_cntl_create, 1613 .validate_bandwidth = dcn32_validate_bandwidth, 1614 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1615 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1616 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1617 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1618 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1619 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1620 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1621 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1622 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1623 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1624 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1625 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1626 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1627 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1628 .add_phantom_pipes = dcn32_add_phantom_pipes, 1629 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1630 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 1631 .save_mall_state = dcn32_save_mall_state, 1632 .restore_mall_state = dcn32_restore_mall_state, 1633 }; 1634 1635 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1636 { 1637 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1638 /* DCN321 support max 4 pipes */ 1639 value = value & 0xf; 1640 return value; 1641 } 1642 1643 1644 static bool dcn321_resource_construct( 1645 uint8_t num_virtual_links, 1646 struct dc *dc, 1647 struct dcn321_resource_pool *pool) 1648 { 1649 int i, j; 1650 struct dc_context *ctx = dc->ctx; 1651 struct irq_service_init_data init_data; 1652 struct ddc_service_init_data ddc_init_data = {0}; 1653 uint32_t pipe_fuses = 0; 1654 uint32_t num_pipes = 4; 1655 1656 #undef REG_STRUCT 1657 #define REG_STRUCT bios_regs 1658 bios_regs_init(); 1659 1660 #undef REG_STRUCT 1661 #define REG_STRUCT clk_src_regs 1662 clk_src_regs_init(0, A), 1663 clk_src_regs_init(1, B), 1664 clk_src_regs_init(2, C), 1665 clk_src_regs_init(3, D), 1666 clk_src_regs_init(4, E); 1667 1668 #undef REG_STRUCT 1669 #define REG_STRUCT abm_regs 1670 abm_regs_init(0), 1671 abm_regs_init(1), 1672 abm_regs_init(2), 1673 abm_regs_init(3); 1674 1675 #undef REG_STRUCT 1676 #define REG_STRUCT dccg_regs 1677 dccg_regs_init(); 1678 1679 1680 ctx->dc_bios->regs = &bios_regs; 1681 1682 pool->base.res_cap = &res_cap_dcn321; 1683 /* max number of pipes for ASIC before checking for pipe fuses */ 1684 num_pipes = pool->base.res_cap->num_timing_generator; 1685 pipe_fuses = read_pipe_fuses(ctx); 1686 1687 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1688 if (pipe_fuses & 1 << i) 1689 num_pipes--; 1690 1691 if (pipe_fuses & 1) 1692 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1693 1694 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1695 ASSERT(0); //Entire DCN is harvested! 1696 1697 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1698 * value will be changed, update max_num_dpp and max_num_otg for dml. 1699 */ 1700 dcn3_21_ip.max_num_dpp = num_pipes; 1701 dcn3_21_ip.max_num_otg = num_pipes; 1702 1703 pool->base.funcs = &dcn321_res_pool_funcs; 1704 1705 /************************************************* 1706 * Resource + asic cap harcoding * 1707 *************************************************/ 1708 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1709 pool->base.timing_generator_count = num_pipes; 1710 pool->base.pipe_count = num_pipes; 1711 pool->base.mpcc_count = num_pipes; 1712 dc->caps.max_downscale_ratio = 600; 1713 dc->caps.i2c_speed_in_khz = 100; 1714 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1715 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1716 dc->caps.max_cursor_size = 64; 1717 dc->caps.min_horizontal_blanking_period = 80; 1718 dc->caps.dmdata_alloc_size = 2048; 1719 dc->caps.mall_size_per_mem_channel = 4; 1720 dc->caps.mall_size_total = 0; 1721 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1722 dc->caps.cache_line_size = 64; 1723 dc->caps.cache_num_ways = 16; 1724 1725 /* Calculate the available MALL space */ 1726 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 1727 dc, dc->ctx->dc_bios->vram_info.num_chans) * 1728 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1729 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1730 1731 dc->caps.subvp_fw_processing_delay_us = 15; 1732 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1733 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1734 dc->caps.subvp_swath_height_margin_lines = 16; 1735 dc->caps.subvp_pstate_allow_width_us = 20; 1736 dc->caps.subvp_vertical_int_margin_us = 30; 1737 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1738 dc->caps.max_slave_planes = 1; 1739 dc->caps.max_slave_yuv_planes = 1; 1740 dc->caps.max_slave_rgb_planes = 1; 1741 dc->caps.post_blend_color_processing = true; 1742 dc->caps.force_dp_tps4_for_cp2520 = true; 1743 dc->caps.dp_hpo = true; 1744 dc->caps.dp_hdmi21_pcon_support = true; 1745 dc->caps.edp_dsc_support = true; 1746 dc->caps.extended_aux_timeout_support = true; 1747 dc->caps.dmcub_support = true; 1748 1749 /* Color pipeline capabilities */ 1750 dc->caps.color.dpp.dcn_arch = 1; 1751 dc->caps.color.dpp.input_lut_shared = 0; 1752 dc->caps.color.dpp.icsc = 1; 1753 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1754 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1755 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1756 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1757 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1758 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1759 dc->caps.color.dpp.post_csc = 1; 1760 dc->caps.color.dpp.gamma_corr = 1; 1761 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1762 1763 dc->caps.color.dpp.hw_3d_lut = 1; 1764 dc->caps.color.dpp.ogam_ram = 1; 1765 // no OGAM ROM on DCN2 and later ASICs 1766 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1767 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1768 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1769 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1770 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1771 dc->caps.color.dpp.ocsc = 0; 1772 1773 dc->caps.color.mpc.gamut_remap = 1; 1774 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1775 dc->caps.color.mpc.ogam_ram = 1; 1776 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1777 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1778 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1779 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1780 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1781 dc->caps.color.mpc.ocsc = 1; 1782 1783 /* read VBIOS LTTPR caps */ 1784 { 1785 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1786 enum bp_result bp_query_result; 1787 uint8_t is_vbios_lttpr_enable = 0; 1788 1789 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1790 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1791 } 1792 1793 /* interop bit is implicit */ 1794 { 1795 dc->caps.vbios_lttpr_aware = true; 1796 } 1797 } 1798 1799 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1800 dc->debug = debug_defaults_drv; 1801 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1802 dc->debug = debug_defaults_diags; 1803 } else 1804 dc->debug = debug_defaults_diags; 1805 // Init the vm_helper 1806 if (dc->vm_helper) 1807 vm_helper_init(dc->vm_helper, 16); 1808 1809 /************************************************* 1810 * Create resources * 1811 *************************************************/ 1812 1813 /* Clock Sources for Pixel Clock*/ 1814 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1815 dcn321_clock_source_create(ctx, ctx->dc_bios, 1816 CLOCK_SOURCE_COMBO_PHY_PLL0, 1817 &clk_src_regs[0], false); 1818 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1819 dcn321_clock_source_create(ctx, ctx->dc_bios, 1820 CLOCK_SOURCE_COMBO_PHY_PLL1, 1821 &clk_src_regs[1], false); 1822 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1823 dcn321_clock_source_create(ctx, ctx->dc_bios, 1824 CLOCK_SOURCE_COMBO_PHY_PLL2, 1825 &clk_src_regs[2], false); 1826 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1827 dcn321_clock_source_create(ctx, ctx->dc_bios, 1828 CLOCK_SOURCE_COMBO_PHY_PLL3, 1829 &clk_src_regs[3], false); 1830 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1831 dcn321_clock_source_create(ctx, ctx->dc_bios, 1832 CLOCK_SOURCE_COMBO_PHY_PLL4, 1833 &clk_src_regs[4], false); 1834 1835 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1836 1837 /* todo: not reuse phy_pll registers */ 1838 pool->base.dp_clock_source = 1839 dcn321_clock_source_create(ctx, ctx->dc_bios, 1840 CLOCK_SOURCE_ID_DP_DTO, 1841 &clk_src_regs[0], true); 1842 1843 for (i = 0; i < pool->base.clk_src_count; i++) { 1844 if (pool->base.clock_sources[i] == NULL) { 1845 dm_error("DC: failed to create clock sources!\n"); 1846 BREAK_TO_DEBUGGER(); 1847 goto create_fail; 1848 } 1849 } 1850 1851 /* DCCG */ 1852 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1853 if (pool->base.dccg == NULL) { 1854 dm_error("DC: failed to create dccg!\n"); 1855 BREAK_TO_DEBUGGER(); 1856 goto create_fail; 1857 } 1858 1859 /* DML */ 1860 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1861 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1862 1863 /* IRQ Service */ 1864 init_data.ctx = dc->ctx; 1865 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1866 if (!pool->base.irqs) 1867 goto create_fail; 1868 1869 /* HUBBUB */ 1870 pool->base.hubbub = dcn321_hubbub_create(ctx); 1871 if (pool->base.hubbub == NULL) { 1872 BREAK_TO_DEBUGGER(); 1873 dm_error("DC: failed to create hubbub!\n"); 1874 goto create_fail; 1875 } 1876 1877 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1878 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1879 1880 /* if pipe is disabled, skip instance of HW pipe, 1881 * i.e, skip ASIC register instance 1882 */ 1883 if (pipe_fuses & 1 << i) 1884 continue; 1885 1886 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1887 if (pool->base.hubps[j] == NULL) { 1888 BREAK_TO_DEBUGGER(); 1889 dm_error( 1890 "DC: failed to create hubps!\n"); 1891 goto create_fail; 1892 } 1893 1894 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1895 if (pool->base.dpps[j] == NULL) { 1896 BREAK_TO_DEBUGGER(); 1897 dm_error( 1898 "DC: failed to create dpps!\n"); 1899 goto create_fail; 1900 } 1901 1902 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1903 if (pool->base.opps[j] == NULL) { 1904 BREAK_TO_DEBUGGER(); 1905 dm_error( 1906 "DC: failed to create output pixel processor!\n"); 1907 goto create_fail; 1908 } 1909 1910 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1911 ctx, i); 1912 if (pool->base.timing_generators[j] == NULL) { 1913 BREAK_TO_DEBUGGER(); 1914 dm_error("DC: failed to create tg!\n"); 1915 goto create_fail; 1916 } 1917 1918 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1919 &abm_regs[i], 1920 &abm_shift, 1921 &abm_mask); 1922 if (pool->base.multiple_abms[j] == NULL) { 1923 dm_error("DC: failed to create abm for pipe %d!\n", i); 1924 BREAK_TO_DEBUGGER(); 1925 goto create_fail; 1926 } 1927 1928 /* index for resource pool arrays for next valid pipe */ 1929 j++; 1930 } 1931 1932 /* PSR */ 1933 pool->base.psr = dmub_psr_create(ctx); 1934 if (pool->base.psr == NULL) { 1935 dm_error("DC: failed to create psr obj!\n"); 1936 BREAK_TO_DEBUGGER(); 1937 goto create_fail; 1938 } 1939 1940 /* MPCCs */ 1941 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1942 if (pool->base.mpc == NULL) { 1943 BREAK_TO_DEBUGGER(); 1944 dm_error("DC: failed to create mpc!\n"); 1945 goto create_fail; 1946 } 1947 1948 /* DSCs */ 1949 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1950 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1951 if (pool->base.dscs[i] == NULL) { 1952 BREAK_TO_DEBUGGER(); 1953 dm_error("DC: failed to create display stream compressor %d!\n", i); 1954 goto create_fail; 1955 } 1956 } 1957 1958 /* DWB */ 1959 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1960 BREAK_TO_DEBUGGER(); 1961 dm_error("DC: failed to create dwbc!\n"); 1962 goto create_fail; 1963 } 1964 1965 /* MMHUBBUB */ 1966 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1967 BREAK_TO_DEBUGGER(); 1968 dm_error("DC: failed to create mcif_wb!\n"); 1969 goto create_fail; 1970 } 1971 1972 /* AUX and I2C */ 1973 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1974 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1975 if (pool->base.engines[i] == NULL) { 1976 BREAK_TO_DEBUGGER(); 1977 dm_error( 1978 "DC:failed to create aux engine!!\n"); 1979 goto create_fail; 1980 } 1981 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1982 if (pool->base.hw_i2cs[i] == NULL) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error( 1985 "DC:failed to create hw i2c!!\n"); 1986 goto create_fail; 1987 } 1988 pool->base.sw_i2cs[i] = NULL; 1989 } 1990 1991 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1992 if (!resource_construct(num_virtual_links, dc, &pool->base, 1993 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1994 &res_create_funcs : &res_create_maximus_funcs))) 1995 goto create_fail; 1996 1997 /* HW Sequencer init functions and Plane caps */ 1998 dcn32_hw_sequencer_init_functions(dc); 1999 2000 dc->caps.max_planes = pool->base.pipe_count; 2001 2002 for (i = 0; i < dc->caps.max_planes; ++i) 2003 dc->caps.planes[i] = plane_cap; 2004 2005 dc->cap_funcs = cap_funcs; 2006 2007 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2008 ddc_init_data.ctx = dc->ctx; 2009 ddc_init_data.link = NULL; 2010 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2011 ddc_init_data.id.enum_id = 0; 2012 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2013 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2014 } else { 2015 pool->base.oem_device = NULL; 2016 } 2017 2018 return true; 2019 2020 create_fail: 2021 2022 dcn321_resource_destruct(pool); 2023 2024 return false; 2025 } 2026 2027 struct resource_pool *dcn321_create_resource_pool( 2028 const struct dc_init_data *init_data, 2029 struct dc *dc) 2030 { 2031 struct dcn321_resource_pool *pool = 2032 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2033 2034 if (!pool) 2035 return NULL; 2036 2037 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2038 return &pool->base; 2039 2040 BREAK_TO_DEBUGGER(); 2041 kfree(pool); 2042 return NULL; 2043 } 2044