1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dc_link_dp.h" 64 #include "dcn31/dcn31_apg.h" 65 #include "dcn31/dcn31_dio_link_encoder.h" 66 #include "dcn32/dcn32_dio_link_encoder.h" 67 #include "dcn321_dio_link_encoder.h" 68 #include "dce/dce_clock_source.h" 69 #include "dce/dce_audio.h" 70 #include "dce/dce_hwseq.h" 71 #include "clk_mgr.h" 72 #include "virtual/virtual_stream_encoder.h" 73 #include "dml/display_mode_vba.h" 74 #include "dcn32/dcn32_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "link.h" 77 #include "dcn31/dcn31_panel_cntl.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn32/dcn32_mmhubbub.h" 81 82 #include "dcn/dcn_3_2_1_offset.h" 83 #include "dcn/dcn_3_2_1_sh_mask.h" 84 #include "nbio/nbio_4_3_0_offset.h" 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #define DC_LOGGER_INIT(logger) 97 98 enum dcn321_clk_src_array_id { 99 DCN321_CLK_SRC_PLL0, 100 DCN321_CLK_SRC_PLL1, 101 DCN321_CLK_SRC_PLL2, 102 DCN321_CLK_SRC_PLL3, 103 DCN321_CLK_SRC_PLL4, 104 DCN321_CLK_SRC_TOTAL 105 }; 106 107 /* begin ********************* 108 * macros to expend register list macro defined in HW object header file 109 */ 110 111 /* DCN */ 112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 113 114 #define BASE(seg) BASE_INNER(seg) 115 116 #define SR(reg_name)\ 117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 118 reg ## reg_name 119 #define SR_ARR(reg_name, id)\ 120 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 121 reg ## reg_name 122 #define SR_ARR_INIT(reg_name, id, value)\ 123 REG_STRUCT[id].reg_name = value 124 125 #define SRI(reg_name, block, id)\ 126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SRI_ARR(reg_name, block, id)\ 130 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 131 reg ## block ## id ## _ ## reg_name 132 133 #define SR_ARR_I2C(reg_name, id) \ 134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 135 136 #define SRI_ARR_I2C(reg_name, block, id)\ 137 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 141 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 reg ## block ## id ## _ ## reg_name 143 144 #define SRI2(reg_name, block, id)\ 145 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 146 reg ## reg_name 147 #define SRI2_ARR(reg_name, block, id)\ 148 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 149 reg ## reg_name 150 151 #define SRIR(var_name, reg_name, block, id)\ 152 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII(reg_name, block, id)\ 156 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_ARR_2(reg_name, block, id, inst)\ 160 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_MPC_RMU(reg_name, block, id)\ 164 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRII_DWB(reg_name, temp_name, block, id)\ 168 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 169 reg ## block ## id ## _ ## temp_name 170 171 #define DCCG_SRII(reg_name, block, id)\ 172 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## reg_name 174 175 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 176 .field_name = reg_name ## __ ## field_name ## post_fix 177 178 #define VUPDATE_SRII(reg_name, block, id)\ 179 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 180 reg ## reg_name ## _ ## block ## id 181 182 /* NBIO */ 183 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 184 185 #define NBIO_BASE(seg) \ 186 NBIO_BASE_INNER(seg) 187 188 #define NBIO_SR(reg_name)\ 189 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 190 regBIF_BX0_ ## reg_name 191 #define NBIO_SR_ARR(reg_name, id)\ 192 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 193 regBIF_BX0_ ## reg_name 194 195 #define CTX ctx 196 #define REG(reg_name) \ 197 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 198 199 static struct bios_registers bios_regs; 200 201 #define bios_regs_init() \ 202 ( \ 203 NBIO_SR(BIOS_SCRATCH_3),\ 204 NBIO_SR(BIOS_SCRATCH_6)\ 205 ) 206 207 #define clk_src_regs_init(index, pllid)\ 208 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 209 210 static struct dce110_clk_src_regs clk_src_regs[5]; 211 212 static const struct dce110_clk_src_shift cs_shift = { 213 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 214 }; 215 216 static const struct dce110_clk_src_mask cs_mask = { 217 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 218 }; 219 220 #define abm_regs_init(id)\ 221 ABM_DCN32_REG_LIST_RI(id) 222 223 static struct dce_abm_registers abm_regs[4]; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN32(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN32(_MASK) 231 }; 232 233 #define audio_regs_init(id)\ 234 AUD_COMMON_REG_LIST_RI(id) 235 236 static struct dce_audio_registers audio_regs[5]; 237 238 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 241 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 242 243 static const struct dce_audio_shift audio_shift = { 244 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 245 }; 246 247 static const struct dce_audio_mask audio_mask = { 248 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 249 }; 250 251 #define vpg_regs_init(id)\ 252 VPG_DCN3_REG_LIST_RI(id) 253 254 static struct dcn30_vpg_registers vpg_regs[10]; 255 256 static const struct dcn30_vpg_shift vpg_shift = { 257 DCN3_VPG_MASK_SH_LIST(__SHIFT) 258 }; 259 260 static const struct dcn30_vpg_mask vpg_mask = { 261 DCN3_VPG_MASK_SH_LIST(_MASK) 262 }; 263 264 #define afmt_regs_init(id)\ 265 AFMT_DCN3_REG_LIST_RI(id) 266 267 static struct dcn30_afmt_registers afmt_regs[6]; 268 269 static const struct dcn30_afmt_shift afmt_shift = { 270 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 271 }; 272 273 static const struct dcn30_afmt_mask afmt_mask = { 274 DCN3_AFMT_MASK_SH_LIST(_MASK) 275 }; 276 277 #define apg_regs_init(id)\ 278 APG_DCN31_REG_LIST_RI(id) 279 280 static struct dcn31_apg_registers apg_regs[4]; 281 282 static const struct dcn31_apg_shift apg_shift = { 283 DCN31_APG_MASK_SH_LIST(__SHIFT) 284 }; 285 286 static const struct dcn31_apg_mask apg_mask = { 287 DCN31_APG_MASK_SH_LIST(_MASK) 288 }; 289 290 #define stream_enc_regs_init(id)\ 291 SE_DCN32_REG_LIST_RI(id) 292 293 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 294 295 static const struct dcn10_stream_encoder_shift se_shift = { 296 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 297 }; 298 299 static const struct dcn10_stream_encoder_mask se_mask = { 300 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 301 }; 302 303 304 #define aux_regs_init(id)\ 305 DCN2_AUX_REG_LIST_RI(id) 306 307 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 308 309 #define hpd_regs_init(id)\ 310 HPD_REG_LIST_RI(id) 311 312 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 313 314 #define link_regs_init(id, phyid)\ 315 ( \ 316 LE_DCN31_REG_LIST_RI(id), \ 317 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 318 ) 319 /*DPCS_DCN31_REG_LIST(id),*/ \ 320 321 static struct dcn10_link_enc_registers link_enc_regs[5]; 322 323 static const struct dcn10_link_enc_shift le_shift = { 324 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 325 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 326 }; 327 328 static const struct dcn10_link_enc_mask le_mask = { 329 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 330 // DPCS_DCN31_MASK_SH_LIST(_MASK) 331 }; 332 333 #define hpo_dp_stream_encoder_reg_init(id)\ 334 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 335 336 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 337 338 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 339 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 340 }; 341 342 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 343 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 344 }; 345 346 347 #define hpo_dp_link_encoder_reg_init(id)\ 348 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 349 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 352 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 353 354 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 355 356 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 357 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 358 }; 359 360 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 361 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 362 }; 363 364 #define dpp_regs_init(id)\ 365 DPP_REG_LIST_DCN30_COMMON_RI(id) 366 367 static struct dcn3_dpp_registers dpp_regs[4]; 368 369 static const struct dcn3_dpp_shift tf_shift = { 370 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 371 }; 372 373 static const struct dcn3_dpp_mask tf_mask = { 374 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 375 }; 376 377 378 #define opp_regs_init(id)\ 379 OPP_REG_LIST_DCN30_RI(id) 380 381 static struct dcn20_opp_registers opp_regs[4]; 382 383 static const struct dcn20_opp_shift opp_shift = { 384 OPP_MASK_SH_LIST_DCN20(__SHIFT) 385 }; 386 387 static const struct dcn20_opp_mask opp_mask = { 388 OPP_MASK_SH_LIST_DCN20(_MASK) 389 }; 390 391 #define aux_engine_regs_init(id) \ 392 ( \ 393 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 396 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 397 ) 398 399 static struct dce110_aux_registers aux_engine_regs[5]; 400 401 static const struct dce110_aux_registers_shift aux_shift = { 402 DCN_AUX_MASK_SH_LIST(__SHIFT) 403 }; 404 405 static const struct dce110_aux_registers_mask aux_mask = { 406 DCN_AUX_MASK_SH_LIST(_MASK) 407 }; 408 409 #define dwbc_regs_dcn3_init(id)\ 410 DWBC_COMMON_REG_LIST_DCN30_RI(id) 411 412 static struct dcn30_dwbc_registers dwbc30_regs[1]; 413 414 static const struct dcn30_dwbc_shift dwbc30_shift = { 415 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 416 }; 417 418 static const struct dcn30_dwbc_mask dwbc30_mask = { 419 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 420 }; 421 422 #define mcif_wb_regs_dcn3_init(id)\ 423 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 424 425 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 426 427 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 428 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 429 }; 430 431 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 432 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 433 }; 434 435 #define dsc_regsDCN20_init(id)\ 436 DSC_REG_LIST_DCN20_RI(id) 437 438 static struct dcn20_dsc_registers dsc_regs[4]; 439 440 static const struct dcn20_dsc_shift dsc_shift = { 441 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 442 }; 443 444 static const struct dcn20_dsc_mask dsc_mask = { 445 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 446 }; 447 448 static struct dcn30_mpc_registers mpc_regs; 449 #define dcn_mpc_regs_init()\ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id) \ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 static const struct dcn_hubp2_shift hubp_shift = { 487 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 488 }; 489 490 static const struct dcn_hubp2_mask hubp_mask = { 491 HUBP_MASK_SH_LIST_DCN32(_MASK) 492 }; 493 494 static struct dcn_hubbub_registers hubbub_reg; 495 #define hubbub_reg_init()\ 496 HUBBUB_REG_LIST_DCN32_RI(0) 497 498 static const struct dcn_hubbub_shift hubbub_shift = { 499 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 500 }; 501 502 static const struct dcn_hubbub_mask hubbub_mask = { 503 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 504 }; 505 506 static struct dccg_registers dccg_regs; 507 508 #define dccg_regs_init()\ 509 DCCG_REG_LIST_DCN32_RI() 510 511 static const struct dccg_shift dccg_shift = { 512 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 513 }; 514 515 static const struct dccg_mask dccg_mask = { 516 DCCG_MASK_SH_LIST_DCN32(_MASK) 517 }; 518 519 520 #define SRII2(reg_name_pre, reg_name_post, id)\ 521 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 522 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 523 reg ## reg_name_pre ## id ## _ ## reg_name_post 524 525 526 #define HWSEQ_DCN32_REG_LIST()\ 527 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 528 SR(DIO_MEM_PWR_CTRL), \ 529 SR(ODM_MEM_PWR_CTRL3), \ 530 SR(MMHUBBUB_MEM_PWR_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL2), \ 533 SR(DCFCLK_CNTL),\ 534 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 543 SR(MICROSECOND_TIME_BASE_DIV), \ 544 SR(MILLISECOND_TIME_BASE_DIV), \ 545 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 546 SR(RBBMIF_TIMEOUT_DIS), \ 547 SR(RBBMIF_TIMEOUT_DIS_2), \ 548 SR(DCHUBBUB_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 552 SR(MPC_CRC_CTRL), \ 553 SR(MPC_CRC_RESULT_GB), \ 554 SR(MPC_CRC_RESULT_C), \ 555 SR(MPC_CRC_RESULT_AR), \ 556 SR(DOMAIN0_PG_CONFIG), \ 557 SR(DOMAIN1_PG_CONFIG), \ 558 SR(DOMAIN2_PG_CONFIG), \ 559 SR(DOMAIN3_PG_CONFIG), \ 560 SR(DOMAIN16_PG_CONFIG), \ 561 SR(DOMAIN17_PG_CONFIG), \ 562 SR(DOMAIN18_PG_CONFIG), \ 563 SR(DOMAIN19_PG_CONFIG), \ 564 SR(DOMAIN0_PG_STATUS), \ 565 SR(DOMAIN1_PG_STATUS), \ 566 SR(DOMAIN2_PG_STATUS), \ 567 SR(DOMAIN3_PG_STATUS), \ 568 SR(DOMAIN16_PG_STATUS), \ 569 SR(DOMAIN17_PG_STATUS), \ 570 SR(DOMAIN18_PG_STATUS), \ 571 SR(DOMAIN19_PG_STATUS), \ 572 SR(D1VGA_CONTROL), \ 573 SR(D2VGA_CONTROL), \ 574 SR(D3VGA_CONTROL), \ 575 SR(D4VGA_CONTROL), \ 576 SR(D5VGA_CONTROL), \ 577 SR(D6VGA_CONTROL), \ 578 SR(DC_IP_REQUEST_CNTL), \ 579 SR(AZALIA_AUDIO_DTO), \ 580 SR(AZALIA_CONTROLLER_CLOCK_GATING) 581 582 static struct dce_hwseq_registers hwseq_reg; 583 584 #define hwseq_reg_init()\ 585 HWSEQ_DCN32_REG_LIST() 586 587 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 588 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 589 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 615 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 616 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 619 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 620 621 static const struct dce_hwseq_shift hwseq_shift = { 622 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 623 }; 624 625 static const struct dce_hwseq_mask hwseq_mask = { 626 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 627 }; 628 #define vmid_regs_init(id)\ 629 DCN20_VMID_REG_LIST_RI(id) 630 631 static struct dcn_vmid_registers vmid_regs[16]; 632 633 static const struct dcn20_vmid_shift vmid_shifts = { 634 DCN20_VMID_MASK_SH_LIST(__SHIFT) 635 }; 636 637 static const struct dcn20_vmid_mask vmid_masks = { 638 DCN20_VMID_MASK_SH_LIST(_MASK) 639 }; 640 641 static const struct resource_caps res_cap_dcn321 = { 642 .num_timing_generator = 4, 643 .num_opp = 4, 644 .num_video_plane = 4, 645 .num_audio = 5, 646 .num_stream_encoder = 5, 647 .num_hpo_dp_stream_encoder = 4, 648 .num_hpo_dp_link_encoder = 2, 649 .num_pll = 5, 650 .num_dwb = 1, 651 .num_ddc = 5, 652 .num_vmid = 16, 653 .num_mpc_3dlut = 4, 654 .num_dsc = 4, 655 }; 656 657 static const struct dc_plane_cap plane_cap = { 658 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 659 .blends_with_above = true, 660 .blends_with_below = true, 661 .per_pixel_alpha = true, 662 663 .pixel_format_support = { 664 .argb8888 = true, 665 .nv12 = true, 666 .fp16 = true, 667 .p010 = true, 668 .ayuv = false, 669 }, 670 671 .max_upscale_factor = { 672 .argb8888 = 16000, 673 .nv12 = 16000, 674 .fp16 = 16000 675 }, 676 677 // 6:1 downscaling ratio: 1000/6 = 166.666 678 .max_downscale_factor = { 679 .argb8888 = 167, 680 .nv12 = 167, 681 .fp16 = 167 682 }, 683 64, 684 64 685 }; 686 687 static const struct dc_debug_options debug_defaults_drv = { 688 .disable_dmcu = true, 689 .force_abm_enable = false, 690 .timing_trace = false, 691 .clock_trace = true, 692 .disable_pplib_clock_request = false, 693 .pipe_split_policy = MPC_SPLIT_AVOID, 694 .force_single_disp_pipe_split = false, 695 .disable_dcc = DCC_ENABLE, 696 .vsr_support = true, 697 .performance_trace = false, 698 .max_downscale_src_width = 7680,/*upto 8K*/ 699 .disable_pplib_wm_range = false, 700 .scl_reset_length10 = true, 701 .sanity_checks = false, 702 .underflow_assert_delay_us = 0xFFFFFFFF, 703 .dwb_fi_phase = -1, // -1 = disable, 704 .dmub_command_table = true, 705 .enable_mem_low_power = { 706 .bits = { 707 .vga = false, 708 .i2c = false, 709 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 710 .dscl = false, 711 .cm = false, 712 .mpc = false, 713 .optc = true, 714 } 715 }, 716 .use_max_lb = true, 717 .force_disable_subvp = false, 718 .exit_idle_opt_for_cursor_updates = true, 719 .enable_single_display_2to1_odm_policy = true, 720 721 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 722 .enable_double_buffered_dsc_pg_support = true, 723 .enable_dp_dig_pixel_rate_div_policy = 1, 724 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 725 .alloc_extra_way_for_cursor = true, 726 .min_prefetch_in_strobe_ns = 60000, // 60us 727 .disable_unbounded_requesting = false, 728 }; 729 730 static const struct dc_debug_options debug_defaults_diags = { 731 .disable_dmcu = true, 732 .force_abm_enable = false, 733 .timing_trace = true, 734 .clock_trace = true, 735 .disable_dpp_power_gate = true, 736 .disable_hubp_power_gate = true, 737 .disable_dsc_power_gate = true, 738 .disable_clock_gate = true, 739 .disable_pplib_clock_request = true, 740 .disable_pplib_wm_range = true, 741 .disable_stutter = false, 742 .scl_reset_length10 = true, 743 .dwb_fi_phase = -1, // -1 = disable 744 .dmub_command_table = true, 745 .enable_tri_buf = true, 746 .use_max_lb = true, 747 .force_disable_subvp = true, 748 }; 749 750 751 static struct dce_aux *dcn321_aux_engine_create( 752 struct dc_context *ctx, 753 uint32_t inst) 754 { 755 struct aux_engine_dce110 *aux_engine = 756 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 757 758 if (!aux_engine) 759 return NULL; 760 761 #undef REG_STRUCT 762 #define REG_STRUCT aux_engine_regs 763 aux_engine_regs_init(0), 764 aux_engine_regs_init(1), 765 aux_engine_regs_init(2), 766 aux_engine_regs_init(3), 767 aux_engine_regs_init(4); 768 769 dce110_aux_engine_construct(aux_engine, ctx, inst, 770 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 771 &aux_engine_regs[inst], 772 &aux_mask, 773 &aux_shift, 774 ctx->dc->caps.extended_aux_timeout_support); 775 776 return &aux_engine->base; 777 } 778 #define i2c_inst_regs_init(id)\ 779 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 780 781 static struct dce_i2c_registers i2c_hw_regs[5]; 782 783 static const struct dce_i2c_shift i2c_shifts = { 784 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 785 }; 786 787 static const struct dce_i2c_mask i2c_masks = { 788 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 789 }; 790 791 static struct dce_i2c_hw *dcn321_i2c_hw_create( 792 struct dc_context *ctx, 793 uint32_t inst) 794 { 795 struct dce_i2c_hw *dce_i2c_hw = 796 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 797 798 if (!dce_i2c_hw) 799 return NULL; 800 801 #undef REG_STRUCT 802 #define REG_STRUCT i2c_hw_regs 803 i2c_inst_regs_init(1), 804 i2c_inst_regs_init(2), 805 i2c_inst_regs_init(3), 806 i2c_inst_regs_init(4), 807 i2c_inst_regs_init(5); 808 809 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 810 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 811 812 return dce_i2c_hw; 813 } 814 815 static struct clock_source *dcn321_clock_source_create( 816 struct dc_context *ctx, 817 struct dc_bios *bios, 818 enum clock_source_id id, 819 const struct dce110_clk_src_regs *regs, 820 bool dp_clk_src) 821 { 822 struct dce110_clk_src *clk_src = 823 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 824 825 if (!clk_src) 826 return NULL; 827 828 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 829 regs, &cs_shift, &cs_mask)) { 830 clk_src->base.dp_clk_src = dp_clk_src; 831 return &clk_src->base; 832 } 833 834 kfree(clk_src); 835 BREAK_TO_DEBUGGER(); 836 return NULL; 837 } 838 839 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 840 { 841 int i; 842 843 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 844 GFP_KERNEL); 845 846 if (!hubbub2) 847 return NULL; 848 849 #undef REG_STRUCT 850 #define REG_STRUCT hubbub_reg 851 hubbub_reg_init(); 852 853 #undef REG_STRUCT 854 #define REG_STRUCT vmid_regs 855 vmid_regs_init(0), 856 vmid_regs_init(1), 857 vmid_regs_init(2), 858 vmid_regs_init(3), 859 vmid_regs_init(4), 860 vmid_regs_init(5), 861 vmid_regs_init(6), 862 vmid_regs_init(7), 863 vmid_regs_init(8), 864 vmid_regs_init(9), 865 vmid_regs_init(10), 866 vmid_regs_init(11), 867 vmid_regs_init(12), 868 vmid_regs_init(13), 869 vmid_regs_init(14), 870 vmid_regs_init(15); 871 872 hubbub32_construct(hubbub2, ctx, 873 &hubbub_reg, 874 &hubbub_shift, 875 &hubbub_mask, 876 ctx->dc->dml.ip.det_buffer_size_kbytes, 877 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 878 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 879 880 881 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 882 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 883 884 vmid->ctx = ctx; 885 886 vmid->regs = &vmid_regs[i]; 887 vmid->shifts = &vmid_shifts; 888 vmid->masks = &vmid_masks; 889 } 890 891 return &hubbub2->base; 892 } 893 894 static struct hubp *dcn321_hubp_create( 895 struct dc_context *ctx, 896 uint32_t inst) 897 { 898 struct dcn20_hubp *hubp2 = 899 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 900 901 if (!hubp2) 902 return NULL; 903 904 #undef REG_STRUCT 905 #define REG_STRUCT hubp_regs 906 hubp_regs_init(0), 907 hubp_regs_init(1), 908 hubp_regs_init(2), 909 hubp_regs_init(3); 910 911 if (hubp32_construct(hubp2, ctx, inst, 912 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 913 return &hubp2->base; 914 915 BREAK_TO_DEBUGGER(); 916 kfree(hubp2); 917 return NULL; 918 } 919 920 static void dcn321_dpp_destroy(struct dpp **dpp) 921 { 922 kfree(TO_DCN30_DPP(*dpp)); 923 *dpp = NULL; 924 } 925 926 static struct dpp *dcn321_dpp_create( 927 struct dc_context *ctx, 928 uint32_t inst) 929 { 930 struct dcn3_dpp *dpp3 = 931 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 932 933 if (!dpp3) 934 return NULL; 935 936 #undef REG_STRUCT 937 #define REG_STRUCT dpp_regs 938 dpp_regs_init(0), 939 dpp_regs_init(1), 940 dpp_regs_init(2), 941 dpp_regs_init(3); 942 943 if (dpp32_construct(dpp3, ctx, inst, 944 &dpp_regs[inst], &tf_shift, &tf_mask)) 945 return &dpp3->base; 946 947 BREAK_TO_DEBUGGER(); 948 kfree(dpp3); 949 return NULL; 950 } 951 952 static struct mpc *dcn321_mpc_create( 953 struct dc_context *ctx, 954 int num_mpcc, 955 int num_rmu) 956 { 957 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 958 GFP_KERNEL); 959 960 if (!mpc30) 961 return NULL; 962 963 #undef REG_STRUCT 964 #define REG_STRUCT mpc_regs 965 dcn_mpc_regs_init(); 966 967 dcn32_mpc_construct(mpc30, ctx, 968 &mpc_regs, 969 &mpc_shift, 970 &mpc_mask, 971 num_mpcc, 972 num_rmu); 973 974 return &mpc30->base; 975 } 976 977 static struct output_pixel_processor *dcn321_opp_create( 978 struct dc_context *ctx, uint32_t inst) 979 { 980 struct dcn20_opp *opp2 = 981 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 982 983 if (!opp2) { 984 BREAK_TO_DEBUGGER(); 985 return NULL; 986 } 987 988 #undef REG_STRUCT 989 #define REG_STRUCT opp_regs 990 opp_regs_init(0), 991 opp_regs_init(1), 992 opp_regs_init(2), 993 opp_regs_init(3); 994 995 dcn20_opp_construct(opp2, ctx, inst, 996 &opp_regs[inst], &opp_shift, &opp_mask); 997 return &opp2->base; 998 } 999 1000 1001 static struct timing_generator *dcn321_timing_generator_create( 1002 struct dc_context *ctx, 1003 uint32_t instance) 1004 { 1005 struct optc *tgn10 = 1006 kzalloc(sizeof(struct optc), GFP_KERNEL); 1007 1008 if (!tgn10) 1009 return NULL; 1010 1011 #undef REG_STRUCT 1012 #define REG_STRUCT optc_regs 1013 optc_regs_init(0), 1014 optc_regs_init(1), 1015 optc_regs_init(2), 1016 optc_regs_init(3); 1017 1018 tgn10->base.inst = instance; 1019 tgn10->base.ctx = ctx; 1020 1021 tgn10->tg_regs = &optc_regs[instance]; 1022 tgn10->tg_shift = &optc_shift; 1023 tgn10->tg_mask = &optc_mask; 1024 1025 dcn32_timing_generator_init(tgn10); 1026 1027 return &tgn10->base; 1028 } 1029 1030 static const struct encoder_feature_support link_enc_feature = { 1031 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1032 .max_hdmi_pixel_clock = 600000, 1033 .hdmi_ycbcr420_supported = true, 1034 .dp_ycbcr420_supported = true, 1035 .fec_supported = true, 1036 .flags.bits.IS_HBR2_CAPABLE = true, 1037 .flags.bits.IS_HBR3_CAPABLE = true, 1038 .flags.bits.IS_TPS3_CAPABLE = true, 1039 .flags.bits.IS_TPS4_CAPABLE = true 1040 }; 1041 1042 static struct link_encoder *dcn321_link_encoder_create( 1043 struct dc_context *ctx, 1044 const struct encoder_init_data *enc_init_data) 1045 { 1046 struct dcn20_link_encoder *enc20 = 1047 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1048 1049 if (!enc20) 1050 return NULL; 1051 1052 #undef REG_STRUCT 1053 #define REG_STRUCT link_enc_aux_regs 1054 aux_regs_init(0), 1055 aux_regs_init(1), 1056 aux_regs_init(2), 1057 aux_regs_init(3), 1058 aux_regs_init(4); 1059 1060 #undef REG_STRUCT 1061 #define REG_STRUCT link_enc_hpd_regs 1062 hpd_regs_init(0), 1063 hpd_regs_init(1), 1064 hpd_regs_init(2), 1065 hpd_regs_init(3), 1066 hpd_regs_init(4); 1067 1068 #undef REG_STRUCT 1069 #define REG_STRUCT link_enc_regs 1070 link_regs_init(0, A), 1071 link_regs_init(1, B), 1072 link_regs_init(2, C), 1073 link_regs_init(3, D), 1074 link_regs_init(4, E); 1075 1076 dcn321_link_encoder_construct(enc20, 1077 enc_init_data, 1078 &link_enc_feature, 1079 &link_enc_regs[enc_init_data->transmitter], 1080 &link_enc_aux_regs[enc_init_data->channel - 1], 1081 &link_enc_hpd_regs[enc_init_data->hpd_source], 1082 &le_shift, 1083 &le_mask); 1084 1085 return &enc20->enc10.base; 1086 } 1087 1088 static void read_dce_straps( 1089 struct dc_context *ctx, 1090 struct resource_straps *straps) 1091 { 1092 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1093 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1094 1095 } 1096 1097 static struct audio *dcn321_create_audio( 1098 struct dc_context *ctx, unsigned int inst) 1099 { 1100 1101 #undef REG_STRUCT 1102 #define REG_STRUCT audio_regs 1103 audio_regs_init(0), 1104 audio_regs_init(1), 1105 audio_regs_init(2), 1106 audio_regs_init(3), 1107 audio_regs_init(4); 1108 1109 return dce_audio_create(ctx, inst, 1110 &audio_regs[inst], &audio_shift, &audio_mask); 1111 } 1112 1113 static struct vpg *dcn321_vpg_create( 1114 struct dc_context *ctx, 1115 uint32_t inst) 1116 { 1117 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1118 1119 if (!vpg3) 1120 return NULL; 1121 1122 #undef REG_STRUCT 1123 #define REG_STRUCT vpg_regs 1124 vpg_regs_init(0), 1125 vpg_regs_init(1), 1126 vpg_regs_init(2), 1127 vpg_regs_init(3), 1128 vpg_regs_init(4), 1129 vpg_regs_init(5), 1130 vpg_regs_init(6), 1131 vpg_regs_init(7), 1132 vpg_regs_init(8), 1133 vpg_regs_init(9); 1134 1135 vpg3_construct(vpg3, ctx, inst, 1136 &vpg_regs[inst], 1137 &vpg_shift, 1138 &vpg_mask); 1139 1140 return &vpg3->base; 1141 } 1142 1143 static struct afmt *dcn321_afmt_create( 1144 struct dc_context *ctx, 1145 uint32_t inst) 1146 { 1147 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1148 1149 if (!afmt3) 1150 return NULL; 1151 1152 #undef REG_STRUCT 1153 #define REG_STRUCT afmt_regs 1154 afmt_regs_init(0), 1155 afmt_regs_init(1), 1156 afmt_regs_init(2), 1157 afmt_regs_init(3), 1158 afmt_regs_init(4), 1159 afmt_regs_init(5); 1160 1161 afmt3_construct(afmt3, ctx, inst, 1162 &afmt_regs[inst], 1163 &afmt_shift, 1164 &afmt_mask); 1165 1166 return &afmt3->base; 1167 } 1168 1169 static struct apg *dcn321_apg_create( 1170 struct dc_context *ctx, 1171 uint32_t inst) 1172 { 1173 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1174 1175 if (!apg31) 1176 return NULL; 1177 1178 #undef REG_STRUCT 1179 #define REG_STRUCT apg_regs 1180 apg_regs_init(0), 1181 apg_regs_init(1), 1182 apg_regs_init(2), 1183 apg_regs_init(3); 1184 1185 apg31_construct(apg31, ctx, inst, 1186 &apg_regs[inst], 1187 &apg_shift, 1188 &apg_mask); 1189 1190 return &apg31->base; 1191 } 1192 1193 static struct stream_encoder *dcn321_stream_encoder_create( 1194 enum engine_id eng_id, 1195 struct dc_context *ctx) 1196 { 1197 struct dcn10_stream_encoder *enc1; 1198 struct vpg *vpg; 1199 struct afmt *afmt; 1200 int vpg_inst; 1201 int afmt_inst; 1202 1203 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1204 if (eng_id <= ENGINE_ID_DIGF) { 1205 vpg_inst = eng_id; 1206 afmt_inst = eng_id; 1207 } else 1208 return NULL; 1209 1210 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1211 vpg = dcn321_vpg_create(ctx, vpg_inst); 1212 afmt = dcn321_afmt_create(ctx, afmt_inst); 1213 1214 if (!enc1 || !vpg || !afmt) { 1215 kfree(enc1); 1216 kfree(vpg); 1217 kfree(afmt); 1218 return NULL; 1219 } 1220 1221 #undef REG_STRUCT 1222 #define REG_STRUCT stream_enc_regs 1223 stream_enc_regs_init(0), 1224 stream_enc_regs_init(1), 1225 stream_enc_regs_init(2), 1226 stream_enc_regs_init(3), 1227 stream_enc_regs_init(4); 1228 1229 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1230 eng_id, vpg, afmt, 1231 &stream_enc_regs[eng_id], 1232 &se_shift, &se_mask); 1233 1234 return &enc1->base; 1235 } 1236 1237 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1238 enum engine_id eng_id, 1239 struct dc_context *ctx) 1240 { 1241 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1242 struct vpg *vpg; 1243 struct apg *apg; 1244 uint32_t hpo_dp_inst; 1245 uint32_t vpg_inst; 1246 uint32_t apg_inst; 1247 1248 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1249 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1250 1251 /* Mapping of VPG register blocks to HPO DP block instance: 1252 * VPG[6] -> HPO_DP[0] 1253 * VPG[7] -> HPO_DP[1] 1254 * VPG[8] -> HPO_DP[2] 1255 * VPG[9] -> HPO_DP[3] 1256 */ 1257 vpg_inst = hpo_dp_inst + 6; 1258 1259 /* Mapping of APG register blocks to HPO DP block instance: 1260 * APG[0] -> HPO_DP[0] 1261 * APG[1] -> HPO_DP[1] 1262 * APG[2] -> HPO_DP[2] 1263 * APG[3] -> HPO_DP[3] 1264 */ 1265 apg_inst = hpo_dp_inst; 1266 1267 /* allocate HPO stream encoder and create VPG sub-block */ 1268 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1269 vpg = dcn321_vpg_create(ctx, vpg_inst); 1270 apg = dcn321_apg_create(ctx, apg_inst); 1271 1272 if (!hpo_dp_enc31 || !vpg || !apg) { 1273 kfree(hpo_dp_enc31); 1274 kfree(vpg); 1275 kfree(apg); 1276 return NULL; 1277 } 1278 1279 #undef REG_STRUCT 1280 #define REG_STRUCT hpo_dp_stream_enc_regs 1281 hpo_dp_stream_encoder_reg_init(0), 1282 hpo_dp_stream_encoder_reg_init(1), 1283 hpo_dp_stream_encoder_reg_init(2), 1284 hpo_dp_stream_encoder_reg_init(3); 1285 1286 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1287 hpo_dp_inst, eng_id, vpg, apg, 1288 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1289 &hpo_dp_se_shift, &hpo_dp_se_mask); 1290 1291 return &hpo_dp_enc31->base; 1292 } 1293 1294 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1295 uint8_t inst, 1296 struct dc_context *ctx) 1297 { 1298 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1299 1300 /* allocate HPO link encoder */ 1301 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1302 1303 #undef REG_STRUCT 1304 #define REG_STRUCT hpo_dp_link_enc_regs 1305 hpo_dp_link_encoder_reg_init(0), 1306 hpo_dp_link_encoder_reg_init(1); 1307 1308 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1309 &hpo_dp_link_enc_regs[inst], 1310 &hpo_dp_le_shift, &hpo_dp_le_mask); 1311 1312 return &hpo_dp_enc31->base; 1313 } 1314 1315 static struct dce_hwseq *dcn321_hwseq_create( 1316 struct dc_context *ctx) 1317 { 1318 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1319 1320 #undef REG_STRUCT 1321 #define REG_STRUCT hwseq_reg 1322 hwseq_reg_init(); 1323 1324 if (hws) { 1325 hws->ctx = ctx; 1326 hws->regs = &hwseq_reg; 1327 hws->shifts = &hwseq_shift; 1328 hws->masks = &hwseq_mask; 1329 } 1330 return hws; 1331 } 1332 static const struct resource_create_funcs res_create_funcs = { 1333 .read_dce_straps = read_dce_straps, 1334 .create_audio = dcn321_create_audio, 1335 .create_stream_encoder = dcn321_stream_encoder_create, 1336 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1337 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1338 .create_hwseq = dcn321_hwseq_create, 1339 }; 1340 1341 static const struct resource_create_funcs res_create_maximus_funcs = { 1342 .read_dce_straps = NULL, 1343 .create_audio = NULL, 1344 .create_stream_encoder = NULL, 1345 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1346 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1347 .create_hwseq = dcn321_hwseq_create, 1348 }; 1349 1350 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1351 { 1352 unsigned int i; 1353 1354 for (i = 0; i < pool->base.stream_enc_count; i++) { 1355 if (pool->base.stream_enc[i] != NULL) { 1356 if (pool->base.stream_enc[i]->vpg != NULL) { 1357 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1358 pool->base.stream_enc[i]->vpg = NULL; 1359 } 1360 if (pool->base.stream_enc[i]->afmt != NULL) { 1361 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1362 pool->base.stream_enc[i]->afmt = NULL; 1363 } 1364 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1365 pool->base.stream_enc[i] = NULL; 1366 } 1367 } 1368 1369 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1370 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1371 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1372 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1373 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1374 } 1375 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1376 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1377 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1378 } 1379 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1380 pool->base.hpo_dp_stream_enc[i] = NULL; 1381 } 1382 } 1383 1384 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1385 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1386 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1387 pool->base.hpo_dp_link_enc[i] = NULL; 1388 } 1389 } 1390 1391 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1392 if (pool->base.dscs[i] != NULL) 1393 dcn20_dsc_destroy(&pool->base.dscs[i]); 1394 } 1395 1396 if (pool->base.mpc != NULL) { 1397 kfree(TO_DCN20_MPC(pool->base.mpc)); 1398 pool->base.mpc = NULL; 1399 } 1400 if (pool->base.hubbub != NULL) { 1401 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1402 pool->base.hubbub = NULL; 1403 } 1404 for (i = 0; i < pool->base.pipe_count; i++) { 1405 if (pool->base.dpps[i] != NULL) 1406 dcn321_dpp_destroy(&pool->base.dpps[i]); 1407 1408 if (pool->base.ipps[i] != NULL) 1409 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1410 1411 if (pool->base.hubps[i] != NULL) { 1412 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1413 pool->base.hubps[i] = NULL; 1414 } 1415 1416 if (pool->base.irqs != NULL) 1417 dal_irq_service_destroy(&pool->base.irqs); 1418 } 1419 1420 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1421 if (pool->base.engines[i] != NULL) 1422 dce110_engine_destroy(&pool->base.engines[i]); 1423 if (pool->base.hw_i2cs[i] != NULL) { 1424 kfree(pool->base.hw_i2cs[i]); 1425 pool->base.hw_i2cs[i] = NULL; 1426 } 1427 if (pool->base.sw_i2cs[i] != NULL) { 1428 kfree(pool->base.sw_i2cs[i]); 1429 pool->base.sw_i2cs[i] = NULL; 1430 } 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1434 if (pool->base.opps[i] != NULL) 1435 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1436 } 1437 1438 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1439 if (pool->base.timing_generators[i] != NULL) { 1440 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1441 pool->base.timing_generators[i] = NULL; 1442 } 1443 } 1444 1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1446 if (pool->base.dwbc[i] != NULL) { 1447 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1448 pool->base.dwbc[i] = NULL; 1449 } 1450 if (pool->base.mcif_wb[i] != NULL) { 1451 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1452 pool->base.mcif_wb[i] = NULL; 1453 } 1454 } 1455 1456 for (i = 0; i < pool->base.audio_count; i++) { 1457 if (pool->base.audios[i]) 1458 dce_aud_destroy(&pool->base.audios[i]); 1459 } 1460 1461 for (i = 0; i < pool->base.clk_src_count; i++) { 1462 if (pool->base.clock_sources[i] != NULL) { 1463 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1464 pool->base.clock_sources[i] = NULL; 1465 } 1466 } 1467 1468 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1469 if (pool->base.mpc_lut[i] != NULL) { 1470 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1471 pool->base.mpc_lut[i] = NULL; 1472 } 1473 if (pool->base.mpc_shaper[i] != NULL) { 1474 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1475 pool->base.mpc_shaper[i] = NULL; 1476 } 1477 } 1478 1479 if (pool->base.dp_clock_source != NULL) { 1480 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1481 pool->base.dp_clock_source = NULL; 1482 } 1483 1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1485 if (pool->base.multiple_abms[i] != NULL) 1486 dce_abm_destroy(&pool->base.multiple_abms[i]); 1487 } 1488 1489 if (pool->base.psr != NULL) 1490 dmub_psr_destroy(&pool->base.psr); 1491 1492 if (pool->base.dccg != NULL) 1493 dcn_dccg_destroy(&pool->base.dccg); 1494 1495 if (pool->base.oem_device != NULL) 1496 link_destroy_ddc_service(&pool->base.oem_device); 1497 } 1498 1499 1500 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1501 { 1502 int i; 1503 uint32_t dwb_count = pool->res_cap->num_dwb; 1504 1505 for (i = 0; i < dwb_count; i++) { 1506 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1507 GFP_KERNEL); 1508 1509 if (!dwbc30) { 1510 dm_error("DC: failed to create dwbc30!\n"); 1511 return false; 1512 } 1513 1514 #undef REG_STRUCT 1515 #define REG_STRUCT dwbc30_regs 1516 dwbc_regs_dcn3_init(0); 1517 1518 dcn30_dwbc_construct(dwbc30, ctx, 1519 &dwbc30_regs[i], 1520 &dwbc30_shift, 1521 &dwbc30_mask, 1522 i); 1523 1524 pool->dwbc[i] = &dwbc30->base; 1525 } 1526 return true; 1527 } 1528 1529 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1530 { 1531 int i; 1532 uint32_t dwb_count = pool->res_cap->num_dwb; 1533 1534 for (i = 0; i < dwb_count; i++) { 1535 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1536 GFP_KERNEL); 1537 1538 if (!mcif_wb30) { 1539 dm_error("DC: failed to create mcif_wb30!\n"); 1540 return false; 1541 } 1542 1543 #undef REG_STRUCT 1544 #define REG_STRUCT mcif_wb30_regs 1545 mcif_wb_regs_dcn3_init(0); 1546 1547 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1548 &mcif_wb30_regs[i], 1549 &mcif_wb30_shift, 1550 &mcif_wb30_mask, 1551 i); 1552 1553 pool->mcif_wb[i] = &mcif_wb30->base; 1554 } 1555 return true; 1556 } 1557 1558 static struct display_stream_compressor *dcn321_dsc_create( 1559 struct dc_context *ctx, uint32_t inst) 1560 { 1561 struct dcn20_dsc *dsc = 1562 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1563 1564 if (!dsc) { 1565 BREAK_TO_DEBUGGER(); 1566 return NULL; 1567 } 1568 1569 #undef REG_STRUCT 1570 #define REG_STRUCT dsc_regs 1571 dsc_regsDCN20_init(0), 1572 dsc_regsDCN20_init(1), 1573 dsc_regsDCN20_init(2), 1574 dsc_regsDCN20_init(3); 1575 1576 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1577 1578 dsc->max_image_width = 6016; 1579 1580 return &dsc->base; 1581 } 1582 1583 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1584 { 1585 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1586 1587 dcn321_resource_destruct(dcn321_pool); 1588 kfree(dcn321_pool); 1589 *pool = NULL; 1590 } 1591 1592 static struct dc_cap_funcs cap_funcs = { 1593 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1594 }; 1595 1596 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1597 { 1598 DC_FP_START(); 1599 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1600 DC_FP_END(); 1601 } 1602 1603 static struct resource_funcs dcn321_res_pool_funcs = { 1604 .destroy = dcn321_destroy_resource_pool, 1605 .link_enc_create = dcn321_link_encoder_create, 1606 .link_enc_create_minimal = NULL, 1607 .panel_cntl_create = dcn32_panel_cntl_create, 1608 .validate_bandwidth = dcn32_validate_bandwidth, 1609 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1610 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1611 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1612 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1613 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1614 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1615 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1616 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1617 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1618 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1619 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1620 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1621 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1622 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1623 .add_phantom_pipes = dcn32_add_phantom_pipes, 1624 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1625 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 1626 .save_mall_state = dcn32_save_mall_state, 1627 .restore_mall_state = dcn32_restore_mall_state, 1628 }; 1629 1630 1631 static bool dcn321_resource_construct( 1632 uint8_t num_virtual_links, 1633 struct dc *dc, 1634 struct dcn321_resource_pool *pool) 1635 { 1636 int i, j; 1637 struct dc_context *ctx = dc->ctx; 1638 struct irq_service_init_data init_data; 1639 struct ddc_service_init_data ddc_init_data = {0}; 1640 uint32_t pipe_fuses = 0; 1641 uint32_t num_pipes = 4; 1642 1643 #undef REG_STRUCT 1644 #define REG_STRUCT bios_regs 1645 bios_regs_init(); 1646 1647 #undef REG_STRUCT 1648 #define REG_STRUCT clk_src_regs 1649 clk_src_regs_init(0, A), 1650 clk_src_regs_init(1, B), 1651 clk_src_regs_init(2, C), 1652 clk_src_regs_init(3, D), 1653 clk_src_regs_init(4, E); 1654 1655 #undef REG_STRUCT 1656 #define REG_STRUCT abm_regs 1657 abm_regs_init(0), 1658 abm_regs_init(1), 1659 abm_regs_init(2), 1660 abm_regs_init(3); 1661 1662 #undef REG_STRUCT 1663 #define REG_STRUCT dccg_regs 1664 dccg_regs_init(); 1665 1666 1667 ctx->dc_bios->regs = &bios_regs; 1668 1669 pool->base.res_cap = &res_cap_dcn321; 1670 /* max number of pipes for ASIC before checking for pipe fuses */ 1671 num_pipes = pool->base.res_cap->num_timing_generator; 1672 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1673 1674 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1675 if (pipe_fuses & 1 << i) 1676 num_pipes--; 1677 1678 if (pipe_fuses & 1) 1679 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1680 1681 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1682 ASSERT(0); //Entire DCN is harvested! 1683 1684 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1685 * value will be changed, update max_num_dpp and max_num_otg for dml. 1686 */ 1687 dcn3_21_ip.max_num_dpp = num_pipes; 1688 dcn3_21_ip.max_num_otg = num_pipes; 1689 1690 pool->base.funcs = &dcn321_res_pool_funcs; 1691 1692 /************************************************* 1693 * Resource + asic cap harcoding * 1694 *************************************************/ 1695 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1696 pool->base.timing_generator_count = num_pipes; 1697 pool->base.pipe_count = num_pipes; 1698 pool->base.mpcc_count = num_pipes; 1699 dc->caps.max_downscale_ratio = 600; 1700 dc->caps.i2c_speed_in_khz = 100; 1701 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1702 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1703 dc->caps.max_cursor_size = 64; 1704 dc->caps.min_horizontal_blanking_period = 80; 1705 dc->caps.dmdata_alloc_size = 2048; 1706 dc->caps.mall_size_per_mem_channel = 4; 1707 dc->caps.mall_size_total = 0; 1708 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1709 dc->caps.cache_line_size = 64; 1710 dc->caps.cache_num_ways = 16; 1711 1712 /* Calculate the available MALL space */ 1713 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 1714 dc, dc->ctx->dc_bios->vram_info.num_chans) * 1715 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1716 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1717 1718 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 1719 dc->caps.subvp_fw_processing_delay_us = 15; 1720 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1721 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1722 dc->caps.subvp_swath_height_margin_lines = 16; 1723 dc->caps.subvp_pstate_allow_width_us = 20; 1724 dc->caps.subvp_vertical_int_margin_us = 30; 1725 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1726 dc->caps.max_slave_planes = 1; 1727 dc->caps.max_slave_yuv_planes = 1; 1728 dc->caps.max_slave_rgb_planes = 1; 1729 dc->caps.post_blend_color_processing = true; 1730 dc->caps.force_dp_tps4_for_cp2520 = true; 1731 dc->caps.dp_hpo = true; 1732 dc->caps.dp_hdmi21_pcon_support = true; 1733 dc->caps.edp_dsc_support = true; 1734 dc->caps.extended_aux_timeout_support = true; 1735 dc->caps.dmcub_support = true; 1736 1737 /* Color pipeline capabilities */ 1738 dc->caps.color.dpp.dcn_arch = 1; 1739 dc->caps.color.dpp.input_lut_shared = 0; 1740 dc->caps.color.dpp.icsc = 1; 1741 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1742 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1743 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1744 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1745 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1746 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1747 dc->caps.color.dpp.post_csc = 1; 1748 dc->caps.color.dpp.gamma_corr = 1; 1749 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1750 1751 dc->caps.color.dpp.hw_3d_lut = 1; 1752 dc->caps.color.dpp.ogam_ram = 1; 1753 // no OGAM ROM on DCN2 and later ASICs 1754 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1755 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1756 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1757 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1758 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1759 dc->caps.color.dpp.ocsc = 0; 1760 1761 dc->caps.color.mpc.gamut_remap = 1; 1762 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1763 dc->caps.color.mpc.ogam_ram = 1; 1764 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1765 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1766 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1767 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1768 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1769 dc->caps.color.mpc.ocsc = 1; 1770 1771 /* read VBIOS LTTPR caps */ 1772 { 1773 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1774 enum bp_result bp_query_result; 1775 uint8_t is_vbios_lttpr_enable = 0; 1776 1777 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1778 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1779 } 1780 1781 /* interop bit is implicit */ 1782 { 1783 dc->caps.vbios_lttpr_aware = true; 1784 } 1785 } 1786 1787 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1788 dc->debug = debug_defaults_drv; 1789 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1790 dc->debug = debug_defaults_diags; 1791 } else 1792 dc->debug = debug_defaults_diags; 1793 // Init the vm_helper 1794 if (dc->vm_helper) 1795 vm_helper_init(dc->vm_helper, 16); 1796 1797 /************************************************* 1798 * Create resources * 1799 *************************************************/ 1800 1801 /* Clock Sources for Pixel Clock*/ 1802 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1803 dcn321_clock_source_create(ctx, ctx->dc_bios, 1804 CLOCK_SOURCE_COMBO_PHY_PLL0, 1805 &clk_src_regs[0], false); 1806 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1807 dcn321_clock_source_create(ctx, ctx->dc_bios, 1808 CLOCK_SOURCE_COMBO_PHY_PLL1, 1809 &clk_src_regs[1], false); 1810 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1811 dcn321_clock_source_create(ctx, ctx->dc_bios, 1812 CLOCK_SOURCE_COMBO_PHY_PLL2, 1813 &clk_src_regs[2], false); 1814 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1815 dcn321_clock_source_create(ctx, ctx->dc_bios, 1816 CLOCK_SOURCE_COMBO_PHY_PLL3, 1817 &clk_src_regs[3], false); 1818 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1819 dcn321_clock_source_create(ctx, ctx->dc_bios, 1820 CLOCK_SOURCE_COMBO_PHY_PLL4, 1821 &clk_src_regs[4], false); 1822 1823 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1824 1825 /* todo: not reuse phy_pll registers */ 1826 pool->base.dp_clock_source = 1827 dcn321_clock_source_create(ctx, ctx->dc_bios, 1828 CLOCK_SOURCE_ID_DP_DTO, 1829 &clk_src_regs[0], true); 1830 1831 for (i = 0; i < pool->base.clk_src_count; i++) { 1832 if (pool->base.clock_sources[i] == NULL) { 1833 dm_error("DC: failed to create clock sources!\n"); 1834 BREAK_TO_DEBUGGER(); 1835 goto create_fail; 1836 } 1837 } 1838 1839 /* DCCG */ 1840 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1841 if (pool->base.dccg == NULL) { 1842 dm_error("DC: failed to create dccg!\n"); 1843 BREAK_TO_DEBUGGER(); 1844 goto create_fail; 1845 } 1846 1847 /* DML */ 1848 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1849 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1850 1851 /* IRQ Service */ 1852 init_data.ctx = dc->ctx; 1853 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1854 if (!pool->base.irqs) 1855 goto create_fail; 1856 1857 /* HUBBUB */ 1858 pool->base.hubbub = dcn321_hubbub_create(ctx); 1859 if (pool->base.hubbub == NULL) { 1860 BREAK_TO_DEBUGGER(); 1861 dm_error("DC: failed to create hubbub!\n"); 1862 goto create_fail; 1863 } 1864 1865 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1866 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1867 1868 /* if pipe is disabled, skip instance of HW pipe, 1869 * i.e, skip ASIC register instance 1870 */ 1871 if (pipe_fuses & 1 << i) 1872 continue; 1873 1874 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1875 if (pool->base.hubps[j] == NULL) { 1876 BREAK_TO_DEBUGGER(); 1877 dm_error( 1878 "DC: failed to create hubps!\n"); 1879 goto create_fail; 1880 } 1881 1882 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1883 if (pool->base.dpps[j] == NULL) { 1884 BREAK_TO_DEBUGGER(); 1885 dm_error( 1886 "DC: failed to create dpps!\n"); 1887 goto create_fail; 1888 } 1889 1890 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1891 if (pool->base.opps[j] == NULL) { 1892 BREAK_TO_DEBUGGER(); 1893 dm_error( 1894 "DC: failed to create output pixel processor!\n"); 1895 goto create_fail; 1896 } 1897 1898 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1899 ctx, i); 1900 if (pool->base.timing_generators[j] == NULL) { 1901 BREAK_TO_DEBUGGER(); 1902 dm_error("DC: failed to create tg!\n"); 1903 goto create_fail; 1904 } 1905 1906 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1907 &abm_regs[i], 1908 &abm_shift, 1909 &abm_mask); 1910 if (pool->base.multiple_abms[j] == NULL) { 1911 dm_error("DC: failed to create abm for pipe %d!\n", i); 1912 BREAK_TO_DEBUGGER(); 1913 goto create_fail; 1914 } 1915 1916 /* index for resource pool arrays for next valid pipe */ 1917 j++; 1918 } 1919 1920 /* PSR */ 1921 pool->base.psr = dmub_psr_create(ctx); 1922 if (pool->base.psr == NULL) { 1923 dm_error("DC: failed to create psr obj!\n"); 1924 BREAK_TO_DEBUGGER(); 1925 goto create_fail; 1926 } 1927 1928 /* MPCCs */ 1929 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1930 if (pool->base.mpc == NULL) { 1931 BREAK_TO_DEBUGGER(); 1932 dm_error("DC: failed to create mpc!\n"); 1933 goto create_fail; 1934 } 1935 1936 /* DSCs */ 1937 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1938 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1939 if (pool->base.dscs[i] == NULL) { 1940 BREAK_TO_DEBUGGER(); 1941 dm_error("DC: failed to create display stream compressor %d!\n", i); 1942 goto create_fail; 1943 } 1944 } 1945 1946 /* DWB */ 1947 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1948 BREAK_TO_DEBUGGER(); 1949 dm_error("DC: failed to create dwbc!\n"); 1950 goto create_fail; 1951 } 1952 1953 /* MMHUBBUB */ 1954 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1955 BREAK_TO_DEBUGGER(); 1956 dm_error("DC: failed to create mcif_wb!\n"); 1957 goto create_fail; 1958 } 1959 1960 /* AUX and I2C */ 1961 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1962 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1963 if (pool->base.engines[i] == NULL) { 1964 BREAK_TO_DEBUGGER(); 1965 dm_error( 1966 "DC:failed to create aux engine!!\n"); 1967 goto create_fail; 1968 } 1969 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1970 if (pool->base.hw_i2cs[i] == NULL) { 1971 BREAK_TO_DEBUGGER(); 1972 dm_error( 1973 "DC:failed to create hw i2c!!\n"); 1974 goto create_fail; 1975 } 1976 pool->base.sw_i2cs[i] = NULL; 1977 } 1978 1979 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1980 if (!resource_construct(num_virtual_links, dc, &pool->base, 1981 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1982 &res_create_funcs : &res_create_maximus_funcs))) 1983 goto create_fail; 1984 1985 /* HW Sequencer init functions and Plane caps */ 1986 dcn32_hw_sequencer_init_functions(dc); 1987 1988 dc->caps.max_planes = pool->base.pipe_count; 1989 1990 for (i = 0; i < dc->caps.max_planes; ++i) 1991 dc->caps.planes[i] = plane_cap; 1992 1993 dc->cap_funcs = cap_funcs; 1994 1995 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1996 ddc_init_data.ctx = dc->ctx; 1997 ddc_init_data.link = NULL; 1998 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1999 ddc_init_data.id.enum_id = 0; 2000 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2001 pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2002 } else { 2003 pool->base.oem_device = NULL; 2004 } 2005 2006 return true; 2007 2008 create_fail: 2009 2010 dcn321_resource_destruct(pool); 2011 2012 return false; 2013 } 2014 2015 struct resource_pool *dcn321_create_resource_pool( 2016 const struct dc_init_data *init_data, 2017 struct dc *dc) 2018 { 2019 struct dcn321_resource_pool *pool = 2020 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2021 2022 if (!pool) 2023 return NULL; 2024 2025 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2026 return &pool->base; 2027 2028 BREAK_TO_DEBUGGER(); 2029 kfree(pool); 2030 return NULL; 2031 } 2032