1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dc_link_dp.h" 64 #include "dcn31/dcn31_apg.h" 65 #include "dcn31/dcn31_dio_link_encoder.h" 66 #include "dcn32/dcn32_dio_link_encoder.h" 67 #include "dcn321_dio_link_encoder.h" 68 #include "dce/dce_clock_source.h" 69 #include "dce/dce_audio.h" 70 #include "dce/dce_hwseq.h" 71 #include "clk_mgr.h" 72 #include "virtual/virtual_stream_encoder.h" 73 #include "dml/display_mode_vba.h" 74 #include "dcn32/dcn32_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dc_link_ddc.h" 77 #include "dcn31/dcn31_panel_cntl.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn32/dcn32_mmhubbub.h" 81 82 #include "dcn/dcn_3_2_1_offset.h" 83 #include "dcn/dcn_3_2_1_sh_mask.h" 84 #include "nbio/nbio_4_3_0_offset.h" 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #define DC_LOGGER_INIT(logger) 97 98 enum dcn321_clk_src_array_id { 99 DCN321_CLK_SRC_PLL0, 100 DCN321_CLK_SRC_PLL1, 101 DCN321_CLK_SRC_PLL2, 102 DCN321_CLK_SRC_PLL3, 103 DCN321_CLK_SRC_PLL4, 104 DCN321_CLK_SRC_TOTAL 105 }; 106 107 /* begin ********************* 108 * macros to expend register list macro defined in HW object header file 109 */ 110 111 /* DCN */ 112 /* TODO awful hack. fixup dcn20_dwb.h */ 113 #undef BASE_INNER 114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 115 116 #define BASE(seg) BASE_INNER(seg) 117 118 #define SR(reg_name)\ 119 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR(reg_name, id)\ 122 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 123 reg ## reg_name 124 #define SR_ARR_INIT(reg_name, id, value)\ 125 REG_STRUCT[id].reg_name = value 126 127 #define SRI(reg_name, block, id)\ 128 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 129 reg ## block ## id ## _ ## reg_name 130 131 #define SRI_ARR(reg_name, block, id)\ 132 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 133 reg ## block ## id ## _ ## reg_name 134 135 #define SR_ARR_I2C(reg_name, id) \ 136 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 137 138 #define SRI_ARR_I2C(reg_name, block, id)\ 139 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 140 reg ## block ## id ## _ ## reg_name 141 142 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 143 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 reg ## block ## id ## _ ## reg_name 145 146 #define SRI2(reg_name, block, id)\ 147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 #define SRI2_ARR(reg_name, block, id)\ 150 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 151 reg ## reg_name 152 153 #define SRIR(var_name, reg_name, block, id)\ 154 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 155 reg ## block ## id ## _ ## reg_name 156 157 #define SRII(reg_name, block, id)\ 158 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161 #define SRII_ARR_2(reg_name, block, id, inst)\ 162 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165 #define SRII_MPC_RMU(reg_name, block, id)\ 166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169 #define SRII_DWB(reg_name, temp_name, block, id)\ 170 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## temp_name 172 173 #define DCCG_SRII(reg_name, block, id)\ 174 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 183 184 #define NBIO_BASE(seg) \ 185 NBIO_BASE_INNER(seg) 186 187 #define NBIO_SR(reg_name)\ 188 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 #define NBIO_SR_ARR(reg_name, id)\ 191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 192 regBIF_BX0_ ## reg_name 193 194 #define CTX ctx 195 #define REG(reg_name) \ 196 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 197 198 static struct bios_registers bios_regs; 199 200 #define bios_regs_init() \ 201 ( \ 202 NBIO_SR(BIOS_SCRATCH_3),\ 203 NBIO_SR(BIOS_SCRATCH_6)\ 204 ) 205 206 #define clk_src_regs_init(index, pllid)\ 207 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 208 209 static struct dce110_clk_src_regs clk_src_regs[5]; 210 211 static const struct dce110_clk_src_shift cs_shift = { 212 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 213 }; 214 215 static const struct dce110_clk_src_mask cs_mask = { 216 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 217 }; 218 219 #define abm_regs_init(id)\ 220 ABM_DCN32_REG_LIST_RI(id) 221 222 static struct dce_abm_registers abm_regs[4]; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN32(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN32(_MASK) 230 }; 231 232 #define audio_regs_init(id)\ 233 AUD_COMMON_REG_LIST_RI(id) 234 235 static struct dce_audio_registers audio_regs[5]; 236 237 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 238 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 240 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 241 242 static const struct dce_audio_shift audio_shift = { 243 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 244 }; 245 246 static const struct dce_audio_mask audio_mask = { 247 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 248 }; 249 250 #define vpg_regs_init(id)\ 251 VPG_DCN3_REG_LIST_RI(id) 252 253 static struct dcn30_vpg_registers vpg_regs[10]; 254 255 static const struct dcn30_vpg_shift vpg_shift = { 256 DCN3_VPG_MASK_SH_LIST(__SHIFT) 257 }; 258 259 static const struct dcn30_vpg_mask vpg_mask = { 260 DCN3_VPG_MASK_SH_LIST(_MASK) 261 }; 262 263 #define afmt_regs_init(id)\ 264 AFMT_DCN3_REG_LIST_RI(id) 265 266 static struct dcn30_afmt_registers afmt_regs[6]; 267 268 static const struct dcn30_afmt_shift afmt_shift = { 269 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 270 }; 271 272 static const struct dcn30_afmt_mask afmt_mask = { 273 DCN3_AFMT_MASK_SH_LIST(_MASK) 274 }; 275 276 #define apg_regs_init(id)\ 277 APG_DCN31_REG_LIST_RI(id) 278 279 static struct dcn31_apg_registers apg_regs[4]; 280 281 static const struct dcn31_apg_shift apg_shift = { 282 DCN31_APG_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dcn31_apg_mask apg_mask = { 286 DCN31_APG_MASK_SH_LIST(_MASK) 287 }; 288 289 #define stream_enc_regs_init(id)\ 290 SE_DCN32_REG_LIST_RI(id) 291 292 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 293 294 static const struct dcn10_stream_encoder_shift se_shift = { 295 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 296 }; 297 298 static const struct dcn10_stream_encoder_mask se_mask = { 299 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 300 }; 301 302 303 #define aux_regs_init(id)\ 304 DCN2_AUX_REG_LIST_RI(id) 305 306 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 307 308 #define hpd_regs_init(id)\ 309 HPD_REG_LIST_RI(id) 310 311 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 312 313 #define link_regs_init(id, phyid)\ 314 ( \ 315 LE_DCN31_REG_LIST_RI(id), \ 316 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 317 ) 318 /*DPCS_DCN31_REG_LIST(id),*/ \ 319 320 static struct dcn10_link_enc_registers link_enc_regs[5]; 321 322 static const struct dcn10_link_enc_shift le_shift = { 323 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 324 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dcn10_link_enc_mask le_mask = { 328 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 329 // DPCS_DCN31_MASK_SH_LIST(_MASK) 330 }; 331 332 #define hpo_dp_stream_encoder_reg_init(id)\ 333 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 334 335 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 336 337 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 338 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 343 }; 344 345 346 #define hpo_dp_link_encoder_reg_init(id)\ 347 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 352 353 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 354 355 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 356 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 361 }; 362 363 #define dpp_regs_init(id)\ 364 DPP_REG_LIST_DCN30_COMMON_RI(id) 365 366 static struct dcn3_dpp_registers dpp_regs[4]; 367 368 static const struct dcn3_dpp_shift tf_shift = { 369 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 370 }; 371 372 static const struct dcn3_dpp_mask tf_mask = { 373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 374 }; 375 376 377 #define opp_regs_init(id)\ 378 OPP_REG_LIST_DCN30_RI(id) 379 380 static struct dcn20_opp_registers opp_regs[4]; 381 382 static const struct dcn20_opp_shift opp_shift = { 383 OPP_MASK_SH_LIST_DCN20(__SHIFT) 384 }; 385 386 static const struct dcn20_opp_mask opp_mask = { 387 OPP_MASK_SH_LIST_DCN20(_MASK) 388 }; 389 390 #define aux_engine_regs_init(id) \ 391 ( \ 392 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 #define dcn_mpc_regs_init()\ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id) \ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 static const struct dcn_hubp2_shift hubp_shift = { 486 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 487 }; 488 489 static const struct dcn_hubp2_mask hubp_mask = { 490 HUBP_MASK_SH_LIST_DCN32(_MASK) 491 }; 492 493 static struct dcn_hubbub_registers hubbub_reg; 494 #define hubbub_reg_init()\ 495 HUBBUB_REG_LIST_DCN32_RI(0) 496 497 static const struct dcn_hubbub_shift hubbub_shift = { 498 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 499 }; 500 501 static const struct dcn_hubbub_mask hubbub_mask = { 502 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 503 }; 504 505 static struct dccg_registers dccg_regs; 506 507 #define dccg_regs_init()\ 508 DCCG_REG_LIST_DCN32_RI() 509 510 static const struct dccg_shift dccg_shift = { 511 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 512 }; 513 514 static const struct dccg_mask dccg_mask = { 515 DCCG_MASK_SH_LIST_DCN32(_MASK) 516 }; 517 518 519 #define SRII2(reg_name_pre, reg_name_post, id)\ 520 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 521 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 522 reg ## reg_name_pre ## id ## _ ## reg_name_post 523 524 525 #define HWSEQ_DCN32_REG_LIST()\ 526 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 527 SR(DIO_MEM_PWR_CTRL), \ 528 SR(ODM_MEM_PWR_CTRL3), \ 529 SR(MMHUBBUB_MEM_PWR_CNTL), \ 530 SR(DCCG_GATE_DISABLE_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL2), \ 532 SR(DCFCLK_CNTL),\ 533 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 534 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 536 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 542 SR(MICROSECOND_TIME_BASE_DIV), \ 543 SR(MILLISECOND_TIME_BASE_DIV), \ 544 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 545 SR(RBBMIF_TIMEOUT_DIS), \ 546 SR(RBBMIF_TIMEOUT_DIS_2), \ 547 SR(DCHUBBUB_CRC_CTRL), \ 548 SR(DPP_TOP0_DPP_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 551 SR(MPC_CRC_CTRL), \ 552 SR(MPC_CRC_RESULT_GB), \ 553 SR(MPC_CRC_RESULT_C), \ 554 SR(MPC_CRC_RESULT_AR), \ 555 SR(DOMAIN0_PG_CONFIG), \ 556 SR(DOMAIN1_PG_CONFIG), \ 557 SR(DOMAIN2_PG_CONFIG), \ 558 SR(DOMAIN3_PG_CONFIG), \ 559 SR(DOMAIN16_PG_CONFIG), \ 560 SR(DOMAIN17_PG_CONFIG), \ 561 SR(DOMAIN18_PG_CONFIG), \ 562 SR(DOMAIN19_PG_CONFIG), \ 563 SR(DOMAIN0_PG_STATUS), \ 564 SR(DOMAIN1_PG_STATUS), \ 565 SR(DOMAIN2_PG_STATUS), \ 566 SR(DOMAIN3_PG_STATUS), \ 567 SR(DOMAIN16_PG_STATUS), \ 568 SR(DOMAIN17_PG_STATUS), \ 569 SR(DOMAIN18_PG_STATUS), \ 570 SR(DOMAIN19_PG_STATUS), \ 571 SR(D1VGA_CONTROL), \ 572 SR(D2VGA_CONTROL), \ 573 SR(D3VGA_CONTROL), \ 574 SR(D4VGA_CONTROL), \ 575 SR(D5VGA_CONTROL), \ 576 SR(D6VGA_CONTROL), \ 577 SR(DC_IP_REQUEST_CNTL), \ 578 SR(AZALIA_AUDIO_DTO), \ 579 SR(AZALIA_CONTROLLER_CLOCK_GATING) 580 581 static struct dce_hwseq_registers hwseq_reg; 582 583 #define hwseq_reg_init()\ 584 HWSEQ_DCN32_REG_LIST() 585 586 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 587 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 588 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 589 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 591 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 606 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 616 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 618 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 619 620 static const struct dce_hwseq_shift hwseq_shift = { 621 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 622 }; 623 624 static const struct dce_hwseq_mask hwseq_mask = { 625 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 626 }; 627 #define vmid_regs_init(id)\ 628 DCN20_VMID_REG_LIST_RI(id) 629 630 static struct dcn_vmid_registers vmid_regs[16]; 631 632 static const struct dcn20_vmid_shift vmid_shifts = { 633 DCN20_VMID_MASK_SH_LIST(__SHIFT) 634 }; 635 636 static const struct dcn20_vmid_mask vmid_masks = { 637 DCN20_VMID_MASK_SH_LIST(_MASK) 638 }; 639 640 static const struct resource_caps res_cap_dcn321 = { 641 .num_timing_generator = 4, 642 .num_opp = 4, 643 .num_video_plane = 4, 644 .num_audio = 5, 645 .num_stream_encoder = 5, 646 .num_hpo_dp_stream_encoder = 4, 647 .num_hpo_dp_link_encoder = 2, 648 .num_pll = 5, 649 .num_dwb = 1, 650 .num_ddc = 5, 651 .num_vmid = 16, 652 .num_mpc_3dlut = 4, 653 .num_dsc = 4, 654 }; 655 656 static const struct dc_plane_cap plane_cap = { 657 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 658 .blends_with_above = true, 659 .blends_with_below = true, 660 .per_pixel_alpha = true, 661 662 .pixel_format_support = { 663 .argb8888 = true, 664 .nv12 = true, 665 .fp16 = true, 666 .p010 = true, 667 .ayuv = false, 668 }, 669 670 .max_upscale_factor = { 671 .argb8888 = 16000, 672 .nv12 = 16000, 673 .fp16 = 16000 674 }, 675 676 // 6:1 downscaling ratio: 1000/6 = 166.666 677 .max_downscale_factor = { 678 .argb8888 = 167, 679 .nv12 = 167, 680 .fp16 = 167 681 }, 682 64, 683 64 684 }; 685 686 static const struct dc_debug_options debug_defaults_drv = { 687 .disable_dmcu = true, 688 .force_abm_enable = false, 689 .timing_trace = false, 690 .clock_trace = true, 691 .disable_pplib_clock_request = false, 692 .pipe_split_policy = MPC_SPLIT_AVOID, 693 .force_single_disp_pipe_split = false, 694 .disable_dcc = DCC_ENABLE, 695 .vsr_support = true, 696 .performance_trace = false, 697 .max_downscale_src_width = 7680,/*upto 8K*/ 698 .disable_pplib_wm_range = false, 699 .scl_reset_length10 = true, 700 .sanity_checks = false, 701 .underflow_assert_delay_us = 0xFFFFFFFF, 702 .dwb_fi_phase = -1, // -1 = disable, 703 .dmub_command_table = true, 704 .enable_mem_low_power = { 705 .bits = { 706 .vga = false, 707 .i2c = false, 708 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 709 .dscl = false, 710 .cm = false, 711 .mpc = false, 712 .optc = true, 713 } 714 }, 715 .use_max_lb = true, 716 .force_disable_subvp = false, 717 .exit_idle_opt_for_cursor_updates = true, 718 .enable_single_display_2to1_odm_policy = true, 719 720 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 721 .enable_double_buffered_dsc_pg_support = true, 722 .enable_dp_dig_pixel_rate_div_policy = 1, 723 .allow_sw_cursor_fallback = false, 724 .alloc_extra_way_for_cursor = true, 725 .min_prefetch_in_strobe_ns = 60000, // 60us 726 }; 727 728 static const struct dc_debug_options debug_defaults_diags = { 729 .disable_dmcu = true, 730 .force_abm_enable = false, 731 .timing_trace = true, 732 .clock_trace = true, 733 .disable_dpp_power_gate = true, 734 .disable_hubp_power_gate = true, 735 .disable_dsc_power_gate = true, 736 .disable_clock_gate = true, 737 .disable_pplib_clock_request = true, 738 .disable_pplib_wm_range = true, 739 .disable_stutter = false, 740 .scl_reset_length10 = true, 741 .dwb_fi_phase = -1, // -1 = disable 742 .dmub_command_table = true, 743 .enable_tri_buf = true, 744 .use_max_lb = true, 745 .force_disable_subvp = true 746 }; 747 748 749 static struct dce_aux *dcn321_aux_engine_create( 750 struct dc_context *ctx, 751 uint32_t inst) 752 { 753 struct aux_engine_dce110 *aux_engine = 754 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 755 756 if (!aux_engine) 757 return NULL; 758 759 #undef REG_STRUCT 760 #define REG_STRUCT aux_engine_regs 761 aux_engine_regs_init(0), 762 aux_engine_regs_init(1), 763 aux_engine_regs_init(2), 764 aux_engine_regs_init(3), 765 aux_engine_regs_init(4); 766 767 dce110_aux_engine_construct(aux_engine, ctx, inst, 768 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 769 &aux_engine_regs[inst], 770 &aux_mask, 771 &aux_shift, 772 ctx->dc->caps.extended_aux_timeout_support); 773 774 return &aux_engine->base; 775 } 776 #define i2c_inst_regs_init(id)\ 777 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 778 779 static struct dce_i2c_registers i2c_hw_regs[5]; 780 781 static const struct dce_i2c_shift i2c_shifts = { 782 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 783 }; 784 785 static const struct dce_i2c_mask i2c_masks = { 786 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 787 }; 788 789 static struct dce_i2c_hw *dcn321_i2c_hw_create( 790 struct dc_context *ctx, 791 uint32_t inst) 792 { 793 struct dce_i2c_hw *dce_i2c_hw = 794 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 795 796 if (!dce_i2c_hw) 797 return NULL; 798 799 #undef REG_STRUCT 800 #define REG_STRUCT i2c_hw_regs 801 i2c_inst_regs_init(1), 802 i2c_inst_regs_init(2), 803 i2c_inst_regs_init(3), 804 i2c_inst_regs_init(4), 805 i2c_inst_regs_init(5); 806 807 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 808 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 809 810 return dce_i2c_hw; 811 } 812 813 static struct clock_source *dcn321_clock_source_create( 814 struct dc_context *ctx, 815 struct dc_bios *bios, 816 enum clock_source_id id, 817 const struct dce110_clk_src_regs *regs, 818 bool dp_clk_src) 819 { 820 struct dce110_clk_src *clk_src = 821 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 822 823 if (!clk_src) 824 return NULL; 825 826 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 827 regs, &cs_shift, &cs_mask)) { 828 clk_src->base.dp_clk_src = dp_clk_src; 829 return &clk_src->base; 830 } 831 832 BREAK_TO_DEBUGGER(); 833 return NULL; 834 } 835 836 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 837 { 838 int i; 839 840 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 841 GFP_KERNEL); 842 843 if (!hubbub2) 844 return NULL; 845 846 #undef REG_STRUCT 847 #define REG_STRUCT hubbub_reg 848 hubbub_reg_init(); 849 850 #undef REG_STRUCT 851 #define REG_STRUCT vmid_regs 852 vmid_regs_init(0), 853 vmid_regs_init(1), 854 vmid_regs_init(2), 855 vmid_regs_init(3), 856 vmid_regs_init(4), 857 vmid_regs_init(5), 858 vmid_regs_init(6), 859 vmid_regs_init(7), 860 vmid_regs_init(8), 861 vmid_regs_init(9), 862 vmid_regs_init(10), 863 vmid_regs_init(11), 864 vmid_regs_init(12), 865 vmid_regs_init(13), 866 vmid_regs_init(14), 867 vmid_regs_init(15); 868 869 hubbub32_construct(hubbub2, ctx, 870 &hubbub_reg, 871 &hubbub_shift, 872 &hubbub_mask, 873 ctx->dc->dml.ip.det_buffer_size_kbytes, 874 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 875 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 876 877 878 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 879 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 880 881 vmid->ctx = ctx; 882 883 vmid->regs = &vmid_regs[i]; 884 vmid->shifts = &vmid_shifts; 885 vmid->masks = &vmid_masks; 886 } 887 888 return &hubbub2->base; 889 } 890 891 static struct hubp *dcn321_hubp_create( 892 struct dc_context *ctx, 893 uint32_t inst) 894 { 895 struct dcn20_hubp *hubp2 = 896 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 897 898 if (!hubp2) 899 return NULL; 900 901 #undef REG_STRUCT 902 #define REG_STRUCT hubp_regs 903 hubp_regs_init(0), 904 hubp_regs_init(1), 905 hubp_regs_init(2), 906 hubp_regs_init(3); 907 908 if (hubp32_construct(hubp2, ctx, inst, 909 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 910 return &hubp2->base; 911 912 BREAK_TO_DEBUGGER(); 913 kfree(hubp2); 914 return NULL; 915 } 916 917 static void dcn321_dpp_destroy(struct dpp **dpp) 918 { 919 kfree(TO_DCN30_DPP(*dpp)); 920 *dpp = NULL; 921 } 922 923 static struct dpp *dcn321_dpp_create( 924 struct dc_context *ctx, 925 uint32_t inst) 926 { 927 struct dcn3_dpp *dpp3 = 928 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 929 930 if (!dpp3) 931 return NULL; 932 933 #undef REG_STRUCT 934 #define REG_STRUCT dpp_regs 935 dpp_regs_init(0), 936 dpp_regs_init(1), 937 dpp_regs_init(2), 938 dpp_regs_init(3); 939 940 if (dpp32_construct(dpp3, ctx, inst, 941 &dpp_regs[inst], &tf_shift, &tf_mask)) 942 return &dpp3->base; 943 944 BREAK_TO_DEBUGGER(); 945 kfree(dpp3); 946 return NULL; 947 } 948 949 static struct mpc *dcn321_mpc_create( 950 struct dc_context *ctx, 951 int num_mpcc, 952 int num_rmu) 953 { 954 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 955 GFP_KERNEL); 956 957 if (!mpc30) 958 return NULL; 959 960 #undef REG_STRUCT 961 #define REG_STRUCT mpc_regs 962 dcn_mpc_regs_init(); 963 964 dcn32_mpc_construct(mpc30, ctx, 965 &mpc_regs, 966 &mpc_shift, 967 &mpc_mask, 968 num_mpcc, 969 num_rmu); 970 971 return &mpc30->base; 972 } 973 974 static struct output_pixel_processor *dcn321_opp_create( 975 struct dc_context *ctx, uint32_t inst) 976 { 977 struct dcn20_opp *opp2 = 978 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 979 980 if (!opp2) { 981 BREAK_TO_DEBUGGER(); 982 return NULL; 983 } 984 985 #undef REG_STRUCT 986 #define REG_STRUCT opp_regs 987 opp_regs_init(0), 988 opp_regs_init(1), 989 opp_regs_init(2), 990 opp_regs_init(3); 991 992 dcn20_opp_construct(opp2, ctx, inst, 993 &opp_regs[inst], &opp_shift, &opp_mask); 994 return &opp2->base; 995 } 996 997 998 static struct timing_generator *dcn321_timing_generator_create( 999 struct dc_context *ctx, 1000 uint32_t instance) 1001 { 1002 struct optc *tgn10 = 1003 kzalloc(sizeof(struct optc), GFP_KERNEL); 1004 1005 if (!tgn10) 1006 return NULL; 1007 1008 #undef REG_STRUCT 1009 #define REG_STRUCT optc_regs 1010 optc_regs_init(0), 1011 optc_regs_init(1), 1012 optc_regs_init(2), 1013 optc_regs_init(3); 1014 1015 tgn10->base.inst = instance; 1016 tgn10->base.ctx = ctx; 1017 1018 tgn10->tg_regs = &optc_regs[instance]; 1019 tgn10->tg_shift = &optc_shift; 1020 tgn10->tg_mask = &optc_mask; 1021 1022 dcn32_timing_generator_init(tgn10); 1023 1024 return &tgn10->base; 1025 } 1026 1027 static const struct encoder_feature_support link_enc_feature = { 1028 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1029 .max_hdmi_pixel_clock = 600000, 1030 .hdmi_ycbcr420_supported = true, 1031 .dp_ycbcr420_supported = true, 1032 .fec_supported = true, 1033 .flags.bits.IS_HBR2_CAPABLE = true, 1034 .flags.bits.IS_HBR3_CAPABLE = true, 1035 .flags.bits.IS_TPS3_CAPABLE = true, 1036 .flags.bits.IS_TPS4_CAPABLE = true 1037 }; 1038 1039 static struct link_encoder *dcn321_link_encoder_create( 1040 struct dc_context *ctx, 1041 const struct encoder_init_data *enc_init_data) 1042 { 1043 struct dcn20_link_encoder *enc20 = 1044 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1045 1046 if (!enc20) 1047 return NULL; 1048 1049 #undef REG_STRUCT 1050 #define REG_STRUCT link_enc_aux_regs 1051 aux_regs_init(0), 1052 aux_regs_init(1), 1053 aux_regs_init(2), 1054 aux_regs_init(3), 1055 aux_regs_init(4); 1056 1057 #undef REG_STRUCT 1058 #define REG_STRUCT link_enc_hpd_regs 1059 hpd_regs_init(0), 1060 hpd_regs_init(1), 1061 hpd_regs_init(2), 1062 hpd_regs_init(3), 1063 hpd_regs_init(4); 1064 1065 #undef REG_STRUCT 1066 #define REG_STRUCT link_enc_regs 1067 link_regs_init(0, A), 1068 link_regs_init(1, B), 1069 link_regs_init(2, C), 1070 link_regs_init(3, D), 1071 link_regs_init(4, E); 1072 1073 dcn321_link_encoder_construct(enc20, 1074 enc_init_data, 1075 &link_enc_feature, 1076 &link_enc_regs[enc_init_data->transmitter], 1077 &link_enc_aux_regs[enc_init_data->channel - 1], 1078 &link_enc_hpd_regs[enc_init_data->hpd_source], 1079 &le_shift, 1080 &le_mask); 1081 1082 return &enc20->enc10.base; 1083 } 1084 1085 static void read_dce_straps( 1086 struct dc_context *ctx, 1087 struct resource_straps *straps) 1088 { 1089 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1090 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1091 1092 } 1093 1094 static struct audio *dcn321_create_audio( 1095 struct dc_context *ctx, unsigned int inst) 1096 { 1097 1098 #undef REG_STRUCT 1099 #define REG_STRUCT audio_regs 1100 audio_regs_init(0), 1101 audio_regs_init(1), 1102 audio_regs_init(2), 1103 audio_regs_init(3), 1104 audio_regs_init(4); 1105 1106 return dce_audio_create(ctx, inst, 1107 &audio_regs[inst], &audio_shift, &audio_mask); 1108 } 1109 1110 static struct vpg *dcn321_vpg_create( 1111 struct dc_context *ctx, 1112 uint32_t inst) 1113 { 1114 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1115 1116 if (!vpg3) 1117 return NULL; 1118 1119 #undef REG_STRUCT 1120 #define REG_STRUCT vpg_regs 1121 vpg_regs_init(0), 1122 vpg_regs_init(1), 1123 vpg_regs_init(2), 1124 vpg_regs_init(3), 1125 vpg_regs_init(4), 1126 vpg_regs_init(5), 1127 vpg_regs_init(6), 1128 vpg_regs_init(7), 1129 vpg_regs_init(8), 1130 vpg_regs_init(9); 1131 1132 vpg3_construct(vpg3, ctx, inst, 1133 &vpg_regs[inst], 1134 &vpg_shift, 1135 &vpg_mask); 1136 1137 return &vpg3->base; 1138 } 1139 1140 static struct afmt *dcn321_afmt_create( 1141 struct dc_context *ctx, 1142 uint32_t inst) 1143 { 1144 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1145 1146 if (!afmt3) 1147 return NULL; 1148 1149 #undef REG_STRUCT 1150 #define REG_STRUCT afmt_regs 1151 afmt_regs_init(0), 1152 afmt_regs_init(1), 1153 afmt_regs_init(2), 1154 afmt_regs_init(3), 1155 afmt_regs_init(4), 1156 afmt_regs_init(5); 1157 1158 afmt3_construct(afmt3, ctx, inst, 1159 &afmt_regs[inst], 1160 &afmt_shift, 1161 &afmt_mask); 1162 1163 return &afmt3->base; 1164 } 1165 1166 static struct apg *dcn321_apg_create( 1167 struct dc_context *ctx, 1168 uint32_t inst) 1169 { 1170 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1171 1172 if (!apg31) 1173 return NULL; 1174 1175 #undef REG_STRUCT 1176 #define REG_STRUCT apg_regs 1177 apg_regs_init(0), 1178 apg_regs_init(1), 1179 apg_regs_init(2), 1180 apg_regs_init(3); 1181 1182 apg31_construct(apg31, ctx, inst, 1183 &apg_regs[inst], 1184 &apg_shift, 1185 &apg_mask); 1186 1187 return &apg31->base; 1188 } 1189 1190 static struct stream_encoder *dcn321_stream_encoder_create( 1191 enum engine_id eng_id, 1192 struct dc_context *ctx) 1193 { 1194 struct dcn10_stream_encoder *enc1; 1195 struct vpg *vpg; 1196 struct afmt *afmt; 1197 int vpg_inst; 1198 int afmt_inst; 1199 1200 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1201 if (eng_id <= ENGINE_ID_DIGF) { 1202 vpg_inst = eng_id; 1203 afmt_inst = eng_id; 1204 } else 1205 return NULL; 1206 1207 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1208 vpg = dcn321_vpg_create(ctx, vpg_inst); 1209 afmt = dcn321_afmt_create(ctx, afmt_inst); 1210 1211 if (!enc1 || !vpg || !afmt) { 1212 kfree(enc1); 1213 kfree(vpg); 1214 kfree(afmt); 1215 return NULL; 1216 } 1217 1218 #undef REG_STRUCT 1219 #define REG_STRUCT stream_enc_regs 1220 stream_enc_regs_init(0), 1221 stream_enc_regs_init(1), 1222 stream_enc_regs_init(2), 1223 stream_enc_regs_init(3), 1224 stream_enc_regs_init(4); 1225 1226 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1227 eng_id, vpg, afmt, 1228 &stream_enc_regs[eng_id], 1229 &se_shift, &se_mask); 1230 1231 return &enc1->base; 1232 } 1233 1234 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1235 enum engine_id eng_id, 1236 struct dc_context *ctx) 1237 { 1238 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1239 struct vpg *vpg; 1240 struct apg *apg; 1241 uint32_t hpo_dp_inst; 1242 uint32_t vpg_inst; 1243 uint32_t apg_inst; 1244 1245 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1246 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1247 1248 /* Mapping of VPG register blocks to HPO DP block instance: 1249 * VPG[6] -> HPO_DP[0] 1250 * VPG[7] -> HPO_DP[1] 1251 * VPG[8] -> HPO_DP[2] 1252 * VPG[9] -> HPO_DP[3] 1253 */ 1254 vpg_inst = hpo_dp_inst + 6; 1255 1256 /* Mapping of APG register blocks to HPO DP block instance: 1257 * APG[0] -> HPO_DP[0] 1258 * APG[1] -> HPO_DP[1] 1259 * APG[2] -> HPO_DP[2] 1260 * APG[3] -> HPO_DP[3] 1261 */ 1262 apg_inst = hpo_dp_inst; 1263 1264 /* allocate HPO stream encoder and create VPG sub-block */ 1265 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1266 vpg = dcn321_vpg_create(ctx, vpg_inst); 1267 apg = dcn321_apg_create(ctx, apg_inst); 1268 1269 if (!hpo_dp_enc31 || !vpg || !apg) { 1270 kfree(hpo_dp_enc31); 1271 kfree(vpg); 1272 kfree(apg); 1273 return NULL; 1274 } 1275 1276 #undef REG_STRUCT 1277 #define REG_STRUCT hpo_dp_stream_enc_regs 1278 hpo_dp_stream_encoder_reg_init(0), 1279 hpo_dp_stream_encoder_reg_init(1), 1280 hpo_dp_stream_encoder_reg_init(2), 1281 hpo_dp_stream_encoder_reg_init(3); 1282 1283 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1284 hpo_dp_inst, eng_id, vpg, apg, 1285 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1286 &hpo_dp_se_shift, &hpo_dp_se_mask); 1287 1288 return &hpo_dp_enc31->base; 1289 } 1290 1291 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1292 uint8_t inst, 1293 struct dc_context *ctx) 1294 { 1295 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1296 1297 /* allocate HPO link encoder */ 1298 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1299 1300 #undef REG_STRUCT 1301 #define REG_STRUCT hpo_dp_link_enc_regs 1302 hpo_dp_link_encoder_reg_init(0), 1303 hpo_dp_link_encoder_reg_init(1); 1304 1305 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1306 &hpo_dp_link_enc_regs[inst], 1307 &hpo_dp_le_shift, &hpo_dp_le_mask); 1308 1309 return &hpo_dp_enc31->base; 1310 } 1311 1312 static struct dce_hwseq *dcn321_hwseq_create( 1313 struct dc_context *ctx) 1314 { 1315 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1316 1317 #undef REG_STRUCT 1318 #define REG_STRUCT hwseq_reg 1319 hwseq_reg_init(); 1320 1321 if (hws) { 1322 hws->ctx = ctx; 1323 hws->regs = &hwseq_reg; 1324 hws->shifts = &hwseq_shift; 1325 hws->masks = &hwseq_mask; 1326 } 1327 return hws; 1328 } 1329 static const struct resource_create_funcs res_create_funcs = { 1330 .read_dce_straps = read_dce_straps, 1331 .create_audio = dcn321_create_audio, 1332 .create_stream_encoder = dcn321_stream_encoder_create, 1333 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1334 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1335 .create_hwseq = dcn321_hwseq_create, 1336 }; 1337 1338 static const struct resource_create_funcs res_create_maximus_funcs = { 1339 .read_dce_straps = NULL, 1340 .create_audio = NULL, 1341 .create_stream_encoder = NULL, 1342 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1343 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1344 .create_hwseq = dcn321_hwseq_create, 1345 }; 1346 1347 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1348 { 1349 unsigned int i; 1350 1351 for (i = 0; i < pool->base.stream_enc_count; i++) { 1352 if (pool->base.stream_enc[i] != NULL) { 1353 if (pool->base.stream_enc[i]->vpg != NULL) { 1354 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1355 pool->base.stream_enc[i]->vpg = NULL; 1356 } 1357 if (pool->base.stream_enc[i]->afmt != NULL) { 1358 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1359 pool->base.stream_enc[i]->afmt = NULL; 1360 } 1361 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1362 pool->base.stream_enc[i] = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1367 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1368 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1369 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1370 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1371 } 1372 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1373 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1374 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1375 } 1376 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1377 pool->base.hpo_dp_stream_enc[i] = NULL; 1378 } 1379 } 1380 1381 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1382 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1383 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1384 pool->base.hpo_dp_link_enc[i] = NULL; 1385 } 1386 } 1387 1388 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1389 if (pool->base.dscs[i] != NULL) 1390 dcn20_dsc_destroy(&pool->base.dscs[i]); 1391 } 1392 1393 if (pool->base.mpc != NULL) { 1394 kfree(TO_DCN20_MPC(pool->base.mpc)); 1395 pool->base.mpc = NULL; 1396 } 1397 if (pool->base.hubbub != NULL) { 1398 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1399 pool->base.hubbub = NULL; 1400 } 1401 for (i = 0; i < pool->base.pipe_count; i++) { 1402 if (pool->base.dpps[i] != NULL) 1403 dcn321_dpp_destroy(&pool->base.dpps[i]); 1404 1405 if (pool->base.ipps[i] != NULL) 1406 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1407 1408 if (pool->base.hubps[i] != NULL) { 1409 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1410 pool->base.hubps[i] = NULL; 1411 } 1412 1413 if (pool->base.irqs != NULL) 1414 dal_irq_service_destroy(&pool->base.irqs); 1415 } 1416 1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1418 if (pool->base.engines[i] != NULL) 1419 dce110_engine_destroy(&pool->base.engines[i]); 1420 if (pool->base.hw_i2cs[i] != NULL) { 1421 kfree(pool->base.hw_i2cs[i]); 1422 pool->base.hw_i2cs[i] = NULL; 1423 } 1424 if (pool->base.sw_i2cs[i] != NULL) { 1425 kfree(pool->base.sw_i2cs[i]); 1426 pool->base.sw_i2cs[i] = NULL; 1427 } 1428 } 1429 1430 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1431 if (pool->base.opps[i] != NULL) 1432 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1433 } 1434 1435 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1436 if (pool->base.timing_generators[i] != NULL) { 1437 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1438 pool->base.timing_generators[i] = NULL; 1439 } 1440 } 1441 1442 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1443 if (pool->base.dwbc[i] != NULL) { 1444 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1445 pool->base.dwbc[i] = NULL; 1446 } 1447 if (pool->base.mcif_wb[i] != NULL) { 1448 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1449 pool->base.mcif_wb[i] = NULL; 1450 } 1451 } 1452 1453 for (i = 0; i < pool->base.audio_count; i++) { 1454 if (pool->base.audios[i]) 1455 dce_aud_destroy(&pool->base.audios[i]); 1456 } 1457 1458 for (i = 0; i < pool->base.clk_src_count; i++) { 1459 if (pool->base.clock_sources[i] != NULL) { 1460 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1461 pool->base.clock_sources[i] = NULL; 1462 } 1463 } 1464 1465 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1466 if (pool->base.mpc_lut[i] != NULL) { 1467 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1468 pool->base.mpc_lut[i] = NULL; 1469 } 1470 if (pool->base.mpc_shaper[i] != NULL) { 1471 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1472 pool->base.mpc_shaper[i] = NULL; 1473 } 1474 } 1475 1476 if (pool->base.dp_clock_source != NULL) { 1477 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1478 pool->base.dp_clock_source = NULL; 1479 } 1480 1481 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1482 if (pool->base.multiple_abms[i] != NULL) 1483 dce_abm_destroy(&pool->base.multiple_abms[i]); 1484 } 1485 1486 if (pool->base.psr != NULL) 1487 dmub_psr_destroy(&pool->base.psr); 1488 1489 if (pool->base.dccg != NULL) 1490 dcn_dccg_destroy(&pool->base.dccg); 1491 1492 if (pool->base.oem_device != NULL) 1493 dal_ddc_service_destroy(&pool->base.oem_device); 1494 } 1495 1496 1497 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1498 { 1499 int i; 1500 uint32_t dwb_count = pool->res_cap->num_dwb; 1501 1502 for (i = 0; i < dwb_count; i++) { 1503 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1504 GFP_KERNEL); 1505 1506 if (!dwbc30) { 1507 dm_error("DC: failed to create dwbc30!\n"); 1508 return false; 1509 } 1510 1511 #undef REG_STRUCT 1512 #define REG_STRUCT dwbc30_regs 1513 dwbc_regs_dcn3_init(0); 1514 1515 dcn30_dwbc_construct(dwbc30, ctx, 1516 &dwbc30_regs[i], 1517 &dwbc30_shift, 1518 &dwbc30_mask, 1519 i); 1520 1521 pool->dwbc[i] = &dwbc30->base; 1522 } 1523 return true; 1524 } 1525 1526 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1527 { 1528 int i; 1529 uint32_t dwb_count = pool->res_cap->num_dwb; 1530 1531 for (i = 0; i < dwb_count; i++) { 1532 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1533 GFP_KERNEL); 1534 1535 if (!mcif_wb30) { 1536 dm_error("DC: failed to create mcif_wb30!\n"); 1537 return false; 1538 } 1539 1540 #undef REG_STRUCT 1541 #define REG_STRUCT mcif_wb30_regs 1542 mcif_wb_regs_dcn3_init(0); 1543 1544 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1545 &mcif_wb30_regs[i], 1546 &mcif_wb30_shift, 1547 &mcif_wb30_mask, 1548 i); 1549 1550 pool->mcif_wb[i] = &mcif_wb30->base; 1551 } 1552 return true; 1553 } 1554 1555 static struct display_stream_compressor *dcn321_dsc_create( 1556 struct dc_context *ctx, uint32_t inst) 1557 { 1558 struct dcn20_dsc *dsc = 1559 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1560 1561 if (!dsc) { 1562 BREAK_TO_DEBUGGER(); 1563 return NULL; 1564 } 1565 1566 #undef REG_STRUCT 1567 #define REG_STRUCT dsc_regs 1568 dsc_regsDCN20_init(0), 1569 dsc_regsDCN20_init(1), 1570 dsc_regsDCN20_init(2), 1571 dsc_regsDCN20_init(3); 1572 1573 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1574 1575 dsc->max_image_width = 6016; 1576 1577 return &dsc->base; 1578 } 1579 1580 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1581 { 1582 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1583 1584 dcn321_resource_destruct(dcn321_pool); 1585 kfree(dcn321_pool); 1586 *pool = NULL; 1587 } 1588 1589 static struct dc_cap_funcs cap_funcs = { 1590 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1591 }; 1592 1593 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1594 { 1595 DC_FP_START(); 1596 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1597 DC_FP_END(); 1598 } 1599 1600 static struct resource_funcs dcn321_res_pool_funcs = { 1601 .destroy = dcn321_destroy_resource_pool, 1602 .link_enc_create = dcn321_link_encoder_create, 1603 .link_enc_create_minimal = NULL, 1604 .panel_cntl_create = dcn32_panel_cntl_create, 1605 .validate_bandwidth = dcn32_validate_bandwidth, 1606 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1607 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1608 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1609 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1610 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1611 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1612 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1613 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1614 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1615 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1616 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1617 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1618 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1619 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1620 .add_phantom_pipes = dcn32_add_phantom_pipes, 1621 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1622 }; 1623 1624 1625 static bool dcn321_resource_construct( 1626 uint8_t num_virtual_links, 1627 struct dc *dc, 1628 struct dcn321_resource_pool *pool) 1629 { 1630 int i, j; 1631 struct dc_context *ctx = dc->ctx; 1632 struct irq_service_init_data init_data; 1633 struct ddc_service_init_data ddc_init_data = {0}; 1634 uint32_t pipe_fuses = 0; 1635 uint32_t num_pipes = 4; 1636 1637 #undef REG_STRUCT 1638 #define REG_STRUCT bios_regs 1639 bios_regs_init(); 1640 1641 #undef REG_STRUCT 1642 #define REG_STRUCT clk_src_regs 1643 clk_src_regs_init(0, A), 1644 clk_src_regs_init(1, B), 1645 clk_src_regs_init(2, C), 1646 clk_src_regs_init(3, D), 1647 clk_src_regs_init(4, E); 1648 1649 #undef REG_STRUCT 1650 #define REG_STRUCT abm_regs 1651 abm_regs_init(0), 1652 abm_regs_init(1), 1653 abm_regs_init(2), 1654 abm_regs_init(3); 1655 1656 #undef REG_STRUCT 1657 #define REG_STRUCT dccg_regs 1658 dccg_regs_init(); 1659 1660 1661 ctx->dc_bios->regs = &bios_regs; 1662 1663 pool->base.res_cap = &res_cap_dcn321; 1664 /* max number of pipes for ASIC before checking for pipe fuses */ 1665 num_pipes = pool->base.res_cap->num_timing_generator; 1666 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1667 1668 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1669 if (pipe_fuses & 1 << i) 1670 num_pipes--; 1671 1672 if (pipe_fuses & 1) 1673 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1674 1675 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1676 ASSERT(0); //Entire DCN is harvested! 1677 1678 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1679 * value will be changed, update max_num_dpp and max_num_otg for dml. 1680 */ 1681 dcn3_21_ip.max_num_dpp = num_pipes; 1682 dcn3_21_ip.max_num_otg = num_pipes; 1683 1684 pool->base.funcs = &dcn321_res_pool_funcs; 1685 1686 /************************************************* 1687 * Resource + asic cap harcoding * 1688 *************************************************/ 1689 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1690 pool->base.timing_generator_count = num_pipes; 1691 pool->base.pipe_count = num_pipes; 1692 pool->base.mpcc_count = num_pipes; 1693 dc->caps.max_downscale_ratio = 600; 1694 dc->caps.i2c_speed_in_khz = 100; 1695 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1696 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1697 dc->caps.max_cursor_size = 64; 1698 dc->caps.min_horizontal_blanking_period = 80; 1699 dc->caps.dmdata_alloc_size = 2048; 1700 dc->caps.mall_size_per_mem_channel = 0; 1701 dc->caps.mall_size_total = 0; 1702 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1703 dc->caps.cache_line_size = 64; 1704 dc->caps.cache_num_ways = 16; 1705 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 1706 dc->caps.subvp_fw_processing_delay_us = 15; 1707 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1708 dc->caps.subvp_swath_height_margin_lines = 16; 1709 dc->caps.subvp_pstate_allow_width_us = 20; 1710 dc->caps.subvp_vertical_int_margin_us = 30; 1711 dc->caps.max_slave_planes = 1; 1712 dc->caps.max_slave_yuv_planes = 1; 1713 dc->caps.max_slave_rgb_planes = 1; 1714 dc->caps.post_blend_color_processing = true; 1715 dc->caps.force_dp_tps4_for_cp2520 = true; 1716 dc->caps.dp_hpo = true; 1717 dc->caps.dp_hdmi21_pcon_support = true; 1718 dc->caps.edp_dsc_support = true; 1719 dc->caps.extended_aux_timeout_support = true; 1720 dc->caps.dmcub_support = true; 1721 1722 /* Color pipeline capabilities */ 1723 dc->caps.color.dpp.dcn_arch = 1; 1724 dc->caps.color.dpp.input_lut_shared = 0; 1725 dc->caps.color.dpp.icsc = 1; 1726 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1727 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1728 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1729 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1730 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1731 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1732 dc->caps.color.dpp.post_csc = 1; 1733 dc->caps.color.dpp.gamma_corr = 1; 1734 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1735 1736 dc->caps.color.dpp.hw_3d_lut = 1; 1737 dc->caps.color.dpp.ogam_ram = 1; 1738 // no OGAM ROM on DCN2 and later ASICs 1739 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1740 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1741 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1742 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1743 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1744 dc->caps.color.dpp.ocsc = 0; 1745 1746 dc->caps.color.mpc.gamut_remap = 1; 1747 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1748 dc->caps.color.mpc.ogam_ram = 1; 1749 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1750 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1751 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1752 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1753 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1754 dc->caps.color.mpc.ocsc = 1; 1755 1756 /* read VBIOS LTTPR caps */ 1757 { 1758 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1759 enum bp_result bp_query_result; 1760 uint8_t is_vbios_lttpr_enable = 0; 1761 1762 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1763 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1764 } 1765 1766 /* interop bit is implicit */ 1767 { 1768 dc->caps.vbios_lttpr_aware = true; 1769 } 1770 } 1771 1772 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1773 dc->debug = debug_defaults_drv; 1774 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1775 dc->debug = debug_defaults_diags; 1776 } else 1777 dc->debug = debug_defaults_diags; 1778 // Init the vm_helper 1779 if (dc->vm_helper) 1780 vm_helper_init(dc->vm_helper, 16); 1781 1782 /************************************************* 1783 * Create resources * 1784 *************************************************/ 1785 1786 /* Clock Sources for Pixel Clock*/ 1787 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1788 dcn321_clock_source_create(ctx, ctx->dc_bios, 1789 CLOCK_SOURCE_COMBO_PHY_PLL0, 1790 &clk_src_regs[0], false); 1791 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1792 dcn321_clock_source_create(ctx, ctx->dc_bios, 1793 CLOCK_SOURCE_COMBO_PHY_PLL1, 1794 &clk_src_regs[1], false); 1795 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1796 dcn321_clock_source_create(ctx, ctx->dc_bios, 1797 CLOCK_SOURCE_COMBO_PHY_PLL2, 1798 &clk_src_regs[2], false); 1799 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1800 dcn321_clock_source_create(ctx, ctx->dc_bios, 1801 CLOCK_SOURCE_COMBO_PHY_PLL3, 1802 &clk_src_regs[3], false); 1803 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1804 dcn321_clock_source_create(ctx, ctx->dc_bios, 1805 CLOCK_SOURCE_COMBO_PHY_PLL4, 1806 &clk_src_regs[4], false); 1807 1808 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1809 1810 /* todo: not reuse phy_pll registers */ 1811 pool->base.dp_clock_source = 1812 dcn321_clock_source_create(ctx, ctx->dc_bios, 1813 CLOCK_SOURCE_ID_DP_DTO, 1814 &clk_src_regs[0], true); 1815 1816 for (i = 0; i < pool->base.clk_src_count; i++) { 1817 if (pool->base.clock_sources[i] == NULL) { 1818 dm_error("DC: failed to create clock sources!\n"); 1819 BREAK_TO_DEBUGGER(); 1820 goto create_fail; 1821 } 1822 } 1823 1824 /* DCCG */ 1825 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1826 if (pool->base.dccg == NULL) { 1827 dm_error("DC: failed to create dccg!\n"); 1828 BREAK_TO_DEBUGGER(); 1829 goto create_fail; 1830 } 1831 1832 /* DML */ 1833 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1834 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1835 1836 /* IRQ Service */ 1837 init_data.ctx = dc->ctx; 1838 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1839 if (!pool->base.irqs) 1840 goto create_fail; 1841 1842 /* HUBBUB */ 1843 pool->base.hubbub = dcn321_hubbub_create(ctx); 1844 if (pool->base.hubbub == NULL) { 1845 BREAK_TO_DEBUGGER(); 1846 dm_error("DC: failed to create hubbub!\n"); 1847 goto create_fail; 1848 } 1849 1850 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1851 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1852 1853 /* if pipe is disabled, skip instance of HW pipe, 1854 * i.e, skip ASIC register instance 1855 */ 1856 if (pipe_fuses & 1 << i) 1857 continue; 1858 1859 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1860 if (pool->base.hubps[j] == NULL) { 1861 BREAK_TO_DEBUGGER(); 1862 dm_error( 1863 "DC: failed to create hubps!\n"); 1864 goto create_fail; 1865 } 1866 1867 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1868 if (pool->base.dpps[j] == NULL) { 1869 BREAK_TO_DEBUGGER(); 1870 dm_error( 1871 "DC: failed to create dpps!\n"); 1872 goto create_fail; 1873 } 1874 1875 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1876 if (pool->base.opps[j] == NULL) { 1877 BREAK_TO_DEBUGGER(); 1878 dm_error( 1879 "DC: failed to create output pixel processor!\n"); 1880 goto create_fail; 1881 } 1882 1883 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1884 ctx, i); 1885 if (pool->base.timing_generators[j] == NULL) { 1886 BREAK_TO_DEBUGGER(); 1887 dm_error("DC: failed to create tg!\n"); 1888 goto create_fail; 1889 } 1890 1891 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1892 &abm_regs[i], 1893 &abm_shift, 1894 &abm_mask); 1895 if (pool->base.multiple_abms[j] == NULL) { 1896 dm_error("DC: failed to create abm for pipe %d!\n", i); 1897 BREAK_TO_DEBUGGER(); 1898 goto create_fail; 1899 } 1900 1901 /* index for resource pool arrays for next valid pipe */ 1902 j++; 1903 } 1904 1905 /* PSR */ 1906 pool->base.psr = dmub_psr_create(ctx); 1907 if (pool->base.psr == NULL) { 1908 dm_error("DC: failed to create psr obj!\n"); 1909 BREAK_TO_DEBUGGER(); 1910 goto create_fail; 1911 } 1912 1913 /* MPCCs */ 1914 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1915 if (pool->base.mpc == NULL) { 1916 BREAK_TO_DEBUGGER(); 1917 dm_error("DC: failed to create mpc!\n"); 1918 goto create_fail; 1919 } 1920 1921 /* DSCs */ 1922 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1923 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1924 if (pool->base.dscs[i] == NULL) { 1925 BREAK_TO_DEBUGGER(); 1926 dm_error("DC: failed to create display stream compressor %d!\n", i); 1927 goto create_fail; 1928 } 1929 } 1930 1931 /* DWB */ 1932 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1933 BREAK_TO_DEBUGGER(); 1934 dm_error("DC: failed to create dwbc!\n"); 1935 goto create_fail; 1936 } 1937 1938 /* MMHUBBUB */ 1939 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1940 BREAK_TO_DEBUGGER(); 1941 dm_error("DC: failed to create mcif_wb!\n"); 1942 goto create_fail; 1943 } 1944 1945 /* AUX and I2C */ 1946 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1947 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1948 if (pool->base.engines[i] == NULL) { 1949 BREAK_TO_DEBUGGER(); 1950 dm_error( 1951 "DC:failed to create aux engine!!\n"); 1952 goto create_fail; 1953 } 1954 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1955 if (pool->base.hw_i2cs[i] == NULL) { 1956 BREAK_TO_DEBUGGER(); 1957 dm_error( 1958 "DC:failed to create hw i2c!!\n"); 1959 goto create_fail; 1960 } 1961 pool->base.sw_i2cs[i] = NULL; 1962 } 1963 1964 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1965 if (!resource_construct(num_virtual_links, dc, &pool->base, 1966 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1967 &res_create_funcs : &res_create_maximus_funcs))) 1968 goto create_fail; 1969 1970 /* HW Sequencer init functions and Plane caps */ 1971 dcn32_hw_sequencer_init_functions(dc); 1972 1973 dc->caps.max_planes = pool->base.pipe_count; 1974 1975 for (i = 0; i < dc->caps.max_planes; ++i) 1976 dc->caps.planes[i] = plane_cap; 1977 1978 dc->cap_funcs = cap_funcs; 1979 1980 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1981 ddc_init_data.ctx = dc->ctx; 1982 ddc_init_data.link = NULL; 1983 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1984 ddc_init_data.id.enum_id = 0; 1985 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1986 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 1987 } else { 1988 pool->base.oem_device = NULL; 1989 } 1990 1991 return true; 1992 1993 create_fail: 1994 1995 dcn321_resource_destruct(pool); 1996 1997 return false; 1998 } 1999 2000 struct resource_pool *dcn321_create_resource_pool( 2001 const struct dc_init_data *init_data, 2002 struct dc *dc) 2003 { 2004 struct dcn321_resource_pool *pool = 2005 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2006 2007 if (!pool) 2008 return NULL; 2009 2010 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2011 return &pool->base; 2012 2013 BREAK_TO_DEBUGGER(); 2014 kfree(pool); 2015 return NULL; 2016 } 2017