1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dcn31/dcn31_apg.h" 64 #include "dcn31/dcn31_dio_link_encoder.h" 65 #include "dcn32/dcn32_dio_link_encoder.h" 66 #include "dcn321_dio_link_encoder.h" 67 #include "dce/dce_clock_source.h" 68 #include "dce/dce_audio.h" 69 #include "dce/dce_hwseq.h" 70 #include "clk_mgr.h" 71 #include "virtual/virtual_stream_encoder.h" 72 #include "dml/display_mode_vba.h" 73 #include "dcn32/dcn32_dccg.h" 74 #include "dcn10/dcn10_resource.h" 75 #include "link.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 78 #include "dcn30/dcn30_dwb.h" 79 #include "dcn32/dcn32_mmhubbub.h" 80 81 #include "dcn/dcn_3_2_1_offset.h" 82 #include "dcn/dcn_3_2_1_sh_mask.h" 83 #include "nbio/nbio_4_3_0_offset.h" 84 85 #include "reg_helper.h" 86 #include "dce/dmub_abm.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dce_aux.h" 89 #include "dce/dce_i2c.h" 90 91 #include "dml/dcn30/display_mode_vba_30.h" 92 #include "vm_helper.h" 93 #include "dcn20/dcn20_vmid.h" 94 95 #define DC_LOGGER_INIT(logger) 96 97 enum dcn321_clk_src_array_id { 98 DCN321_CLK_SRC_PLL0, 99 DCN321_CLK_SRC_PLL1, 100 DCN321_CLK_SRC_PLL2, 101 DCN321_CLK_SRC_PLL3, 102 DCN321_CLK_SRC_PLL4, 103 DCN321_CLK_SRC_TOTAL 104 }; 105 106 /* begin ********************* 107 * macros to expend register list macro defined in HW object header file 108 */ 109 110 /* DCN */ 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id)\ 119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR_INIT(reg_name, id, value)\ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 175 .field_name = reg_name ## __ ## field_name ## post_fix 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 183 184 #define NBIO_BASE(seg) \ 185 NBIO_BASE_INNER(seg) 186 187 #define NBIO_SR(reg_name)\ 188 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 #define NBIO_SR_ARR(reg_name, id)\ 191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 192 regBIF_BX0_ ## reg_name 193 194 #define CTX ctx 195 #define REG(reg_name) \ 196 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 197 198 static struct bios_registers bios_regs; 199 200 #define bios_regs_init() \ 201 ( \ 202 NBIO_SR(BIOS_SCRATCH_3),\ 203 NBIO_SR(BIOS_SCRATCH_6)\ 204 ) 205 206 #define clk_src_regs_init(index, pllid)\ 207 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 208 209 static struct dce110_clk_src_regs clk_src_regs[5]; 210 211 static const struct dce110_clk_src_shift cs_shift = { 212 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 213 }; 214 215 static const struct dce110_clk_src_mask cs_mask = { 216 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 217 }; 218 219 #define abm_regs_init(id)\ 220 ABM_DCN32_REG_LIST_RI(id) 221 222 static struct dce_abm_registers abm_regs[4]; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN32(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN32(_MASK) 230 }; 231 232 #define audio_regs_init(id)\ 233 AUD_COMMON_REG_LIST_RI(id) 234 235 static struct dce_audio_registers audio_regs[5]; 236 237 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 238 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 240 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 241 242 static const struct dce_audio_shift audio_shift = { 243 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 244 }; 245 246 static const struct dce_audio_mask audio_mask = { 247 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 248 }; 249 250 #define vpg_regs_init(id)\ 251 VPG_DCN3_REG_LIST_RI(id) 252 253 static struct dcn30_vpg_registers vpg_regs[10]; 254 255 static const struct dcn30_vpg_shift vpg_shift = { 256 DCN3_VPG_MASK_SH_LIST(__SHIFT) 257 }; 258 259 static const struct dcn30_vpg_mask vpg_mask = { 260 DCN3_VPG_MASK_SH_LIST(_MASK) 261 }; 262 263 #define afmt_regs_init(id)\ 264 AFMT_DCN3_REG_LIST_RI(id) 265 266 static struct dcn30_afmt_registers afmt_regs[6]; 267 268 static const struct dcn30_afmt_shift afmt_shift = { 269 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 270 }; 271 272 static const struct dcn30_afmt_mask afmt_mask = { 273 DCN3_AFMT_MASK_SH_LIST(_MASK) 274 }; 275 276 #define apg_regs_init(id)\ 277 APG_DCN31_REG_LIST_RI(id) 278 279 static struct dcn31_apg_registers apg_regs[4]; 280 281 static const struct dcn31_apg_shift apg_shift = { 282 DCN31_APG_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dcn31_apg_mask apg_mask = { 286 DCN31_APG_MASK_SH_LIST(_MASK) 287 }; 288 289 #define stream_enc_regs_init(id)\ 290 SE_DCN32_REG_LIST_RI(id) 291 292 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 293 294 static const struct dcn10_stream_encoder_shift se_shift = { 295 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 296 }; 297 298 static const struct dcn10_stream_encoder_mask se_mask = { 299 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 300 }; 301 302 303 #define aux_regs_init(id)\ 304 DCN2_AUX_REG_LIST_RI(id) 305 306 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 307 308 #define hpd_regs_init(id)\ 309 HPD_REG_LIST_RI(id) 310 311 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 312 313 #define link_regs_init(id, phyid)\ 314 ( \ 315 LE_DCN31_REG_LIST_RI(id), \ 316 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 317 ) 318 /*DPCS_DCN31_REG_LIST(id),*/ \ 319 320 static struct dcn10_link_enc_registers link_enc_regs[5]; 321 322 static const struct dcn10_link_enc_shift le_shift = { 323 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 324 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dcn10_link_enc_mask le_mask = { 328 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 329 // DPCS_DCN31_MASK_SH_LIST(_MASK) 330 }; 331 332 #define hpo_dp_stream_encoder_reg_init(id)\ 333 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 334 335 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 336 337 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 338 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 343 }; 344 345 346 #define hpo_dp_link_encoder_reg_init(id)\ 347 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 352 353 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 354 355 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 356 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 361 }; 362 363 #define dpp_regs_init(id)\ 364 DPP_REG_LIST_DCN30_COMMON_RI(id) 365 366 static struct dcn3_dpp_registers dpp_regs[4]; 367 368 static const struct dcn3_dpp_shift tf_shift = { 369 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 370 }; 371 372 static const struct dcn3_dpp_mask tf_mask = { 373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 374 }; 375 376 377 #define opp_regs_init(id)\ 378 OPP_REG_LIST_DCN30_RI(id) 379 380 static struct dcn20_opp_registers opp_regs[4]; 381 382 static const struct dcn20_opp_shift opp_shift = { 383 OPP_MASK_SH_LIST_DCN20(__SHIFT) 384 }; 385 386 static const struct dcn20_opp_mask opp_mask = { 387 OPP_MASK_SH_LIST_DCN20(_MASK) 388 }; 389 390 #define aux_engine_regs_init(id) \ 391 ( \ 392 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 #define dcn_mpc_regs_init()\ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id) \ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 static const struct dcn_hubp2_shift hubp_shift = { 486 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 487 }; 488 489 static const struct dcn_hubp2_mask hubp_mask = { 490 HUBP_MASK_SH_LIST_DCN32(_MASK) 491 }; 492 493 static struct dcn_hubbub_registers hubbub_reg; 494 #define hubbub_reg_init()\ 495 HUBBUB_REG_LIST_DCN32_RI(0) 496 497 static const struct dcn_hubbub_shift hubbub_shift = { 498 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 499 }; 500 501 static const struct dcn_hubbub_mask hubbub_mask = { 502 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 503 }; 504 505 static struct dccg_registers dccg_regs; 506 507 #define dccg_regs_init()\ 508 DCCG_REG_LIST_DCN32_RI() 509 510 static const struct dccg_shift dccg_shift = { 511 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 512 }; 513 514 static const struct dccg_mask dccg_mask = { 515 DCCG_MASK_SH_LIST_DCN32(_MASK) 516 }; 517 518 519 #define SRII2(reg_name_pre, reg_name_post, id)\ 520 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 521 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 522 reg ## reg_name_pre ## id ## _ ## reg_name_post 523 524 525 #define HWSEQ_DCN32_REG_LIST()\ 526 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 527 SR(DIO_MEM_PWR_CTRL), \ 528 SR(ODM_MEM_PWR_CTRL3), \ 529 SR(MMHUBBUB_MEM_PWR_CNTL), \ 530 SR(DCCG_GATE_DISABLE_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL2), \ 532 SR(DCFCLK_CNTL),\ 533 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 534 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 536 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 542 SR(MICROSECOND_TIME_BASE_DIV), \ 543 SR(MILLISECOND_TIME_BASE_DIV), \ 544 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 545 SR(RBBMIF_TIMEOUT_DIS), \ 546 SR(RBBMIF_TIMEOUT_DIS_2), \ 547 SR(DCHUBBUB_CRC_CTRL), \ 548 SR(DPP_TOP0_DPP_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 551 SR(MPC_CRC_CTRL), \ 552 SR(MPC_CRC_RESULT_GB), \ 553 SR(MPC_CRC_RESULT_C), \ 554 SR(MPC_CRC_RESULT_AR), \ 555 SR(DOMAIN0_PG_CONFIG), \ 556 SR(DOMAIN1_PG_CONFIG), \ 557 SR(DOMAIN2_PG_CONFIG), \ 558 SR(DOMAIN3_PG_CONFIG), \ 559 SR(DOMAIN16_PG_CONFIG), \ 560 SR(DOMAIN17_PG_CONFIG), \ 561 SR(DOMAIN18_PG_CONFIG), \ 562 SR(DOMAIN19_PG_CONFIG), \ 563 SR(DOMAIN0_PG_STATUS), \ 564 SR(DOMAIN1_PG_STATUS), \ 565 SR(DOMAIN2_PG_STATUS), \ 566 SR(DOMAIN3_PG_STATUS), \ 567 SR(DOMAIN16_PG_STATUS), \ 568 SR(DOMAIN17_PG_STATUS), \ 569 SR(DOMAIN18_PG_STATUS), \ 570 SR(DOMAIN19_PG_STATUS), \ 571 SR(D1VGA_CONTROL), \ 572 SR(D2VGA_CONTROL), \ 573 SR(D3VGA_CONTROL), \ 574 SR(D4VGA_CONTROL), \ 575 SR(D5VGA_CONTROL), \ 576 SR(D6VGA_CONTROL), \ 577 SR(DC_IP_REQUEST_CNTL), \ 578 SR(AZALIA_AUDIO_DTO), \ 579 SR(AZALIA_CONTROLLER_CLOCK_GATING) 580 581 static struct dce_hwseq_registers hwseq_reg; 582 583 #define hwseq_reg_init()\ 584 HWSEQ_DCN32_REG_LIST() 585 586 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 587 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 588 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 589 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 591 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 606 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 616 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 618 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 619 620 static const struct dce_hwseq_shift hwseq_shift = { 621 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 622 }; 623 624 static const struct dce_hwseq_mask hwseq_mask = { 625 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 626 }; 627 #define vmid_regs_init(id)\ 628 DCN20_VMID_REG_LIST_RI(id) 629 630 static struct dcn_vmid_registers vmid_regs[16]; 631 632 static const struct dcn20_vmid_shift vmid_shifts = { 633 DCN20_VMID_MASK_SH_LIST(__SHIFT) 634 }; 635 636 static const struct dcn20_vmid_mask vmid_masks = { 637 DCN20_VMID_MASK_SH_LIST(_MASK) 638 }; 639 640 static const struct resource_caps res_cap_dcn321 = { 641 .num_timing_generator = 4, 642 .num_opp = 4, 643 .num_video_plane = 4, 644 .num_audio = 5, 645 .num_stream_encoder = 5, 646 .num_hpo_dp_stream_encoder = 4, 647 .num_hpo_dp_link_encoder = 2, 648 .num_pll = 5, 649 .num_dwb = 1, 650 .num_ddc = 5, 651 .num_vmid = 16, 652 .num_mpc_3dlut = 4, 653 .num_dsc = 4, 654 }; 655 656 static const struct dc_plane_cap plane_cap = { 657 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 658 .per_pixel_alpha = true, 659 660 .pixel_format_support = { 661 .argb8888 = true, 662 .nv12 = true, 663 .fp16 = true, 664 .p010 = true, 665 .ayuv = false, 666 }, 667 668 .max_upscale_factor = { 669 .argb8888 = 16000, 670 .nv12 = 16000, 671 .fp16 = 16000 672 }, 673 674 // 6:1 downscaling ratio: 1000/6 = 166.666 675 .max_downscale_factor = { 676 .argb8888 = 167, 677 .nv12 = 167, 678 .fp16 = 167 679 }, 680 64, 681 64 682 }; 683 684 static const struct dc_debug_options debug_defaults_drv = { 685 .disable_dmcu = true, 686 .force_abm_enable = false, 687 .timing_trace = false, 688 .clock_trace = true, 689 .disable_pplib_clock_request = false, 690 .pipe_split_policy = MPC_SPLIT_AVOID, 691 .force_single_disp_pipe_split = false, 692 .disable_dcc = DCC_ENABLE, 693 .vsr_support = true, 694 .performance_trace = false, 695 .max_downscale_src_width = 7680,/*upto 8K*/ 696 .disable_pplib_wm_range = false, 697 .scl_reset_length10 = true, 698 .sanity_checks = false, 699 .underflow_assert_delay_us = 0xFFFFFFFF, 700 .dwb_fi_phase = -1, // -1 = disable, 701 .dmub_command_table = true, 702 .enable_mem_low_power = { 703 .bits = { 704 .vga = false, 705 .i2c = false, 706 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 707 .dscl = false, 708 .cm = false, 709 .mpc = false, 710 .optc = true, 711 } 712 }, 713 .use_max_lb = true, 714 .force_disable_subvp = false, 715 .exit_idle_opt_for_cursor_updates = true, 716 .enable_single_display_2to1_odm_policy = true, 717 718 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 719 .enable_double_buffered_dsc_pg_support = true, 720 .enable_dp_dig_pixel_rate_div_policy = 1, 721 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 722 .alloc_extra_way_for_cursor = true, 723 .min_prefetch_in_strobe_ns = 60000, // 60us 724 .disable_unbounded_requesting = false, 725 .override_dispclk_programming = true, 726 .disable_fpo_optimizations = false, 727 .fpo_vactive_margin_us = 2000, // 2000us 728 .disable_fpo_vactive = false, 729 .disable_boot_optimizations = false, 730 .disable_subvp_high_refresh = false, 731 .fpo_vactive_min_active_margin_us = 200, 732 .fpo_vactive_max_blank_us = 1000, 733 }; 734 735 static struct dce_aux *dcn321_aux_engine_create( 736 struct dc_context *ctx, 737 uint32_t inst) 738 { 739 struct aux_engine_dce110 *aux_engine = 740 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 741 742 if (!aux_engine) 743 return NULL; 744 745 #undef REG_STRUCT 746 #define REG_STRUCT aux_engine_regs 747 aux_engine_regs_init(0), 748 aux_engine_regs_init(1), 749 aux_engine_regs_init(2), 750 aux_engine_regs_init(3), 751 aux_engine_regs_init(4); 752 753 dce110_aux_engine_construct(aux_engine, ctx, inst, 754 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 755 &aux_engine_regs[inst], 756 &aux_mask, 757 &aux_shift, 758 ctx->dc->caps.extended_aux_timeout_support); 759 760 return &aux_engine->base; 761 } 762 #define i2c_inst_regs_init(id)\ 763 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 764 765 static struct dce_i2c_registers i2c_hw_regs[5]; 766 767 static const struct dce_i2c_shift i2c_shifts = { 768 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 769 }; 770 771 static const struct dce_i2c_mask i2c_masks = { 772 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 773 }; 774 775 static struct dce_i2c_hw *dcn321_i2c_hw_create( 776 struct dc_context *ctx, 777 uint32_t inst) 778 { 779 struct dce_i2c_hw *dce_i2c_hw = 780 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 781 782 if (!dce_i2c_hw) 783 return NULL; 784 785 #undef REG_STRUCT 786 #define REG_STRUCT i2c_hw_regs 787 i2c_inst_regs_init(1), 788 i2c_inst_regs_init(2), 789 i2c_inst_regs_init(3), 790 i2c_inst_regs_init(4), 791 i2c_inst_regs_init(5); 792 793 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 794 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 795 796 return dce_i2c_hw; 797 } 798 799 static struct clock_source *dcn321_clock_source_create( 800 struct dc_context *ctx, 801 struct dc_bios *bios, 802 enum clock_source_id id, 803 const struct dce110_clk_src_regs *regs, 804 bool dp_clk_src) 805 { 806 struct dce110_clk_src *clk_src = 807 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 808 809 if (!clk_src) 810 return NULL; 811 812 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 813 regs, &cs_shift, &cs_mask)) { 814 clk_src->base.dp_clk_src = dp_clk_src; 815 return &clk_src->base; 816 } 817 818 kfree(clk_src); 819 BREAK_TO_DEBUGGER(); 820 return NULL; 821 } 822 823 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 824 { 825 int i; 826 827 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 828 GFP_KERNEL); 829 830 if (!hubbub2) 831 return NULL; 832 833 #undef REG_STRUCT 834 #define REG_STRUCT hubbub_reg 835 hubbub_reg_init(); 836 837 #undef REG_STRUCT 838 #define REG_STRUCT vmid_regs 839 vmid_regs_init(0), 840 vmid_regs_init(1), 841 vmid_regs_init(2), 842 vmid_regs_init(3), 843 vmid_regs_init(4), 844 vmid_regs_init(5), 845 vmid_regs_init(6), 846 vmid_regs_init(7), 847 vmid_regs_init(8), 848 vmid_regs_init(9), 849 vmid_regs_init(10), 850 vmid_regs_init(11), 851 vmid_regs_init(12), 852 vmid_regs_init(13), 853 vmid_regs_init(14), 854 vmid_regs_init(15); 855 856 hubbub32_construct(hubbub2, ctx, 857 &hubbub_reg, 858 &hubbub_shift, 859 &hubbub_mask, 860 ctx->dc->dml.ip.det_buffer_size_kbytes, 861 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 862 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 863 864 865 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 866 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 867 868 vmid->ctx = ctx; 869 870 vmid->regs = &vmid_regs[i]; 871 vmid->shifts = &vmid_shifts; 872 vmid->masks = &vmid_masks; 873 } 874 875 return &hubbub2->base; 876 } 877 878 static struct hubp *dcn321_hubp_create( 879 struct dc_context *ctx, 880 uint32_t inst) 881 { 882 struct dcn20_hubp *hubp2 = 883 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 884 885 if (!hubp2) 886 return NULL; 887 888 #undef REG_STRUCT 889 #define REG_STRUCT hubp_regs 890 hubp_regs_init(0), 891 hubp_regs_init(1), 892 hubp_regs_init(2), 893 hubp_regs_init(3); 894 895 if (hubp32_construct(hubp2, ctx, inst, 896 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 897 return &hubp2->base; 898 899 BREAK_TO_DEBUGGER(); 900 kfree(hubp2); 901 return NULL; 902 } 903 904 static void dcn321_dpp_destroy(struct dpp **dpp) 905 { 906 kfree(TO_DCN30_DPP(*dpp)); 907 *dpp = NULL; 908 } 909 910 static struct dpp *dcn321_dpp_create( 911 struct dc_context *ctx, 912 uint32_t inst) 913 { 914 struct dcn3_dpp *dpp3 = 915 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 916 917 if (!dpp3) 918 return NULL; 919 920 #undef REG_STRUCT 921 #define REG_STRUCT dpp_regs 922 dpp_regs_init(0), 923 dpp_regs_init(1), 924 dpp_regs_init(2), 925 dpp_regs_init(3); 926 927 if (dpp32_construct(dpp3, ctx, inst, 928 &dpp_regs[inst], &tf_shift, &tf_mask)) 929 return &dpp3->base; 930 931 BREAK_TO_DEBUGGER(); 932 kfree(dpp3); 933 return NULL; 934 } 935 936 static struct mpc *dcn321_mpc_create( 937 struct dc_context *ctx, 938 int num_mpcc, 939 int num_rmu) 940 { 941 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 942 GFP_KERNEL); 943 944 if (!mpc30) 945 return NULL; 946 947 #undef REG_STRUCT 948 #define REG_STRUCT mpc_regs 949 dcn_mpc_regs_init(); 950 951 dcn32_mpc_construct(mpc30, ctx, 952 &mpc_regs, 953 &mpc_shift, 954 &mpc_mask, 955 num_mpcc, 956 num_rmu); 957 958 return &mpc30->base; 959 } 960 961 static struct output_pixel_processor *dcn321_opp_create( 962 struct dc_context *ctx, uint32_t inst) 963 { 964 struct dcn20_opp *opp2 = 965 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 966 967 if (!opp2) { 968 BREAK_TO_DEBUGGER(); 969 return NULL; 970 } 971 972 #undef REG_STRUCT 973 #define REG_STRUCT opp_regs 974 opp_regs_init(0), 975 opp_regs_init(1), 976 opp_regs_init(2), 977 opp_regs_init(3); 978 979 dcn20_opp_construct(opp2, ctx, inst, 980 &opp_regs[inst], &opp_shift, &opp_mask); 981 return &opp2->base; 982 } 983 984 985 static struct timing_generator *dcn321_timing_generator_create( 986 struct dc_context *ctx, 987 uint32_t instance) 988 { 989 struct optc *tgn10 = 990 kzalloc(sizeof(struct optc), GFP_KERNEL); 991 992 if (!tgn10) 993 return NULL; 994 995 #undef REG_STRUCT 996 #define REG_STRUCT optc_regs 997 optc_regs_init(0), 998 optc_regs_init(1), 999 optc_regs_init(2), 1000 optc_regs_init(3); 1001 1002 tgn10->base.inst = instance; 1003 tgn10->base.ctx = ctx; 1004 1005 tgn10->tg_regs = &optc_regs[instance]; 1006 tgn10->tg_shift = &optc_shift; 1007 tgn10->tg_mask = &optc_mask; 1008 1009 dcn32_timing_generator_init(tgn10); 1010 1011 return &tgn10->base; 1012 } 1013 1014 static const struct encoder_feature_support link_enc_feature = { 1015 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1016 .max_hdmi_pixel_clock = 600000, 1017 .hdmi_ycbcr420_supported = true, 1018 .dp_ycbcr420_supported = true, 1019 .fec_supported = true, 1020 .flags.bits.IS_HBR2_CAPABLE = true, 1021 .flags.bits.IS_HBR3_CAPABLE = true, 1022 .flags.bits.IS_TPS3_CAPABLE = true, 1023 .flags.bits.IS_TPS4_CAPABLE = true 1024 }; 1025 1026 static struct link_encoder *dcn321_link_encoder_create( 1027 struct dc_context *ctx, 1028 const struct encoder_init_data *enc_init_data) 1029 { 1030 struct dcn20_link_encoder *enc20 = 1031 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1032 1033 if (!enc20) 1034 return NULL; 1035 1036 #undef REG_STRUCT 1037 #define REG_STRUCT link_enc_aux_regs 1038 aux_regs_init(0), 1039 aux_regs_init(1), 1040 aux_regs_init(2), 1041 aux_regs_init(3), 1042 aux_regs_init(4); 1043 1044 #undef REG_STRUCT 1045 #define REG_STRUCT link_enc_hpd_regs 1046 hpd_regs_init(0), 1047 hpd_regs_init(1), 1048 hpd_regs_init(2), 1049 hpd_regs_init(3), 1050 hpd_regs_init(4); 1051 1052 #undef REG_STRUCT 1053 #define REG_STRUCT link_enc_regs 1054 link_regs_init(0, A), 1055 link_regs_init(1, B), 1056 link_regs_init(2, C), 1057 link_regs_init(3, D), 1058 link_regs_init(4, E); 1059 1060 dcn321_link_encoder_construct(enc20, 1061 enc_init_data, 1062 &link_enc_feature, 1063 &link_enc_regs[enc_init_data->transmitter], 1064 &link_enc_aux_regs[enc_init_data->channel - 1], 1065 &link_enc_hpd_regs[enc_init_data->hpd_source], 1066 &le_shift, 1067 &le_mask); 1068 1069 return &enc20->enc10.base; 1070 } 1071 1072 static void read_dce_straps( 1073 struct dc_context *ctx, 1074 struct resource_straps *straps) 1075 { 1076 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1077 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1078 1079 } 1080 1081 static struct audio *dcn321_create_audio( 1082 struct dc_context *ctx, unsigned int inst) 1083 { 1084 1085 #undef REG_STRUCT 1086 #define REG_STRUCT audio_regs 1087 audio_regs_init(0), 1088 audio_regs_init(1), 1089 audio_regs_init(2), 1090 audio_regs_init(3), 1091 audio_regs_init(4); 1092 1093 return dce_audio_create(ctx, inst, 1094 &audio_regs[inst], &audio_shift, &audio_mask); 1095 } 1096 1097 static struct vpg *dcn321_vpg_create( 1098 struct dc_context *ctx, 1099 uint32_t inst) 1100 { 1101 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1102 1103 if (!vpg3) 1104 return NULL; 1105 1106 #undef REG_STRUCT 1107 #define REG_STRUCT vpg_regs 1108 vpg_regs_init(0), 1109 vpg_regs_init(1), 1110 vpg_regs_init(2), 1111 vpg_regs_init(3), 1112 vpg_regs_init(4), 1113 vpg_regs_init(5), 1114 vpg_regs_init(6), 1115 vpg_regs_init(7), 1116 vpg_regs_init(8), 1117 vpg_regs_init(9); 1118 1119 vpg3_construct(vpg3, ctx, inst, 1120 &vpg_regs[inst], 1121 &vpg_shift, 1122 &vpg_mask); 1123 1124 return &vpg3->base; 1125 } 1126 1127 static struct afmt *dcn321_afmt_create( 1128 struct dc_context *ctx, 1129 uint32_t inst) 1130 { 1131 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1132 1133 if (!afmt3) 1134 return NULL; 1135 1136 #undef REG_STRUCT 1137 #define REG_STRUCT afmt_regs 1138 afmt_regs_init(0), 1139 afmt_regs_init(1), 1140 afmt_regs_init(2), 1141 afmt_regs_init(3), 1142 afmt_regs_init(4), 1143 afmt_regs_init(5); 1144 1145 afmt3_construct(afmt3, ctx, inst, 1146 &afmt_regs[inst], 1147 &afmt_shift, 1148 &afmt_mask); 1149 1150 return &afmt3->base; 1151 } 1152 1153 static struct apg *dcn321_apg_create( 1154 struct dc_context *ctx, 1155 uint32_t inst) 1156 { 1157 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1158 1159 if (!apg31) 1160 return NULL; 1161 1162 #undef REG_STRUCT 1163 #define REG_STRUCT apg_regs 1164 apg_regs_init(0), 1165 apg_regs_init(1), 1166 apg_regs_init(2), 1167 apg_regs_init(3); 1168 1169 apg31_construct(apg31, ctx, inst, 1170 &apg_regs[inst], 1171 &apg_shift, 1172 &apg_mask); 1173 1174 return &apg31->base; 1175 } 1176 1177 static struct stream_encoder *dcn321_stream_encoder_create( 1178 enum engine_id eng_id, 1179 struct dc_context *ctx) 1180 { 1181 struct dcn10_stream_encoder *enc1; 1182 struct vpg *vpg; 1183 struct afmt *afmt; 1184 int vpg_inst; 1185 int afmt_inst; 1186 1187 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1188 if (eng_id <= ENGINE_ID_DIGF) { 1189 vpg_inst = eng_id; 1190 afmt_inst = eng_id; 1191 } else 1192 return NULL; 1193 1194 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1195 vpg = dcn321_vpg_create(ctx, vpg_inst); 1196 afmt = dcn321_afmt_create(ctx, afmt_inst); 1197 1198 if (!enc1 || !vpg || !afmt) { 1199 kfree(enc1); 1200 kfree(vpg); 1201 kfree(afmt); 1202 return NULL; 1203 } 1204 1205 #undef REG_STRUCT 1206 #define REG_STRUCT stream_enc_regs 1207 stream_enc_regs_init(0), 1208 stream_enc_regs_init(1), 1209 stream_enc_regs_init(2), 1210 stream_enc_regs_init(3), 1211 stream_enc_regs_init(4); 1212 1213 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1214 eng_id, vpg, afmt, 1215 &stream_enc_regs[eng_id], 1216 &se_shift, &se_mask); 1217 1218 return &enc1->base; 1219 } 1220 1221 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1222 enum engine_id eng_id, 1223 struct dc_context *ctx) 1224 { 1225 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1226 struct vpg *vpg; 1227 struct apg *apg; 1228 uint32_t hpo_dp_inst; 1229 uint32_t vpg_inst; 1230 uint32_t apg_inst; 1231 1232 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1233 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1234 1235 /* Mapping of VPG register blocks to HPO DP block instance: 1236 * VPG[6] -> HPO_DP[0] 1237 * VPG[7] -> HPO_DP[1] 1238 * VPG[8] -> HPO_DP[2] 1239 * VPG[9] -> HPO_DP[3] 1240 */ 1241 vpg_inst = hpo_dp_inst + 6; 1242 1243 /* Mapping of APG register blocks to HPO DP block instance: 1244 * APG[0] -> HPO_DP[0] 1245 * APG[1] -> HPO_DP[1] 1246 * APG[2] -> HPO_DP[2] 1247 * APG[3] -> HPO_DP[3] 1248 */ 1249 apg_inst = hpo_dp_inst; 1250 1251 /* allocate HPO stream encoder and create VPG sub-block */ 1252 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1253 vpg = dcn321_vpg_create(ctx, vpg_inst); 1254 apg = dcn321_apg_create(ctx, apg_inst); 1255 1256 if (!hpo_dp_enc31 || !vpg || !apg) { 1257 kfree(hpo_dp_enc31); 1258 kfree(vpg); 1259 kfree(apg); 1260 return NULL; 1261 } 1262 1263 #undef REG_STRUCT 1264 #define REG_STRUCT hpo_dp_stream_enc_regs 1265 hpo_dp_stream_encoder_reg_init(0), 1266 hpo_dp_stream_encoder_reg_init(1), 1267 hpo_dp_stream_encoder_reg_init(2), 1268 hpo_dp_stream_encoder_reg_init(3); 1269 1270 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1271 hpo_dp_inst, eng_id, vpg, apg, 1272 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1273 &hpo_dp_se_shift, &hpo_dp_se_mask); 1274 1275 return &hpo_dp_enc31->base; 1276 } 1277 1278 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1279 uint8_t inst, 1280 struct dc_context *ctx) 1281 { 1282 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1283 1284 /* allocate HPO link encoder */ 1285 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1286 1287 #undef REG_STRUCT 1288 #define REG_STRUCT hpo_dp_link_enc_regs 1289 hpo_dp_link_encoder_reg_init(0), 1290 hpo_dp_link_encoder_reg_init(1); 1291 1292 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1293 &hpo_dp_link_enc_regs[inst], 1294 &hpo_dp_le_shift, &hpo_dp_le_mask); 1295 1296 return &hpo_dp_enc31->base; 1297 } 1298 1299 static struct dce_hwseq *dcn321_hwseq_create( 1300 struct dc_context *ctx) 1301 { 1302 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1303 1304 #undef REG_STRUCT 1305 #define REG_STRUCT hwseq_reg 1306 hwseq_reg_init(); 1307 1308 if (hws) { 1309 hws->ctx = ctx; 1310 hws->regs = &hwseq_reg; 1311 hws->shifts = &hwseq_shift; 1312 hws->masks = &hwseq_mask; 1313 } 1314 return hws; 1315 } 1316 static const struct resource_create_funcs res_create_funcs = { 1317 .read_dce_straps = read_dce_straps, 1318 .create_audio = dcn321_create_audio, 1319 .create_stream_encoder = dcn321_stream_encoder_create, 1320 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1321 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1322 .create_hwseq = dcn321_hwseq_create, 1323 }; 1324 1325 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1326 { 1327 unsigned int i; 1328 1329 for (i = 0; i < pool->base.stream_enc_count; i++) { 1330 if (pool->base.stream_enc[i] != NULL) { 1331 if (pool->base.stream_enc[i]->vpg != NULL) { 1332 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1333 pool->base.stream_enc[i]->vpg = NULL; 1334 } 1335 if (pool->base.stream_enc[i]->afmt != NULL) { 1336 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1337 pool->base.stream_enc[i]->afmt = NULL; 1338 } 1339 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1340 pool->base.stream_enc[i] = NULL; 1341 } 1342 } 1343 1344 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1345 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1346 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1347 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1348 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1349 } 1350 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1351 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1352 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1353 } 1354 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1355 pool->base.hpo_dp_stream_enc[i] = NULL; 1356 } 1357 } 1358 1359 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1360 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1361 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1362 pool->base.hpo_dp_link_enc[i] = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1367 if (pool->base.dscs[i] != NULL) 1368 dcn20_dsc_destroy(&pool->base.dscs[i]); 1369 } 1370 1371 if (pool->base.mpc != NULL) { 1372 kfree(TO_DCN20_MPC(pool->base.mpc)); 1373 pool->base.mpc = NULL; 1374 } 1375 if (pool->base.hubbub != NULL) { 1376 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1377 pool->base.hubbub = NULL; 1378 } 1379 for (i = 0; i < pool->base.pipe_count; i++) { 1380 if (pool->base.dpps[i] != NULL) 1381 dcn321_dpp_destroy(&pool->base.dpps[i]); 1382 1383 if (pool->base.ipps[i] != NULL) 1384 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1385 1386 if (pool->base.hubps[i] != NULL) { 1387 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1388 pool->base.hubps[i] = NULL; 1389 } 1390 1391 if (pool->base.irqs != NULL) 1392 dal_irq_service_destroy(&pool->base.irqs); 1393 } 1394 1395 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1396 if (pool->base.engines[i] != NULL) 1397 dce110_engine_destroy(&pool->base.engines[i]); 1398 if (pool->base.hw_i2cs[i] != NULL) { 1399 kfree(pool->base.hw_i2cs[i]); 1400 pool->base.hw_i2cs[i] = NULL; 1401 } 1402 if (pool->base.sw_i2cs[i] != NULL) { 1403 kfree(pool->base.sw_i2cs[i]); 1404 pool->base.sw_i2cs[i] = NULL; 1405 } 1406 } 1407 1408 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1409 if (pool->base.opps[i] != NULL) 1410 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1411 } 1412 1413 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1414 if (pool->base.timing_generators[i] != NULL) { 1415 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1416 pool->base.timing_generators[i] = NULL; 1417 } 1418 } 1419 1420 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1421 if (pool->base.dwbc[i] != NULL) { 1422 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1423 pool->base.dwbc[i] = NULL; 1424 } 1425 if (pool->base.mcif_wb[i] != NULL) { 1426 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1427 pool->base.mcif_wb[i] = NULL; 1428 } 1429 } 1430 1431 for (i = 0; i < pool->base.audio_count; i++) { 1432 if (pool->base.audios[i]) 1433 dce_aud_destroy(&pool->base.audios[i]); 1434 } 1435 1436 for (i = 0; i < pool->base.clk_src_count; i++) { 1437 if (pool->base.clock_sources[i] != NULL) { 1438 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1439 pool->base.clock_sources[i] = NULL; 1440 } 1441 } 1442 1443 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1444 if (pool->base.mpc_lut[i] != NULL) { 1445 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1446 pool->base.mpc_lut[i] = NULL; 1447 } 1448 if (pool->base.mpc_shaper[i] != NULL) { 1449 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1450 pool->base.mpc_shaper[i] = NULL; 1451 } 1452 } 1453 1454 if (pool->base.dp_clock_source != NULL) { 1455 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1456 pool->base.dp_clock_source = NULL; 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1460 if (pool->base.multiple_abms[i] != NULL) 1461 dce_abm_destroy(&pool->base.multiple_abms[i]); 1462 } 1463 1464 if (pool->base.psr != NULL) 1465 dmub_psr_destroy(&pool->base.psr); 1466 1467 if (pool->base.dccg != NULL) 1468 dcn_dccg_destroy(&pool->base.dccg); 1469 1470 if (pool->base.oem_device != NULL) { 1471 struct dc *dc = pool->base.oem_device->ctx->dc; 1472 1473 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1474 } 1475 } 1476 1477 1478 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1479 { 1480 int i; 1481 uint32_t dwb_count = pool->res_cap->num_dwb; 1482 1483 for (i = 0; i < dwb_count; i++) { 1484 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1485 GFP_KERNEL); 1486 1487 if (!dwbc30) { 1488 dm_error("DC: failed to create dwbc30!\n"); 1489 return false; 1490 } 1491 1492 #undef REG_STRUCT 1493 #define REG_STRUCT dwbc30_regs 1494 dwbc_regs_dcn3_init(0); 1495 1496 dcn30_dwbc_construct(dwbc30, ctx, 1497 &dwbc30_regs[i], 1498 &dwbc30_shift, 1499 &dwbc30_mask, 1500 i); 1501 1502 pool->dwbc[i] = &dwbc30->base; 1503 } 1504 return true; 1505 } 1506 1507 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1508 { 1509 int i; 1510 uint32_t dwb_count = pool->res_cap->num_dwb; 1511 1512 for (i = 0; i < dwb_count; i++) { 1513 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1514 GFP_KERNEL); 1515 1516 if (!mcif_wb30) { 1517 dm_error("DC: failed to create mcif_wb30!\n"); 1518 return false; 1519 } 1520 1521 #undef REG_STRUCT 1522 #define REG_STRUCT mcif_wb30_regs 1523 mcif_wb_regs_dcn3_init(0); 1524 1525 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1526 &mcif_wb30_regs[i], 1527 &mcif_wb30_shift, 1528 &mcif_wb30_mask, 1529 i); 1530 1531 pool->mcif_wb[i] = &mcif_wb30->base; 1532 } 1533 return true; 1534 } 1535 1536 static struct display_stream_compressor *dcn321_dsc_create( 1537 struct dc_context *ctx, uint32_t inst) 1538 { 1539 struct dcn20_dsc *dsc = 1540 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1541 1542 if (!dsc) { 1543 BREAK_TO_DEBUGGER(); 1544 return NULL; 1545 } 1546 1547 #undef REG_STRUCT 1548 #define REG_STRUCT dsc_regs 1549 dsc_regsDCN20_init(0), 1550 dsc_regsDCN20_init(1), 1551 dsc_regsDCN20_init(2), 1552 dsc_regsDCN20_init(3); 1553 1554 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1555 1556 dsc->max_image_width = 6016; 1557 1558 return &dsc->base; 1559 } 1560 1561 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1562 { 1563 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1564 1565 dcn321_resource_destruct(dcn321_pool); 1566 kfree(dcn321_pool); 1567 *pool = NULL; 1568 } 1569 1570 static struct dc_cap_funcs cap_funcs = { 1571 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1572 }; 1573 1574 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1575 { 1576 DC_FP_START(); 1577 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1578 DC_FP_END(); 1579 } 1580 1581 static struct resource_funcs dcn321_res_pool_funcs = { 1582 .destroy = dcn321_destroy_resource_pool, 1583 .link_enc_create = dcn321_link_encoder_create, 1584 .link_enc_create_minimal = NULL, 1585 .panel_cntl_create = dcn32_panel_cntl_create, 1586 .validate_bandwidth = dcn32_validate_bandwidth, 1587 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1588 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1589 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1590 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1591 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1592 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1593 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1594 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1595 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1596 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1597 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1598 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1599 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1600 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1601 .add_phantom_pipes = dcn32_add_phantom_pipes, 1602 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1603 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 1604 .save_mall_state = dcn32_save_mall_state, 1605 .restore_mall_state = dcn32_restore_mall_state, 1606 }; 1607 1608 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1609 { 1610 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1611 /* DCN321 support max 4 pipes */ 1612 value = value & 0xf; 1613 return value; 1614 } 1615 1616 1617 static bool dcn321_resource_construct( 1618 uint8_t num_virtual_links, 1619 struct dc *dc, 1620 struct dcn321_resource_pool *pool) 1621 { 1622 int i, j; 1623 struct dc_context *ctx = dc->ctx; 1624 struct irq_service_init_data init_data; 1625 struct ddc_service_init_data ddc_init_data = {0}; 1626 uint32_t pipe_fuses = 0; 1627 uint32_t num_pipes = 4; 1628 1629 #undef REG_STRUCT 1630 #define REG_STRUCT bios_regs 1631 bios_regs_init(); 1632 1633 #undef REG_STRUCT 1634 #define REG_STRUCT clk_src_regs 1635 clk_src_regs_init(0, A), 1636 clk_src_regs_init(1, B), 1637 clk_src_regs_init(2, C), 1638 clk_src_regs_init(3, D), 1639 clk_src_regs_init(4, E); 1640 1641 #undef REG_STRUCT 1642 #define REG_STRUCT abm_regs 1643 abm_regs_init(0), 1644 abm_regs_init(1), 1645 abm_regs_init(2), 1646 abm_regs_init(3); 1647 1648 #undef REG_STRUCT 1649 #define REG_STRUCT dccg_regs 1650 dccg_regs_init(); 1651 1652 1653 ctx->dc_bios->regs = &bios_regs; 1654 1655 pool->base.res_cap = &res_cap_dcn321; 1656 /* max number of pipes for ASIC before checking for pipe fuses */ 1657 num_pipes = pool->base.res_cap->num_timing_generator; 1658 pipe_fuses = read_pipe_fuses(ctx); 1659 1660 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1661 if (pipe_fuses & 1 << i) 1662 num_pipes--; 1663 1664 if (pipe_fuses & 1) 1665 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1666 1667 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1668 ASSERT(0); //Entire DCN is harvested! 1669 1670 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1671 * value will be changed, update max_num_dpp and max_num_otg for dml. 1672 */ 1673 dcn3_21_ip.max_num_dpp = num_pipes; 1674 dcn3_21_ip.max_num_otg = num_pipes; 1675 1676 pool->base.funcs = &dcn321_res_pool_funcs; 1677 1678 /************************************************* 1679 * Resource + asic cap harcoding * 1680 *************************************************/ 1681 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1682 pool->base.timing_generator_count = num_pipes; 1683 pool->base.pipe_count = num_pipes; 1684 pool->base.mpcc_count = num_pipes; 1685 dc->caps.max_downscale_ratio = 600; 1686 dc->caps.i2c_speed_in_khz = 100; 1687 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1688 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1689 dc->caps.max_cursor_size = 64; 1690 dc->caps.min_horizontal_blanking_period = 80; 1691 dc->caps.dmdata_alloc_size = 2048; 1692 dc->caps.mall_size_per_mem_channel = 4; 1693 dc->caps.mall_size_total = 0; 1694 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1695 dc->caps.cache_line_size = 64; 1696 dc->caps.cache_num_ways = 16; 1697 1698 /* Calculate the available MALL space */ 1699 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 1700 dc, dc->ctx->dc_bios->vram_info.num_chans) * 1701 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1702 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1703 1704 dc->caps.subvp_fw_processing_delay_us = 15; 1705 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1706 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1707 dc->caps.subvp_swath_height_margin_lines = 16; 1708 dc->caps.subvp_pstate_allow_width_us = 20; 1709 dc->caps.subvp_vertical_int_margin_us = 30; 1710 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1711 dc->caps.max_slave_planes = 2; 1712 dc->caps.max_slave_yuv_planes = 2; 1713 dc->caps.max_slave_rgb_planes = 2; 1714 dc->caps.post_blend_color_processing = true; 1715 dc->caps.force_dp_tps4_for_cp2520 = true; 1716 dc->caps.dp_hpo = true; 1717 dc->caps.dp_hdmi21_pcon_support = true; 1718 dc->caps.edp_dsc_support = true; 1719 dc->caps.extended_aux_timeout_support = true; 1720 dc->caps.dmcub_support = true; 1721 dc->caps.max_v_total = (1 << 15) - 1; 1722 1723 /* Color pipeline capabilities */ 1724 dc->caps.color.dpp.dcn_arch = 1; 1725 dc->caps.color.dpp.input_lut_shared = 0; 1726 dc->caps.color.dpp.icsc = 1; 1727 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1728 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1729 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1730 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1731 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1732 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1733 dc->caps.color.dpp.post_csc = 1; 1734 dc->caps.color.dpp.gamma_corr = 1; 1735 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1736 1737 dc->caps.color.dpp.hw_3d_lut = 1; 1738 dc->caps.color.dpp.ogam_ram = 1; 1739 // no OGAM ROM on DCN2 and later ASICs 1740 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1741 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1742 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1743 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1744 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1745 dc->caps.color.dpp.ocsc = 0; 1746 1747 dc->caps.color.mpc.gamut_remap = 1; 1748 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1749 dc->caps.color.mpc.ogam_ram = 1; 1750 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1751 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1752 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1753 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1754 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1755 dc->caps.color.mpc.ocsc = 1; 1756 1757 /* read VBIOS LTTPR caps */ 1758 { 1759 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1760 enum bp_result bp_query_result; 1761 uint8_t is_vbios_lttpr_enable = 0; 1762 1763 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1764 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1765 } 1766 1767 /* interop bit is implicit */ 1768 { 1769 dc->caps.vbios_lttpr_aware = true; 1770 } 1771 } 1772 1773 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1774 dc->debug = debug_defaults_drv; 1775 1776 // Init the vm_helper 1777 if (dc->vm_helper) 1778 vm_helper_init(dc->vm_helper, 16); 1779 1780 /************************************************* 1781 * Create resources * 1782 *************************************************/ 1783 1784 /* Clock Sources for Pixel Clock*/ 1785 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1786 dcn321_clock_source_create(ctx, ctx->dc_bios, 1787 CLOCK_SOURCE_COMBO_PHY_PLL0, 1788 &clk_src_regs[0], false); 1789 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1790 dcn321_clock_source_create(ctx, ctx->dc_bios, 1791 CLOCK_SOURCE_COMBO_PHY_PLL1, 1792 &clk_src_regs[1], false); 1793 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1794 dcn321_clock_source_create(ctx, ctx->dc_bios, 1795 CLOCK_SOURCE_COMBO_PHY_PLL2, 1796 &clk_src_regs[2], false); 1797 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1798 dcn321_clock_source_create(ctx, ctx->dc_bios, 1799 CLOCK_SOURCE_COMBO_PHY_PLL3, 1800 &clk_src_regs[3], false); 1801 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1802 dcn321_clock_source_create(ctx, ctx->dc_bios, 1803 CLOCK_SOURCE_COMBO_PHY_PLL4, 1804 &clk_src_regs[4], false); 1805 1806 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1807 1808 /* todo: not reuse phy_pll registers */ 1809 pool->base.dp_clock_source = 1810 dcn321_clock_source_create(ctx, ctx->dc_bios, 1811 CLOCK_SOURCE_ID_DP_DTO, 1812 &clk_src_regs[0], true); 1813 1814 for (i = 0; i < pool->base.clk_src_count; i++) { 1815 if (pool->base.clock_sources[i] == NULL) { 1816 dm_error("DC: failed to create clock sources!\n"); 1817 BREAK_TO_DEBUGGER(); 1818 goto create_fail; 1819 } 1820 } 1821 1822 /* DCCG */ 1823 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1824 if (pool->base.dccg == NULL) { 1825 dm_error("DC: failed to create dccg!\n"); 1826 BREAK_TO_DEBUGGER(); 1827 goto create_fail; 1828 } 1829 1830 /* DML */ 1831 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1832 1833 /* IRQ Service */ 1834 init_data.ctx = dc->ctx; 1835 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1836 if (!pool->base.irqs) 1837 goto create_fail; 1838 1839 /* HUBBUB */ 1840 pool->base.hubbub = dcn321_hubbub_create(ctx); 1841 if (pool->base.hubbub == NULL) { 1842 BREAK_TO_DEBUGGER(); 1843 dm_error("DC: failed to create hubbub!\n"); 1844 goto create_fail; 1845 } 1846 1847 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1848 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1849 1850 /* if pipe is disabled, skip instance of HW pipe, 1851 * i.e, skip ASIC register instance 1852 */ 1853 if (pipe_fuses & 1 << i) 1854 continue; 1855 1856 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1857 if (pool->base.hubps[j] == NULL) { 1858 BREAK_TO_DEBUGGER(); 1859 dm_error( 1860 "DC: failed to create hubps!\n"); 1861 goto create_fail; 1862 } 1863 1864 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1865 if (pool->base.dpps[j] == NULL) { 1866 BREAK_TO_DEBUGGER(); 1867 dm_error( 1868 "DC: failed to create dpps!\n"); 1869 goto create_fail; 1870 } 1871 1872 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1873 if (pool->base.opps[j] == NULL) { 1874 BREAK_TO_DEBUGGER(); 1875 dm_error( 1876 "DC: failed to create output pixel processor!\n"); 1877 goto create_fail; 1878 } 1879 1880 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1881 ctx, i); 1882 if (pool->base.timing_generators[j] == NULL) { 1883 BREAK_TO_DEBUGGER(); 1884 dm_error("DC: failed to create tg!\n"); 1885 goto create_fail; 1886 } 1887 1888 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1889 &abm_regs[i], 1890 &abm_shift, 1891 &abm_mask); 1892 if (pool->base.multiple_abms[j] == NULL) { 1893 dm_error("DC: failed to create abm for pipe %d!\n", i); 1894 BREAK_TO_DEBUGGER(); 1895 goto create_fail; 1896 } 1897 1898 /* index for resource pool arrays for next valid pipe */ 1899 j++; 1900 } 1901 1902 /* PSR */ 1903 pool->base.psr = dmub_psr_create(ctx); 1904 if (pool->base.psr == NULL) { 1905 dm_error("DC: failed to create psr obj!\n"); 1906 BREAK_TO_DEBUGGER(); 1907 goto create_fail; 1908 } 1909 1910 /* MPCCs */ 1911 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1912 if (pool->base.mpc == NULL) { 1913 BREAK_TO_DEBUGGER(); 1914 dm_error("DC: failed to create mpc!\n"); 1915 goto create_fail; 1916 } 1917 1918 /* DSCs */ 1919 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1920 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1921 if (pool->base.dscs[i] == NULL) { 1922 BREAK_TO_DEBUGGER(); 1923 dm_error("DC: failed to create display stream compressor %d!\n", i); 1924 goto create_fail; 1925 } 1926 } 1927 1928 /* DWB */ 1929 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1930 BREAK_TO_DEBUGGER(); 1931 dm_error("DC: failed to create dwbc!\n"); 1932 goto create_fail; 1933 } 1934 1935 /* MMHUBBUB */ 1936 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1937 BREAK_TO_DEBUGGER(); 1938 dm_error("DC: failed to create mcif_wb!\n"); 1939 goto create_fail; 1940 } 1941 1942 /* AUX and I2C */ 1943 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1944 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1945 if (pool->base.engines[i] == NULL) { 1946 BREAK_TO_DEBUGGER(); 1947 dm_error( 1948 "DC:failed to create aux engine!!\n"); 1949 goto create_fail; 1950 } 1951 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1952 if (pool->base.hw_i2cs[i] == NULL) { 1953 BREAK_TO_DEBUGGER(); 1954 dm_error( 1955 "DC:failed to create hw i2c!!\n"); 1956 goto create_fail; 1957 } 1958 pool->base.sw_i2cs[i] = NULL; 1959 } 1960 1961 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1962 if (!resource_construct(num_virtual_links, dc, &pool->base, 1963 &res_create_funcs)) 1964 goto create_fail; 1965 1966 /* HW Sequencer init functions and Plane caps */ 1967 dcn32_hw_sequencer_init_functions(dc); 1968 1969 dc->caps.max_planes = pool->base.pipe_count; 1970 1971 for (i = 0; i < dc->caps.max_planes; ++i) 1972 dc->caps.planes[i] = plane_cap; 1973 1974 dc->cap_funcs = cap_funcs; 1975 1976 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1977 ddc_init_data.ctx = dc->ctx; 1978 ddc_init_data.link = NULL; 1979 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1980 ddc_init_data.id.enum_id = 0; 1981 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1982 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1983 } else { 1984 pool->base.oem_device = NULL; 1985 } 1986 1987 return true; 1988 1989 create_fail: 1990 1991 dcn321_resource_destruct(pool); 1992 1993 return false; 1994 } 1995 1996 struct resource_pool *dcn321_create_resource_pool( 1997 const struct dc_init_data *init_data, 1998 struct dc *dc) 1999 { 2000 struct dcn321_resource_pool *pool = 2001 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2002 2003 if (!pool) 2004 return NULL; 2005 2006 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2007 return &pool->base; 2008 2009 BREAK_TO_DEBUGGER(); 2010 kfree(pool); 2011 return NULL; 2012 } 2013