1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dc_link_dp.h" 64 #include "dcn31/dcn31_apg.h" 65 #include "dcn31/dcn31_dio_link_encoder.h" 66 #include "dcn32/dcn32_dio_link_encoder.h" 67 #include "dcn321_dio_link_encoder.h" 68 #include "dce/dce_clock_source.h" 69 #include "dce/dce_audio.h" 70 #include "dce/dce_hwseq.h" 71 #include "clk_mgr.h" 72 #include "virtual/virtual_stream_encoder.h" 73 #include "dml/display_mode_vba.h" 74 #include "dcn32/dcn32_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dc_link_ddc.h" 77 #include "dcn31/dcn31_panel_cntl.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn32/dcn32_mmhubbub.h" 81 82 #include "dcn/dcn_3_2_1_offset.h" 83 #include "dcn/dcn_3_2_1_sh_mask.h" 84 #include "nbio/nbio_4_3_0_offset.h" 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #define DC_LOGGER_INIT(logger) 97 #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) 98 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 99 100 enum dcn321_clk_src_array_id { 101 DCN321_CLK_SRC_PLL0, 102 DCN321_CLK_SRC_PLL1, 103 DCN321_CLK_SRC_PLL2, 104 DCN321_CLK_SRC_PLL3, 105 DCN321_CLK_SRC_PLL4, 106 DCN321_CLK_SRC_TOTAL 107 }; 108 109 /* begin ********************* 110 * macros to expend register list macro defined in HW object header file 111 */ 112 113 /* DCN */ 114 /* TODO awful hack. fixup dcn20_dwb.h */ 115 #undef BASE_INNER 116 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 117 118 #define BASE(seg) BASE_INNER(seg) 119 120 #define SR(reg_name)\ 121 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 122 reg ## reg_name 123 #define SR_ARR(reg_name, id)\ 124 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 125 reg ## reg_name 126 #define SR_ARR_INIT(reg_name, id, value)\ 127 REG_STRUCT[id].reg_name = value 128 129 #define SRI(reg_name, block, id)\ 130 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 131 reg ## block ## id ## _ ## reg_name 132 133 #define SRI_ARR(reg_name, block, id)\ 134 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 reg ## block ## id ## _ ## reg_name 136 137 #define SR_ARR_I2C(reg_name, id) \ 138 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 139 140 #define SRI_ARR_I2C(reg_name, block, id)\ 141 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 reg ## block ## id ## _ ## reg_name 143 144 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 145 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 146 reg ## block ## id ## _ ## reg_name 147 148 #define SRI2(reg_name, block, id)\ 149 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 150 reg ## reg_name 151 #define SRI2_ARR(reg_name, block, id)\ 152 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 153 reg ## reg_name 154 155 #define SRIR(var_name, reg_name, block, id)\ 156 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII(reg_name, block, id)\ 160 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_ARR_2(reg_name, block, id, inst)\ 164 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRII_MPC_RMU(reg_name, block, id)\ 168 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 169 reg ## block ## id ## _ ## reg_name 170 171 #define SRII_DWB(reg_name, temp_name, block, id)\ 172 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## temp_name 174 175 #define DCCG_SRII(reg_name, block, id)\ 176 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179 #define VUPDATE_SRII(reg_name, block, id)\ 180 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 181 reg ## reg_name ## _ ## block ## id 182 183 /* NBIO */ 184 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 185 186 #define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189 #define NBIO_SR(reg_name)\ 190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 191 regBIF_BX0_ ## reg_name 192 #define NBIO_SR_ARR(reg_name, id)\ 193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 194 regBIF_BX0_ ## reg_name 195 196 #define CTX ctx 197 #define REG(reg_name) \ 198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 199 200 static struct bios_registers bios_regs; 201 202 #define bios_regs_init() \ 203 ( \ 204 NBIO_SR(BIOS_SCRATCH_3),\ 205 NBIO_SR(BIOS_SCRATCH_6)\ 206 ) 207 208 #define clk_src_regs_init(index, pllid)\ 209 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 210 211 static struct dce110_clk_src_regs clk_src_regs[5]; 212 213 static const struct dce110_clk_src_shift cs_shift = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 215 }; 216 217 static const struct dce110_clk_src_mask cs_mask = { 218 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 219 }; 220 221 #define abm_regs_init(id)\ 222 ABM_DCN32_REG_LIST_RI(id) 223 224 static struct dce_abm_registers abm_regs[4]; 225 226 static const struct dce_abm_shift abm_shift = { 227 ABM_MASK_SH_LIST_DCN32(__SHIFT) 228 }; 229 230 static const struct dce_abm_mask abm_mask = { 231 ABM_MASK_SH_LIST_DCN32(_MASK) 232 }; 233 234 #define audio_regs_init(id)\ 235 AUD_COMMON_REG_LIST_RI(id) 236 237 static struct dce_audio_registers audio_regs[5]; 238 239 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 242 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 243 244 static const struct dce_audio_shift audio_shift = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 246 }; 247 248 static const struct dce_audio_mask audio_mask = { 249 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 250 }; 251 252 #define vpg_regs_init(id)\ 253 VPG_DCN3_REG_LIST_RI(id) 254 255 static struct dcn30_vpg_registers vpg_regs[10]; 256 257 static const struct dcn30_vpg_shift vpg_shift = { 258 DCN3_VPG_MASK_SH_LIST(__SHIFT) 259 }; 260 261 static const struct dcn30_vpg_mask vpg_mask = { 262 DCN3_VPG_MASK_SH_LIST(_MASK) 263 }; 264 265 #define afmt_regs_init(id)\ 266 AFMT_DCN3_REG_LIST_RI(id) 267 268 static struct dcn30_afmt_registers afmt_regs[6]; 269 270 static const struct dcn30_afmt_shift afmt_shift = { 271 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dcn30_afmt_mask afmt_mask = { 275 DCN3_AFMT_MASK_SH_LIST(_MASK) 276 }; 277 278 #define apg_regs_init(id)\ 279 APG_DCN31_REG_LIST_RI(id) 280 281 static struct dcn31_apg_registers apg_regs[4]; 282 283 static const struct dcn31_apg_shift apg_shift = { 284 DCN31_APG_MASK_SH_LIST(__SHIFT) 285 }; 286 287 static const struct dcn31_apg_mask apg_mask = { 288 DCN31_APG_MASK_SH_LIST(_MASK) 289 }; 290 291 #define stream_enc_regs_init(id)\ 292 SE_DCN32_REG_LIST_RI(id) 293 294 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 295 296 static const struct dcn10_stream_encoder_shift se_shift = { 297 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 298 }; 299 300 static const struct dcn10_stream_encoder_mask se_mask = { 301 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 302 }; 303 304 305 #define aux_regs_init(id)\ 306 DCN2_AUX_REG_LIST_RI(id) 307 308 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 309 310 #define hpd_regs_init(id)\ 311 HPD_REG_LIST_RI(id) 312 313 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 314 315 #define link_regs_init(id, phyid)\ 316 ( \ 317 LE_DCN31_REG_LIST_RI(id), \ 318 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 319 ) 320 /*DPCS_DCN31_REG_LIST(id),*/ \ 321 322 static struct dcn10_link_enc_registers link_enc_regs[5]; 323 324 static const struct dcn10_link_enc_shift le_shift = { 325 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 326 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 327 }; 328 329 static const struct dcn10_link_enc_mask le_mask = { 330 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 331 // DPCS_DCN31_MASK_SH_LIST(_MASK) 332 }; 333 334 #define hpo_dp_stream_encoder_reg_init(id)\ 335 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 336 337 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 338 339 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 341 }; 342 343 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 344 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 345 }; 346 347 348 #define hpo_dp_link_encoder_reg_init(id)\ 349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 354 355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 356 357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 359 }; 360 361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 362 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 363 }; 364 365 #define dpp_regs_init(id)\ 366 DPP_REG_LIST_DCN30_COMMON_RI(id) 367 368 static struct dcn3_dpp_registers dpp_regs[4]; 369 370 static const struct dcn3_dpp_shift tf_shift = { 371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 372 }; 373 374 static const struct dcn3_dpp_mask tf_mask = { 375 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 376 }; 377 378 379 #define opp_regs_init(id)\ 380 OPP_REG_LIST_DCN30_RI(id) 381 382 static struct dcn20_opp_registers opp_regs[4]; 383 384 static const struct dcn20_opp_shift opp_shift = { 385 OPP_MASK_SH_LIST_DCN20(__SHIFT) 386 }; 387 388 static const struct dcn20_opp_mask opp_mask = { 389 OPP_MASK_SH_LIST_DCN20(_MASK) 390 }; 391 392 #define aux_engine_regs_init(id) \ 393 ( \ 394 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 395 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 396 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 398 ) 399 400 static struct dce110_aux_registers aux_engine_regs[5]; 401 402 static const struct dce110_aux_registers_shift aux_shift = { 403 DCN_AUX_MASK_SH_LIST(__SHIFT) 404 }; 405 406 static const struct dce110_aux_registers_mask aux_mask = { 407 DCN_AUX_MASK_SH_LIST(_MASK) 408 }; 409 410 #define dwbc_regs_dcn3_init(id)\ 411 DWBC_COMMON_REG_LIST_DCN30_RI(id) 412 413 static struct dcn30_dwbc_registers dwbc30_regs[1]; 414 415 static const struct dcn30_dwbc_shift dwbc30_shift = { 416 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 417 }; 418 419 static const struct dcn30_dwbc_mask dwbc30_mask = { 420 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 421 }; 422 423 #define mcif_wb_regs_dcn3_init(id)\ 424 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 425 426 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 427 428 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 429 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 430 }; 431 432 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 433 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 434 }; 435 436 #define dsc_regsDCN20_init(id)\ 437 DSC_REG_LIST_DCN20_RI(id) 438 439 static struct dcn20_dsc_registers dsc_regs[4]; 440 441 static const struct dcn20_dsc_shift dsc_shift = { 442 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 443 }; 444 445 static const struct dcn20_dsc_mask dsc_mask = { 446 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 447 }; 448 449 static struct dcn30_mpc_registers mpc_regs; 450 #define dcn_mpc_regs_init()\ 451 MPC_REG_LIST_DCN3_2_RI(0),\ 452 MPC_REG_LIST_DCN3_2_RI(1),\ 453 MPC_REG_LIST_DCN3_2_RI(2),\ 454 MPC_REG_LIST_DCN3_2_RI(3),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 459 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 460 461 static const struct dcn30_mpc_shift mpc_shift = { 462 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 463 }; 464 465 static const struct dcn30_mpc_mask mpc_mask = { 466 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 467 }; 468 469 #define optc_regs_init(id)\ 470 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 471 472 static struct dcn_optc_registers optc_regs[4]; 473 474 static const struct dcn_optc_shift optc_shift = { 475 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 476 }; 477 478 static const struct dcn_optc_mask optc_mask = { 479 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 480 }; 481 482 #define hubp_regs_init(id) \ 483 HUBP_REG_LIST_DCN32_RI(id) 484 485 static struct dcn_hubp2_registers hubp_regs[4]; 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn321 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 .enable_dp_dig_pixel_rate_div_policy = 1, 722 .allow_sw_cursor_fallback = false, 723 .alloc_extra_way_for_cursor = true, 724 }; 725 726 static const struct dc_debug_options debug_defaults_diags = { 727 .disable_dmcu = true, 728 .force_abm_enable = false, 729 .timing_trace = true, 730 .clock_trace = true, 731 .disable_dpp_power_gate = true, 732 .disable_hubp_power_gate = true, 733 .disable_dsc_power_gate = true, 734 .disable_clock_gate = true, 735 .disable_pplib_clock_request = true, 736 .disable_pplib_wm_range = true, 737 .disable_stutter = false, 738 .scl_reset_length10 = true, 739 .dwb_fi_phase = -1, // -1 = disable 740 .dmub_command_table = true, 741 .enable_tri_buf = true, 742 .use_max_lb = true, 743 .force_disable_subvp = true 744 }; 745 746 747 static struct dce_aux *dcn321_aux_engine_create( 748 struct dc_context *ctx, 749 uint32_t inst) 750 { 751 struct aux_engine_dce110 *aux_engine = 752 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 753 754 if (!aux_engine) 755 return NULL; 756 757 #undef REG_STRUCT 758 #define REG_STRUCT aux_engine_regs 759 aux_engine_regs_init(0), 760 aux_engine_regs_init(1), 761 aux_engine_regs_init(2), 762 aux_engine_regs_init(3), 763 aux_engine_regs_init(4); 764 765 dce110_aux_engine_construct(aux_engine, ctx, inst, 766 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 767 &aux_engine_regs[inst], 768 &aux_mask, 769 &aux_shift, 770 ctx->dc->caps.extended_aux_timeout_support); 771 772 return &aux_engine->base; 773 } 774 #define i2c_inst_regs_init(id)\ 775 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 776 777 static struct dce_i2c_registers i2c_hw_regs[5]; 778 779 static const struct dce_i2c_shift i2c_shifts = { 780 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 781 }; 782 783 static const struct dce_i2c_mask i2c_masks = { 784 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 785 }; 786 787 static struct dce_i2c_hw *dcn321_i2c_hw_create( 788 struct dc_context *ctx, 789 uint32_t inst) 790 { 791 struct dce_i2c_hw *dce_i2c_hw = 792 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 793 794 if (!dce_i2c_hw) 795 return NULL; 796 797 #undef REG_STRUCT 798 #define REG_STRUCT i2c_hw_regs 799 i2c_inst_regs_init(1), 800 i2c_inst_regs_init(2), 801 i2c_inst_regs_init(3), 802 i2c_inst_regs_init(4), 803 i2c_inst_regs_init(5); 804 805 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 806 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 807 808 return dce_i2c_hw; 809 } 810 811 static struct clock_source *dcn321_clock_source_create( 812 struct dc_context *ctx, 813 struct dc_bios *bios, 814 enum clock_source_id id, 815 const struct dce110_clk_src_regs *regs, 816 bool dp_clk_src) 817 { 818 struct dce110_clk_src *clk_src = 819 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 820 821 if (!clk_src) 822 return NULL; 823 824 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 825 regs, &cs_shift, &cs_mask)) { 826 clk_src->base.dp_clk_src = dp_clk_src; 827 return &clk_src->base; 828 } 829 830 BREAK_TO_DEBUGGER(); 831 return NULL; 832 } 833 834 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 835 { 836 int i; 837 838 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 839 GFP_KERNEL); 840 841 if (!hubbub2) 842 return NULL; 843 844 #undef REG_STRUCT 845 #define REG_STRUCT hubbub_reg 846 hubbub_reg_init(); 847 848 #undef REG_STRUCT 849 #define REG_STRUCT vmid_regs 850 vmid_regs_init(0), 851 vmid_regs_init(1), 852 vmid_regs_init(2), 853 vmid_regs_init(3), 854 vmid_regs_init(4), 855 vmid_regs_init(5), 856 vmid_regs_init(6), 857 vmid_regs_init(7), 858 vmid_regs_init(8), 859 vmid_regs_init(9), 860 vmid_regs_init(10), 861 vmid_regs_init(11), 862 vmid_regs_init(12), 863 vmid_regs_init(13), 864 vmid_regs_init(14), 865 vmid_regs_init(15); 866 867 hubbub32_construct(hubbub2, ctx, 868 &hubbub_reg, 869 &hubbub_shift, 870 &hubbub_mask, 871 ctx->dc->dml.ip.det_buffer_size_kbytes, 872 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 873 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 874 875 876 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 877 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 878 879 vmid->ctx = ctx; 880 881 vmid->regs = &vmid_regs[i]; 882 vmid->shifts = &vmid_shifts; 883 vmid->masks = &vmid_masks; 884 } 885 886 return &hubbub2->base; 887 } 888 889 static struct hubp *dcn321_hubp_create( 890 struct dc_context *ctx, 891 uint32_t inst) 892 { 893 struct dcn20_hubp *hubp2 = 894 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 895 896 if (!hubp2) 897 return NULL; 898 899 #undef REG_STRUCT 900 #define REG_STRUCT hubp_regs 901 hubp_regs_init(0), 902 hubp_regs_init(1), 903 hubp_regs_init(2), 904 hubp_regs_init(3); 905 906 if (hubp32_construct(hubp2, ctx, inst, 907 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 908 return &hubp2->base; 909 910 BREAK_TO_DEBUGGER(); 911 kfree(hubp2); 912 return NULL; 913 } 914 915 static void dcn321_dpp_destroy(struct dpp **dpp) 916 { 917 kfree(TO_DCN30_DPP(*dpp)); 918 *dpp = NULL; 919 } 920 921 static struct dpp *dcn321_dpp_create( 922 struct dc_context *ctx, 923 uint32_t inst) 924 { 925 struct dcn3_dpp *dpp3 = 926 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 927 928 if (!dpp3) 929 return NULL; 930 931 #undef REG_STRUCT 932 #define REG_STRUCT dpp_regs 933 dpp_regs_init(0), 934 dpp_regs_init(1), 935 dpp_regs_init(2), 936 dpp_regs_init(3); 937 938 if (dpp32_construct(dpp3, ctx, inst, 939 &dpp_regs[inst], &tf_shift, &tf_mask)) 940 return &dpp3->base; 941 942 BREAK_TO_DEBUGGER(); 943 kfree(dpp3); 944 return NULL; 945 } 946 947 static struct mpc *dcn321_mpc_create( 948 struct dc_context *ctx, 949 int num_mpcc, 950 int num_rmu) 951 { 952 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 953 GFP_KERNEL); 954 955 if (!mpc30) 956 return NULL; 957 958 #undef REG_STRUCT 959 #define REG_STRUCT mpc_regs 960 dcn_mpc_regs_init(); 961 962 dcn32_mpc_construct(mpc30, ctx, 963 &mpc_regs, 964 &mpc_shift, 965 &mpc_mask, 966 num_mpcc, 967 num_rmu); 968 969 return &mpc30->base; 970 } 971 972 static struct output_pixel_processor *dcn321_opp_create( 973 struct dc_context *ctx, uint32_t inst) 974 { 975 struct dcn20_opp *opp2 = 976 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 977 978 if (!opp2) { 979 BREAK_TO_DEBUGGER(); 980 return NULL; 981 } 982 983 #undef REG_STRUCT 984 #define REG_STRUCT opp_regs 985 opp_regs_init(0), 986 opp_regs_init(1), 987 opp_regs_init(2), 988 opp_regs_init(3); 989 990 dcn20_opp_construct(opp2, ctx, inst, 991 &opp_regs[inst], &opp_shift, &opp_mask); 992 return &opp2->base; 993 } 994 995 996 static struct timing_generator *dcn321_timing_generator_create( 997 struct dc_context *ctx, 998 uint32_t instance) 999 { 1000 struct optc *tgn10 = 1001 kzalloc(sizeof(struct optc), GFP_KERNEL); 1002 1003 if (!tgn10) 1004 return NULL; 1005 1006 #undef REG_STRUCT 1007 #define REG_STRUCT optc_regs 1008 optc_regs_init(0), 1009 optc_regs_init(1), 1010 optc_regs_init(2), 1011 optc_regs_init(3); 1012 1013 tgn10->base.inst = instance; 1014 tgn10->base.ctx = ctx; 1015 1016 tgn10->tg_regs = &optc_regs[instance]; 1017 tgn10->tg_shift = &optc_shift; 1018 tgn10->tg_mask = &optc_mask; 1019 1020 dcn32_timing_generator_init(tgn10); 1021 1022 return &tgn10->base; 1023 } 1024 1025 static const struct encoder_feature_support link_enc_feature = { 1026 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1027 .max_hdmi_pixel_clock = 600000, 1028 .hdmi_ycbcr420_supported = true, 1029 .dp_ycbcr420_supported = true, 1030 .fec_supported = true, 1031 .flags.bits.IS_HBR2_CAPABLE = true, 1032 .flags.bits.IS_HBR3_CAPABLE = true, 1033 .flags.bits.IS_TPS3_CAPABLE = true, 1034 .flags.bits.IS_TPS4_CAPABLE = true 1035 }; 1036 1037 static struct link_encoder *dcn321_link_encoder_create( 1038 struct dc_context *ctx, 1039 const struct encoder_init_data *enc_init_data) 1040 { 1041 struct dcn20_link_encoder *enc20 = 1042 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1043 1044 if (!enc20) 1045 return NULL; 1046 1047 #undef REG_STRUCT 1048 #define REG_STRUCT link_enc_aux_regs 1049 aux_regs_init(0), 1050 aux_regs_init(1), 1051 aux_regs_init(2), 1052 aux_regs_init(3), 1053 aux_regs_init(4); 1054 1055 #undef REG_STRUCT 1056 #define REG_STRUCT link_enc_hpd_regs 1057 hpd_regs_init(0), 1058 hpd_regs_init(1), 1059 hpd_regs_init(2), 1060 hpd_regs_init(3), 1061 hpd_regs_init(4); 1062 1063 #undef REG_STRUCT 1064 #define REG_STRUCT link_enc_regs 1065 link_regs_init(0, A), 1066 link_regs_init(1, B), 1067 link_regs_init(2, C), 1068 link_regs_init(3, D), 1069 link_regs_init(4, E); 1070 1071 dcn321_link_encoder_construct(enc20, 1072 enc_init_data, 1073 &link_enc_feature, 1074 &link_enc_regs[enc_init_data->transmitter], 1075 &link_enc_aux_regs[enc_init_data->channel - 1], 1076 &link_enc_hpd_regs[enc_init_data->hpd_source], 1077 &le_shift, 1078 &le_mask); 1079 1080 return &enc20->enc10.base; 1081 } 1082 1083 static void read_dce_straps( 1084 struct dc_context *ctx, 1085 struct resource_straps *straps) 1086 { 1087 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1088 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1089 1090 } 1091 1092 static struct audio *dcn321_create_audio( 1093 struct dc_context *ctx, unsigned int inst) 1094 { 1095 1096 #undef REG_STRUCT 1097 #define REG_STRUCT audio_regs 1098 audio_regs_init(0), 1099 audio_regs_init(1), 1100 audio_regs_init(2), 1101 audio_regs_init(3), 1102 audio_regs_init(4); 1103 1104 return dce_audio_create(ctx, inst, 1105 &audio_regs[inst], &audio_shift, &audio_mask); 1106 } 1107 1108 static struct vpg *dcn321_vpg_create( 1109 struct dc_context *ctx, 1110 uint32_t inst) 1111 { 1112 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1113 1114 if (!vpg3) 1115 return NULL; 1116 1117 #undef REG_STRUCT 1118 #define REG_STRUCT vpg_regs 1119 vpg_regs_init(0), 1120 vpg_regs_init(1), 1121 vpg_regs_init(2), 1122 vpg_regs_init(3), 1123 vpg_regs_init(4), 1124 vpg_regs_init(5), 1125 vpg_regs_init(6), 1126 vpg_regs_init(7), 1127 vpg_regs_init(8), 1128 vpg_regs_init(9); 1129 1130 vpg3_construct(vpg3, ctx, inst, 1131 &vpg_regs[inst], 1132 &vpg_shift, 1133 &vpg_mask); 1134 1135 return &vpg3->base; 1136 } 1137 1138 static struct afmt *dcn321_afmt_create( 1139 struct dc_context *ctx, 1140 uint32_t inst) 1141 { 1142 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1143 1144 if (!afmt3) 1145 return NULL; 1146 1147 #undef REG_STRUCT 1148 #define REG_STRUCT afmt_regs 1149 afmt_regs_init(0), 1150 afmt_regs_init(1), 1151 afmt_regs_init(2), 1152 afmt_regs_init(3), 1153 afmt_regs_init(4), 1154 afmt_regs_init(5); 1155 1156 afmt3_construct(afmt3, ctx, inst, 1157 &afmt_regs[inst], 1158 &afmt_shift, 1159 &afmt_mask); 1160 1161 return &afmt3->base; 1162 } 1163 1164 static struct apg *dcn321_apg_create( 1165 struct dc_context *ctx, 1166 uint32_t inst) 1167 { 1168 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1169 1170 if (!apg31) 1171 return NULL; 1172 1173 #undef REG_STRUCT 1174 #define REG_STRUCT apg_regs 1175 apg_regs_init(0), 1176 apg_regs_init(1), 1177 apg_regs_init(2), 1178 apg_regs_init(3); 1179 1180 apg31_construct(apg31, ctx, inst, 1181 &apg_regs[inst], 1182 &apg_shift, 1183 &apg_mask); 1184 1185 return &apg31->base; 1186 } 1187 1188 static struct stream_encoder *dcn321_stream_encoder_create( 1189 enum engine_id eng_id, 1190 struct dc_context *ctx) 1191 { 1192 struct dcn10_stream_encoder *enc1; 1193 struct vpg *vpg; 1194 struct afmt *afmt; 1195 int vpg_inst; 1196 int afmt_inst; 1197 1198 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1199 if (eng_id <= ENGINE_ID_DIGF) { 1200 vpg_inst = eng_id; 1201 afmt_inst = eng_id; 1202 } else 1203 return NULL; 1204 1205 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1206 vpg = dcn321_vpg_create(ctx, vpg_inst); 1207 afmt = dcn321_afmt_create(ctx, afmt_inst); 1208 1209 if (!enc1 || !vpg || !afmt) { 1210 kfree(enc1); 1211 kfree(vpg); 1212 kfree(afmt); 1213 return NULL; 1214 } 1215 1216 #undef REG_STRUCT 1217 #define REG_STRUCT stream_enc_regs 1218 stream_enc_regs_init(0), 1219 stream_enc_regs_init(1), 1220 stream_enc_regs_init(2), 1221 stream_enc_regs_init(3), 1222 stream_enc_regs_init(4); 1223 1224 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1225 eng_id, vpg, afmt, 1226 &stream_enc_regs[eng_id], 1227 &se_shift, &se_mask); 1228 1229 return &enc1->base; 1230 } 1231 1232 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1233 enum engine_id eng_id, 1234 struct dc_context *ctx) 1235 { 1236 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1237 struct vpg *vpg; 1238 struct apg *apg; 1239 uint32_t hpo_dp_inst; 1240 uint32_t vpg_inst; 1241 uint32_t apg_inst; 1242 1243 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1244 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1245 1246 /* Mapping of VPG register blocks to HPO DP block instance: 1247 * VPG[6] -> HPO_DP[0] 1248 * VPG[7] -> HPO_DP[1] 1249 * VPG[8] -> HPO_DP[2] 1250 * VPG[9] -> HPO_DP[3] 1251 */ 1252 vpg_inst = hpo_dp_inst + 6; 1253 1254 /* Mapping of APG register blocks to HPO DP block instance: 1255 * APG[0] -> HPO_DP[0] 1256 * APG[1] -> HPO_DP[1] 1257 * APG[2] -> HPO_DP[2] 1258 * APG[3] -> HPO_DP[3] 1259 */ 1260 apg_inst = hpo_dp_inst; 1261 1262 /* allocate HPO stream encoder and create VPG sub-block */ 1263 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1264 vpg = dcn321_vpg_create(ctx, vpg_inst); 1265 apg = dcn321_apg_create(ctx, apg_inst); 1266 1267 if (!hpo_dp_enc31 || !vpg || !apg) { 1268 kfree(hpo_dp_enc31); 1269 kfree(vpg); 1270 kfree(apg); 1271 return NULL; 1272 } 1273 1274 #undef REG_STRUCT 1275 #define REG_STRUCT hpo_dp_stream_enc_regs 1276 hpo_dp_stream_encoder_reg_init(0), 1277 hpo_dp_stream_encoder_reg_init(1), 1278 hpo_dp_stream_encoder_reg_init(2), 1279 hpo_dp_stream_encoder_reg_init(3); 1280 1281 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1282 hpo_dp_inst, eng_id, vpg, apg, 1283 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1284 &hpo_dp_se_shift, &hpo_dp_se_mask); 1285 1286 return &hpo_dp_enc31->base; 1287 } 1288 1289 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1290 uint8_t inst, 1291 struct dc_context *ctx) 1292 { 1293 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1294 1295 /* allocate HPO link encoder */ 1296 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1297 1298 #undef REG_STRUCT 1299 #define REG_STRUCT hpo_dp_link_enc_regs 1300 hpo_dp_link_encoder_reg_init(0), 1301 hpo_dp_link_encoder_reg_init(1); 1302 1303 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1304 &hpo_dp_link_enc_regs[inst], 1305 &hpo_dp_le_shift, &hpo_dp_le_mask); 1306 1307 return &hpo_dp_enc31->base; 1308 } 1309 1310 static struct dce_hwseq *dcn321_hwseq_create( 1311 struct dc_context *ctx) 1312 { 1313 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1314 1315 #undef REG_STRUCT 1316 #define REG_STRUCT hwseq_reg 1317 hwseq_reg_init(); 1318 1319 if (hws) { 1320 hws->ctx = ctx; 1321 hws->regs = &hwseq_reg; 1322 hws->shifts = &hwseq_shift; 1323 hws->masks = &hwseq_mask; 1324 } 1325 return hws; 1326 } 1327 static const struct resource_create_funcs res_create_funcs = { 1328 .read_dce_straps = read_dce_straps, 1329 .create_audio = dcn321_create_audio, 1330 .create_stream_encoder = dcn321_stream_encoder_create, 1331 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1332 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1333 .create_hwseq = dcn321_hwseq_create, 1334 }; 1335 1336 static const struct resource_create_funcs res_create_maximus_funcs = { 1337 .read_dce_straps = NULL, 1338 .create_audio = NULL, 1339 .create_stream_encoder = NULL, 1340 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1341 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1342 .create_hwseq = dcn321_hwseq_create, 1343 }; 1344 1345 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1346 { 1347 unsigned int i; 1348 1349 for (i = 0; i < pool->base.stream_enc_count; i++) { 1350 if (pool->base.stream_enc[i] != NULL) { 1351 if (pool->base.stream_enc[i]->vpg != NULL) { 1352 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1353 pool->base.stream_enc[i]->vpg = NULL; 1354 } 1355 if (pool->base.stream_enc[i]->afmt != NULL) { 1356 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1357 pool->base.stream_enc[i]->afmt = NULL; 1358 } 1359 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1360 pool->base.stream_enc[i] = NULL; 1361 } 1362 } 1363 1364 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1365 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1366 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1367 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1368 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1369 } 1370 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1371 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1372 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1373 } 1374 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1375 pool->base.hpo_dp_stream_enc[i] = NULL; 1376 } 1377 } 1378 1379 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1380 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1381 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1382 pool->base.hpo_dp_link_enc[i] = NULL; 1383 } 1384 } 1385 1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1387 if (pool->base.dscs[i] != NULL) 1388 dcn20_dsc_destroy(&pool->base.dscs[i]); 1389 } 1390 1391 if (pool->base.mpc != NULL) { 1392 kfree(TO_DCN20_MPC(pool->base.mpc)); 1393 pool->base.mpc = NULL; 1394 } 1395 if (pool->base.hubbub != NULL) { 1396 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1397 pool->base.hubbub = NULL; 1398 } 1399 for (i = 0; i < pool->base.pipe_count; i++) { 1400 if (pool->base.dpps[i] != NULL) 1401 dcn321_dpp_destroy(&pool->base.dpps[i]); 1402 1403 if (pool->base.ipps[i] != NULL) 1404 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1405 1406 if (pool->base.hubps[i] != NULL) { 1407 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1408 pool->base.hubps[i] = NULL; 1409 } 1410 1411 if (pool->base.irqs != NULL) 1412 dal_irq_service_destroy(&pool->base.irqs); 1413 } 1414 1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1416 if (pool->base.engines[i] != NULL) 1417 dce110_engine_destroy(&pool->base.engines[i]); 1418 if (pool->base.hw_i2cs[i] != NULL) { 1419 kfree(pool->base.hw_i2cs[i]); 1420 pool->base.hw_i2cs[i] = NULL; 1421 } 1422 if (pool->base.sw_i2cs[i] != NULL) { 1423 kfree(pool->base.sw_i2cs[i]); 1424 pool->base.sw_i2cs[i] = NULL; 1425 } 1426 } 1427 1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1429 if (pool->base.opps[i] != NULL) 1430 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1434 if (pool->base.timing_generators[i] != NULL) { 1435 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1436 pool->base.timing_generators[i] = NULL; 1437 } 1438 } 1439 1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1441 if (pool->base.dwbc[i] != NULL) { 1442 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1443 pool->base.dwbc[i] = NULL; 1444 } 1445 if (pool->base.mcif_wb[i] != NULL) { 1446 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1447 pool->base.mcif_wb[i] = NULL; 1448 } 1449 } 1450 1451 for (i = 0; i < pool->base.audio_count; i++) { 1452 if (pool->base.audios[i]) 1453 dce_aud_destroy(&pool->base.audios[i]); 1454 } 1455 1456 for (i = 0; i < pool->base.clk_src_count; i++) { 1457 if (pool->base.clock_sources[i] != NULL) { 1458 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1459 pool->base.clock_sources[i] = NULL; 1460 } 1461 } 1462 1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1464 if (pool->base.mpc_lut[i] != NULL) { 1465 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1466 pool->base.mpc_lut[i] = NULL; 1467 } 1468 if (pool->base.mpc_shaper[i] != NULL) { 1469 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1470 pool->base.mpc_shaper[i] = NULL; 1471 } 1472 } 1473 1474 if (pool->base.dp_clock_source != NULL) { 1475 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1476 pool->base.dp_clock_source = NULL; 1477 } 1478 1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1480 if (pool->base.multiple_abms[i] != NULL) 1481 dce_abm_destroy(&pool->base.multiple_abms[i]); 1482 } 1483 1484 if (pool->base.psr != NULL) 1485 dmub_psr_destroy(&pool->base.psr); 1486 1487 if (pool->base.dccg != NULL) 1488 dcn_dccg_destroy(&pool->base.dccg); 1489 1490 if (pool->base.oem_device != NULL) 1491 dal_ddc_service_destroy(&pool->base.oem_device); 1492 } 1493 1494 1495 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1496 { 1497 int i; 1498 uint32_t dwb_count = pool->res_cap->num_dwb; 1499 1500 for (i = 0; i < dwb_count; i++) { 1501 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1502 GFP_KERNEL); 1503 1504 if (!dwbc30) { 1505 dm_error("DC: failed to create dwbc30!\n"); 1506 return false; 1507 } 1508 1509 #undef REG_STRUCT 1510 #define REG_STRUCT dwbc30_regs 1511 dwbc_regs_dcn3_init(0); 1512 1513 dcn30_dwbc_construct(dwbc30, ctx, 1514 &dwbc30_regs[i], 1515 &dwbc30_shift, 1516 &dwbc30_mask, 1517 i); 1518 1519 pool->dwbc[i] = &dwbc30->base; 1520 } 1521 return true; 1522 } 1523 1524 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1525 { 1526 int i; 1527 uint32_t dwb_count = pool->res_cap->num_dwb; 1528 1529 for (i = 0; i < dwb_count; i++) { 1530 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1531 GFP_KERNEL); 1532 1533 if (!mcif_wb30) { 1534 dm_error("DC: failed to create mcif_wb30!\n"); 1535 return false; 1536 } 1537 1538 #undef REG_STRUCT 1539 #define REG_STRUCT mcif_wb30_regs 1540 mcif_wb_regs_dcn3_init(0); 1541 1542 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1543 &mcif_wb30_regs[i], 1544 &mcif_wb30_shift, 1545 &mcif_wb30_mask, 1546 i); 1547 1548 pool->mcif_wb[i] = &mcif_wb30->base; 1549 } 1550 return true; 1551 } 1552 1553 static struct display_stream_compressor *dcn321_dsc_create( 1554 struct dc_context *ctx, uint32_t inst) 1555 { 1556 struct dcn20_dsc *dsc = 1557 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1558 1559 if (!dsc) { 1560 BREAK_TO_DEBUGGER(); 1561 return NULL; 1562 } 1563 1564 #undef REG_STRUCT 1565 #define REG_STRUCT dsc_regs 1566 dsc_regsDCN20_init(0), 1567 dsc_regsDCN20_init(1), 1568 dsc_regsDCN20_init(2), 1569 dsc_regsDCN20_init(3); 1570 1571 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1572 1573 dsc->max_image_width = 6016; 1574 1575 return &dsc->base; 1576 } 1577 1578 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1579 { 1580 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1581 1582 dcn321_resource_destruct(dcn321_pool); 1583 kfree(dcn321_pool); 1584 *pool = NULL; 1585 } 1586 1587 static struct dc_cap_funcs cap_funcs = { 1588 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1589 }; 1590 1591 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1592 { 1593 DC_FP_START(); 1594 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1595 DC_FP_END(); 1596 } 1597 1598 static struct resource_funcs dcn321_res_pool_funcs = { 1599 .destroy = dcn321_destroy_resource_pool, 1600 .link_enc_create = dcn321_link_encoder_create, 1601 .link_enc_create_minimal = NULL, 1602 .panel_cntl_create = dcn32_panel_cntl_create, 1603 .validate_bandwidth = dcn32_validate_bandwidth, 1604 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1605 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1606 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1607 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1608 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1609 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1610 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1611 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1612 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1613 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1614 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1615 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1616 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1617 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1618 .add_phantom_pipes = dcn32_add_phantom_pipes, 1619 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1620 }; 1621 1622 1623 static bool dcn321_resource_construct( 1624 uint8_t num_virtual_links, 1625 struct dc *dc, 1626 struct dcn321_resource_pool *pool) 1627 { 1628 int i, j; 1629 struct dc_context *ctx = dc->ctx; 1630 struct irq_service_init_data init_data; 1631 struct ddc_service_init_data ddc_init_data = {0}; 1632 uint32_t pipe_fuses = 0; 1633 uint32_t num_pipes = 4; 1634 1635 #undef REG_STRUCT 1636 #define REG_STRUCT bios_regs 1637 bios_regs_init(); 1638 1639 #undef REG_STRUCT 1640 #define REG_STRUCT clk_src_regs 1641 clk_src_regs_init(0, A), 1642 clk_src_regs_init(1, B), 1643 clk_src_regs_init(2, C), 1644 clk_src_regs_init(3, D), 1645 clk_src_regs_init(4, E); 1646 1647 #undef REG_STRUCT 1648 #define REG_STRUCT abm_regs 1649 abm_regs_init(0), 1650 abm_regs_init(1), 1651 abm_regs_init(2), 1652 abm_regs_init(3); 1653 1654 #undef REG_STRUCT 1655 #define REG_STRUCT dccg_regs 1656 dccg_regs_init(); 1657 1658 1659 ctx->dc_bios->regs = &bios_regs; 1660 1661 pool->base.res_cap = &res_cap_dcn321; 1662 /* max number of pipes for ASIC before checking for pipe fuses */ 1663 num_pipes = pool->base.res_cap->num_timing_generator; 1664 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1665 1666 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1667 if (pipe_fuses & 1 << i) 1668 num_pipes--; 1669 1670 if (pipe_fuses & 1) 1671 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1672 1673 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1674 ASSERT(0); //Entire DCN is harvested! 1675 1676 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1677 * value will be changed, update max_num_dpp and max_num_otg for dml. 1678 */ 1679 dcn3_21_ip.max_num_dpp = num_pipes; 1680 dcn3_21_ip.max_num_otg = num_pipes; 1681 1682 pool->base.funcs = &dcn321_res_pool_funcs; 1683 1684 /************************************************* 1685 * Resource + asic cap harcoding * 1686 *************************************************/ 1687 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1688 pool->base.timing_generator_count = num_pipes; 1689 pool->base.pipe_count = num_pipes; 1690 pool->base.mpcc_count = num_pipes; 1691 dc->caps.max_downscale_ratio = 600; 1692 dc->caps.i2c_speed_in_khz = 100; 1693 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1694 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1695 dc->caps.max_cursor_size = 64; 1696 dc->caps.min_horizontal_blanking_period = 80; 1697 dc->caps.dmdata_alloc_size = 2048; 1698 dc->caps.mall_size_per_mem_channel = 0; 1699 dc->caps.mall_size_total = 0; 1700 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1701 dc->caps.cache_line_size = 64; 1702 dc->caps.cache_num_ways = 16; 1703 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 1704 dc->caps.subvp_fw_processing_delay_us = 15; 1705 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1706 dc->caps.subvp_swath_height_margin_lines = 16; 1707 dc->caps.subvp_pstate_allow_width_us = 20; 1708 dc->caps.subvp_vertical_int_margin_us = 30; 1709 dc->caps.max_slave_planes = 1; 1710 dc->caps.max_slave_yuv_planes = 1; 1711 dc->caps.max_slave_rgb_planes = 1; 1712 dc->caps.post_blend_color_processing = true; 1713 dc->caps.force_dp_tps4_for_cp2520 = true; 1714 dc->caps.dp_hpo = true; 1715 dc->caps.dp_hdmi21_pcon_support = true; 1716 dc->caps.edp_dsc_support = true; 1717 dc->caps.extended_aux_timeout_support = true; 1718 dc->caps.dmcub_support = true; 1719 1720 /* Color pipeline capabilities */ 1721 dc->caps.color.dpp.dcn_arch = 1; 1722 dc->caps.color.dpp.input_lut_shared = 0; 1723 dc->caps.color.dpp.icsc = 1; 1724 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1725 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1726 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1727 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1728 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1729 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1730 dc->caps.color.dpp.post_csc = 1; 1731 dc->caps.color.dpp.gamma_corr = 1; 1732 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1733 1734 dc->caps.color.dpp.hw_3d_lut = 1; 1735 dc->caps.color.dpp.ogam_ram = 1; 1736 // no OGAM ROM on DCN2 and later ASICs 1737 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1738 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1739 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1740 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1741 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1742 dc->caps.color.dpp.ocsc = 0; 1743 1744 dc->caps.color.mpc.gamut_remap = 1; 1745 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1746 dc->caps.color.mpc.ogam_ram = 1; 1747 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1748 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1749 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1750 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1751 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1752 dc->caps.color.mpc.ocsc = 1; 1753 1754 /* read VBIOS LTTPR caps */ 1755 { 1756 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1757 enum bp_result bp_query_result; 1758 uint8_t is_vbios_lttpr_enable = 0; 1759 1760 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1761 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1762 } 1763 1764 /* interop bit is implicit */ 1765 { 1766 dc->caps.vbios_lttpr_aware = true; 1767 } 1768 } 1769 1770 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1771 dc->debug = debug_defaults_drv; 1772 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1773 dc->debug = debug_defaults_diags; 1774 } else 1775 dc->debug = debug_defaults_diags; 1776 // Init the vm_helper 1777 if (dc->vm_helper) 1778 vm_helper_init(dc->vm_helper, 16); 1779 1780 /************************************************* 1781 * Create resources * 1782 *************************************************/ 1783 1784 /* Clock Sources for Pixel Clock*/ 1785 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1786 dcn321_clock_source_create(ctx, ctx->dc_bios, 1787 CLOCK_SOURCE_COMBO_PHY_PLL0, 1788 &clk_src_regs[0], false); 1789 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1790 dcn321_clock_source_create(ctx, ctx->dc_bios, 1791 CLOCK_SOURCE_COMBO_PHY_PLL1, 1792 &clk_src_regs[1], false); 1793 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1794 dcn321_clock_source_create(ctx, ctx->dc_bios, 1795 CLOCK_SOURCE_COMBO_PHY_PLL2, 1796 &clk_src_regs[2], false); 1797 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1798 dcn321_clock_source_create(ctx, ctx->dc_bios, 1799 CLOCK_SOURCE_COMBO_PHY_PLL3, 1800 &clk_src_regs[3], false); 1801 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1802 dcn321_clock_source_create(ctx, ctx->dc_bios, 1803 CLOCK_SOURCE_COMBO_PHY_PLL4, 1804 &clk_src_regs[4], false); 1805 1806 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1807 1808 /* todo: not reuse phy_pll registers */ 1809 pool->base.dp_clock_source = 1810 dcn321_clock_source_create(ctx, ctx->dc_bios, 1811 CLOCK_SOURCE_ID_DP_DTO, 1812 &clk_src_regs[0], true); 1813 1814 for (i = 0; i < pool->base.clk_src_count; i++) { 1815 if (pool->base.clock_sources[i] == NULL) { 1816 dm_error("DC: failed to create clock sources!\n"); 1817 BREAK_TO_DEBUGGER(); 1818 goto create_fail; 1819 } 1820 } 1821 1822 /* DCCG */ 1823 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1824 if (pool->base.dccg == NULL) { 1825 dm_error("DC: failed to create dccg!\n"); 1826 BREAK_TO_DEBUGGER(); 1827 goto create_fail; 1828 } 1829 1830 /* DML */ 1831 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1832 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1833 1834 /* IRQ Service */ 1835 init_data.ctx = dc->ctx; 1836 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1837 if (!pool->base.irqs) 1838 goto create_fail; 1839 1840 /* HUBBUB */ 1841 pool->base.hubbub = dcn321_hubbub_create(ctx); 1842 if (pool->base.hubbub == NULL) { 1843 BREAK_TO_DEBUGGER(); 1844 dm_error("DC: failed to create hubbub!\n"); 1845 goto create_fail; 1846 } 1847 1848 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1849 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1850 1851 /* if pipe is disabled, skip instance of HW pipe, 1852 * i.e, skip ASIC register instance 1853 */ 1854 if (pipe_fuses & 1 << i) 1855 continue; 1856 1857 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1858 if (pool->base.hubps[j] == NULL) { 1859 BREAK_TO_DEBUGGER(); 1860 dm_error( 1861 "DC: failed to create hubps!\n"); 1862 goto create_fail; 1863 } 1864 1865 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1866 if (pool->base.dpps[j] == NULL) { 1867 BREAK_TO_DEBUGGER(); 1868 dm_error( 1869 "DC: failed to create dpps!\n"); 1870 goto create_fail; 1871 } 1872 1873 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1874 if (pool->base.opps[j] == NULL) { 1875 BREAK_TO_DEBUGGER(); 1876 dm_error( 1877 "DC: failed to create output pixel processor!\n"); 1878 goto create_fail; 1879 } 1880 1881 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1882 ctx, i); 1883 if (pool->base.timing_generators[j] == NULL) { 1884 BREAK_TO_DEBUGGER(); 1885 dm_error("DC: failed to create tg!\n"); 1886 goto create_fail; 1887 } 1888 1889 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1890 &abm_regs[i], 1891 &abm_shift, 1892 &abm_mask); 1893 if (pool->base.multiple_abms[j] == NULL) { 1894 dm_error("DC: failed to create abm for pipe %d!\n", i); 1895 BREAK_TO_DEBUGGER(); 1896 goto create_fail; 1897 } 1898 1899 /* index for resource pool arrays for next valid pipe */ 1900 j++; 1901 } 1902 1903 /* PSR */ 1904 pool->base.psr = dmub_psr_create(ctx); 1905 if (pool->base.psr == NULL) { 1906 dm_error("DC: failed to create psr obj!\n"); 1907 BREAK_TO_DEBUGGER(); 1908 goto create_fail; 1909 } 1910 1911 /* MPCCs */ 1912 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1913 if (pool->base.mpc == NULL) { 1914 BREAK_TO_DEBUGGER(); 1915 dm_error("DC: failed to create mpc!\n"); 1916 goto create_fail; 1917 } 1918 1919 /* DSCs */ 1920 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1921 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1922 if (pool->base.dscs[i] == NULL) { 1923 BREAK_TO_DEBUGGER(); 1924 dm_error("DC: failed to create display stream compressor %d!\n", i); 1925 goto create_fail; 1926 } 1927 } 1928 1929 /* DWB */ 1930 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1931 BREAK_TO_DEBUGGER(); 1932 dm_error("DC: failed to create dwbc!\n"); 1933 goto create_fail; 1934 } 1935 1936 /* MMHUBBUB */ 1937 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1938 BREAK_TO_DEBUGGER(); 1939 dm_error("DC: failed to create mcif_wb!\n"); 1940 goto create_fail; 1941 } 1942 1943 /* AUX and I2C */ 1944 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1945 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1946 if (pool->base.engines[i] == NULL) { 1947 BREAK_TO_DEBUGGER(); 1948 dm_error( 1949 "DC:failed to create aux engine!!\n"); 1950 goto create_fail; 1951 } 1952 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1953 if (pool->base.hw_i2cs[i] == NULL) { 1954 BREAK_TO_DEBUGGER(); 1955 dm_error( 1956 "DC:failed to create hw i2c!!\n"); 1957 goto create_fail; 1958 } 1959 pool->base.sw_i2cs[i] = NULL; 1960 } 1961 1962 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1963 if (!resource_construct(num_virtual_links, dc, &pool->base, 1964 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1965 &res_create_funcs : &res_create_maximus_funcs))) 1966 goto create_fail; 1967 1968 /* HW Sequencer init functions and Plane caps */ 1969 dcn32_hw_sequencer_init_functions(dc); 1970 1971 dc->caps.max_planes = pool->base.pipe_count; 1972 1973 for (i = 0; i < dc->caps.max_planes; ++i) 1974 dc->caps.planes[i] = plane_cap; 1975 1976 dc->cap_funcs = cap_funcs; 1977 1978 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1979 ddc_init_data.ctx = dc->ctx; 1980 ddc_init_data.link = NULL; 1981 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1982 ddc_init_data.id.enum_id = 0; 1983 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1984 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 1985 } else { 1986 pool->base.oem_device = NULL; 1987 } 1988 1989 return true; 1990 1991 create_fail: 1992 1993 dcn321_resource_destruct(pool); 1994 1995 return false; 1996 } 1997 1998 struct resource_pool *dcn321_create_resource_pool( 1999 const struct dc_init_data *init_data, 2000 struct dc *dc) 2001 { 2002 struct dcn321_resource_pool *pool = 2003 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2004 2005 if (!pool) 2006 return NULL; 2007 2008 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2009 return &pool->base; 2010 2011 BREAK_TO_DEBUGGER(); 2012 kfree(pool); 2013 return NULL; 2014 } 2015