1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dc_link_dp.h" 64 #include "dcn31/dcn31_apg.h" 65 #include "dcn31/dcn31_dio_link_encoder.h" 66 #include "dcn32/dcn32_dio_link_encoder.h" 67 #include "dcn321_dio_link_encoder.h" 68 #include "dce/dce_clock_source.h" 69 #include "dce/dce_audio.h" 70 #include "dce/dce_hwseq.h" 71 #include "clk_mgr.h" 72 #include "virtual/virtual_stream_encoder.h" 73 #include "dml/display_mode_vba.h" 74 #include "dcn32/dcn32_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dc_link_ddc.h" 77 #include "dcn31/dcn31_panel_cntl.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn32/dcn32_mmhubbub.h" 81 82 #include "dcn/dcn_3_2_1_offset.h" 83 #include "dcn/dcn_3_2_1_sh_mask.h" 84 #include "nbio/nbio_4_3_0_offset.h" 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #define DCN_BASE__INST0_SEG1 0x000000C0 97 #define DCN_BASE__INST0_SEG2 0x000034C0 98 #define DCN_BASE__INST0_SEG3 0x00009000 99 #define NBIO_BASE__INST0_SEG1 0x00000014 100 101 #define MAX_INSTANCE 8 102 #define MAX_SEGMENT 6 103 104 struct IP_BASE_INSTANCE { 105 unsigned int segment[MAX_SEGMENT]; 106 }; 107 108 struct IP_BASE { 109 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 110 }; 111 112 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } } } }; 120 121 #define DC_LOGGER_INIT(logger) 122 #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) 123 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 124 125 enum dcn321_clk_src_array_id { 126 DCN321_CLK_SRC_PLL0, 127 DCN321_CLK_SRC_PLL1, 128 DCN321_CLK_SRC_PLL2, 129 DCN321_CLK_SRC_PLL3, 130 DCN321_CLK_SRC_PLL4, 131 DCN321_CLK_SRC_TOTAL 132 }; 133 134 /* begin ********************* 135 * macros to expend register list macro defined in HW object header file 136 */ 137 138 /* DCN */ 139 /* TODO awful hack. fixup dcn20_dwb.h */ 140 #undef BASE_INNER 141 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 142 143 #define BASE(seg) BASE_INNER(seg) 144 145 #define SR(reg_name)\ 146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 147 reg ## reg_name 148 149 #define SRI(reg_name, block, id)\ 150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 151 reg ## block ## id ## _ ## reg_name 152 153 #define SRI2(reg_name, block, id)\ 154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 155 reg ## reg_name 156 157 #define SRIR(var_name, reg_name, block, id)\ 158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161 #define SRII(reg_name, block, id)\ 162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165 #define SRII_MPC_RMU(reg_name, block, id)\ 166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169 #define SRII_DWB(reg_name, temp_name, block, id)\ 170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## temp_name 172 173 #define DCCG_SRII(reg_name, block, id)\ 174 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) \ 183 NBIO_BASE__INST0_SEG ## seg 184 185 #define NBIO_BASE(seg) \ 186 NBIO_BASE_INNER(seg) 187 188 #define NBIO_SR(reg_name)\ 189 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 190 regBIF_BX0_ ## reg_name 191 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static const struct bios_registers bios_regs = { 197 NBIO_SR(BIOS_SCRATCH_3), 198 NBIO_SR(BIOS_SCRATCH_6) 199 }; 200 201 #define clk_src_regs(index, pllid)\ 202 [index] = {\ 203 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 204 } 205 206 static const struct dce110_clk_src_regs clk_src_regs[] = { 207 clk_src_regs(0, A), 208 clk_src_regs(1, B), 209 clk_src_regs(2, C), 210 clk_src_regs(3, D), 211 clk_src_regs(4, E) 212 }; 213 214 static const struct dce110_clk_src_shift cs_shift = { 215 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 216 }; 217 218 static const struct dce110_clk_src_mask cs_mask = { 219 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 220 }; 221 222 #define abm_regs(id)\ 223 [id] = {\ 224 ABM_DCN32_REG_LIST(id)\ 225 } 226 227 static const struct dce_abm_registers abm_regs[] = { 228 abm_regs(0), 229 abm_regs(1), 230 abm_regs(2), 231 abm_regs(3), 232 }; 233 234 static const struct dce_abm_shift abm_shift = { 235 ABM_MASK_SH_LIST_DCN32(__SHIFT) 236 }; 237 238 static const struct dce_abm_mask abm_mask = { 239 ABM_MASK_SH_LIST_DCN32(_MASK) 240 }; 241 242 #define audio_regs(id)\ 243 [id] = {\ 244 AUD_COMMON_REG_LIST(id)\ 245 } 246 247 static const struct dce_audio_registers audio_regs[] = { 248 audio_regs(0), 249 audio_regs(1), 250 audio_regs(2), 251 audio_regs(3), 252 audio_regs(4) 253 }; 254 255 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 257 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 258 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 259 260 static const struct dce_audio_shift audio_shift = { 261 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 262 }; 263 264 static const struct dce_audio_mask audio_mask = { 265 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 266 }; 267 268 #define vpg_regs(id)\ 269 [id] = {\ 270 VPG_DCN3_REG_LIST(id)\ 271 } 272 273 static const struct dcn30_vpg_registers vpg_regs[] = { 274 vpg_regs(0), 275 vpg_regs(1), 276 vpg_regs(2), 277 vpg_regs(3), 278 vpg_regs(4), 279 vpg_regs(5), 280 vpg_regs(6), 281 vpg_regs(7), 282 vpg_regs(8), 283 vpg_regs(9), 284 }; 285 286 static const struct dcn30_vpg_shift vpg_shift = { 287 DCN3_VPG_MASK_SH_LIST(__SHIFT) 288 }; 289 290 static const struct dcn30_vpg_mask vpg_mask = { 291 DCN3_VPG_MASK_SH_LIST(_MASK) 292 }; 293 294 #define afmt_regs(id)\ 295 [id] = {\ 296 AFMT_DCN3_REG_LIST(id)\ 297 } 298 299 static const struct dcn30_afmt_registers afmt_regs[] = { 300 afmt_regs(0), 301 afmt_regs(1), 302 afmt_regs(2), 303 afmt_regs(3), 304 afmt_regs(4), 305 afmt_regs(5) 306 }; 307 308 static const struct dcn30_afmt_shift afmt_shift = { 309 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 310 }; 311 312 static const struct dcn30_afmt_mask afmt_mask = { 313 DCN3_AFMT_MASK_SH_LIST(_MASK) 314 }; 315 316 #define apg_regs(id)\ 317 [id] = {\ 318 APG_DCN31_REG_LIST(id)\ 319 } 320 321 static const struct dcn31_apg_registers apg_regs[] = { 322 apg_regs(0), 323 apg_regs(1), 324 apg_regs(2), 325 apg_regs(3) 326 }; 327 328 static const struct dcn31_apg_shift apg_shift = { 329 DCN31_APG_MASK_SH_LIST(__SHIFT) 330 }; 331 332 static const struct dcn31_apg_mask apg_mask = { 333 DCN31_APG_MASK_SH_LIST(_MASK) 334 }; 335 336 #define stream_enc_regs(id)\ 337 [id] = {\ 338 SE_DCN32_REG_LIST(id)\ 339 } 340 341 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 342 stream_enc_regs(0), 343 stream_enc_regs(1), 344 stream_enc_regs(2), 345 stream_enc_regs(3), 346 stream_enc_regs(4) 347 }; 348 349 static const struct dcn10_stream_encoder_shift se_shift = { 350 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 351 }; 352 353 static const struct dcn10_stream_encoder_mask se_mask = { 354 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 355 }; 356 357 358 #define aux_regs(id)\ 359 [id] = {\ 360 DCN2_AUX_REG_LIST(id)\ 361 } 362 363 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 364 aux_regs(0), 365 aux_regs(1), 366 aux_regs(2), 367 aux_regs(3), 368 aux_regs(4) 369 }; 370 371 #define hpd_regs(id)\ 372 [id] = {\ 373 HPD_REG_LIST(id)\ 374 } 375 376 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 377 hpd_regs(0), 378 hpd_regs(1), 379 hpd_regs(2), 380 hpd_regs(3), 381 hpd_regs(4) 382 }; 383 384 #define link_regs(id, phyid)\ 385 [id] = {\ 386 LE_DCN31_REG_LIST(id), \ 387 UNIPHY_DCN2_REG_LIST(phyid), \ 388 /*DPCS_DCN31_REG_LIST(id),*/ \ 389 } 390 391 static const struct dcn10_link_enc_registers link_enc_regs[] = { 392 link_regs(0, A), 393 link_regs(1, B), 394 link_regs(2, C), 395 link_regs(3, D), 396 link_regs(4, E) 397 }; 398 399 static const struct dcn10_link_enc_shift le_shift = { 400 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 401 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dcn10_link_enc_mask le_mask = { 405 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 406 // DPCS_DCN31_MASK_SH_LIST(_MASK) 407 }; 408 409 #define hpo_dp_stream_encoder_reg_list(id)\ 410 [id] = {\ 411 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 412 } 413 414 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 415 hpo_dp_stream_encoder_reg_list(0), 416 hpo_dp_stream_encoder_reg_list(1), 417 hpo_dp_stream_encoder_reg_list(2), 418 hpo_dp_stream_encoder_reg_list(3), 419 }; 420 421 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 422 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 423 }; 424 425 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 426 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 427 }; 428 429 430 #define hpo_dp_link_encoder_reg_list(id)\ 431 [id] = {\ 432 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 433 /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ 434 /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ 435 /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ 436 /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ 437 /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ 438 } 439 440 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 441 hpo_dp_link_encoder_reg_list(0), 442 hpo_dp_link_encoder_reg_list(1), 443 }; 444 445 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 446 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 450 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 451 }; 452 453 #define dpp_regs(id)\ 454 [id] = {\ 455 DPP_REG_LIST_DCN30_COMMON(id),\ 456 } 457 458 static const struct dcn3_dpp_registers dpp_regs[] = { 459 dpp_regs(0), 460 dpp_regs(1), 461 dpp_regs(2), 462 dpp_regs(3) 463 }; 464 465 static const struct dcn3_dpp_shift tf_shift = { 466 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 467 }; 468 469 static const struct dcn3_dpp_mask tf_mask = { 470 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 471 }; 472 473 474 #define opp_regs(id)\ 475 [id] = {\ 476 OPP_REG_LIST_DCN30(id),\ 477 } 478 479 static const struct dcn20_opp_registers opp_regs[] = { 480 opp_regs(0), 481 opp_regs(1), 482 opp_regs(2), 483 opp_regs(3) 484 }; 485 486 static const struct dcn20_opp_shift opp_shift = { 487 OPP_MASK_SH_LIST_DCN20(__SHIFT) 488 }; 489 490 static const struct dcn20_opp_mask opp_mask = { 491 OPP_MASK_SH_LIST_DCN20(_MASK) 492 }; 493 494 #define aux_engine_regs(id)\ 495 [id] = {\ 496 AUX_COMMON_REG_LIST0(id), \ 497 .AUXN_IMPCAL = 0, \ 498 .AUXP_IMPCAL = 0, \ 499 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 500 } 501 502 static const struct dce110_aux_registers aux_engine_regs[] = { 503 aux_engine_regs(0), 504 aux_engine_regs(1), 505 aux_engine_regs(2), 506 aux_engine_regs(3), 507 aux_engine_regs(4) 508 }; 509 510 static const struct dce110_aux_registers_shift aux_shift = { 511 DCN_AUX_MASK_SH_LIST(__SHIFT) 512 }; 513 514 static const struct dce110_aux_registers_mask aux_mask = { 515 DCN_AUX_MASK_SH_LIST(_MASK) 516 }; 517 518 519 #define dwbc_regs_dcn3(id)\ 520 [id] = {\ 521 DWBC_COMMON_REG_LIST_DCN30(id),\ 522 } 523 524 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 525 dwbc_regs_dcn3(0), 526 }; 527 528 static const struct dcn30_dwbc_shift dwbc30_shift = { 529 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 530 }; 531 532 static const struct dcn30_dwbc_mask dwbc30_mask = { 533 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 534 }; 535 536 #define mcif_wb_regs_dcn3(id)\ 537 [id] = {\ 538 MCIF_WB_COMMON_REG_LIST_DCN32(id),\ 539 } 540 541 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 542 mcif_wb_regs_dcn3(0) 543 }; 544 545 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 546 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 547 }; 548 549 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 550 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 551 }; 552 553 #define dsc_regsDCN20(id)\ 554 [id] = {\ 555 DSC_REG_LIST_DCN20(id)\ 556 } 557 558 static const struct dcn20_dsc_registers dsc_regs[] = { 559 dsc_regsDCN20(0), 560 dsc_regsDCN20(1), 561 dsc_regsDCN20(2), 562 dsc_regsDCN20(3) 563 }; 564 565 static const struct dcn20_dsc_shift dsc_shift = { 566 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 567 }; 568 569 static const struct dcn20_dsc_mask dsc_mask = { 570 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 571 }; 572 573 static const struct dcn30_mpc_registers mpc_regs = { 574 MPC_REG_LIST_DCN3_2(0), 575 MPC_REG_LIST_DCN3_2(1), 576 MPC_REG_LIST_DCN3_2(2), 577 MPC_REG_LIST_DCN3_2(3), 578 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 579 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 580 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 581 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 582 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 583 }; 584 585 static const struct dcn30_mpc_shift mpc_shift = { 586 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 587 }; 588 589 static const struct dcn30_mpc_mask mpc_mask = { 590 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 591 }; 592 593 #define optc_regs(id)\ 594 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} 595 596 static const struct dcn_optc_registers optc_regs[] = { 597 optc_regs(0), 598 optc_regs(1), 599 optc_regs(2), 600 optc_regs(3) 601 }; 602 603 static const struct dcn_optc_shift optc_shift = { 604 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 605 }; 606 607 static const struct dcn_optc_mask optc_mask = { 608 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 609 }; 610 611 #define hubp_regs(id)\ 612 [id] = {\ 613 HUBP_REG_LIST_DCN32(id)\ 614 } 615 616 static const struct dcn_hubp2_registers hubp_regs[] = { 617 hubp_regs(0), 618 hubp_regs(1), 619 hubp_regs(2), 620 hubp_regs(3) 621 }; 622 623 624 static const struct dcn_hubp2_shift hubp_shift = { 625 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 626 }; 627 628 static const struct dcn_hubp2_mask hubp_mask = { 629 HUBP_MASK_SH_LIST_DCN32(_MASK) 630 }; 631 static const struct dcn_hubbub_registers hubbub_reg = { 632 HUBBUB_REG_LIST_DCN32(0) 633 }; 634 635 static const struct dcn_hubbub_shift hubbub_shift = { 636 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 637 }; 638 639 static const struct dcn_hubbub_mask hubbub_mask = { 640 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 641 }; 642 643 static const struct dccg_registers dccg_regs = { 644 DCCG_REG_LIST_DCN32() 645 }; 646 647 static const struct dccg_shift dccg_shift = { 648 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 649 }; 650 651 static const struct dccg_mask dccg_mask = { 652 DCCG_MASK_SH_LIST_DCN32(_MASK) 653 }; 654 655 656 #define SRII2(reg_name_pre, reg_name_post, id)\ 657 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 658 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 659 reg ## reg_name_pre ## id ## _ ## reg_name_post 660 661 662 #define HWSEQ_DCN32_REG_LIST()\ 663 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 664 SR(DIO_MEM_PWR_CTRL), \ 665 SR(ODM_MEM_PWR_CTRL3), \ 666 SR(MMHUBBUB_MEM_PWR_CNTL), \ 667 SR(DCCG_GATE_DISABLE_CNTL), \ 668 SR(DCCG_GATE_DISABLE_CNTL2), \ 669 SR(DCFCLK_CNTL),\ 670 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 671 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 672 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 673 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 674 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 675 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 676 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 677 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 678 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 679 SR(MICROSECOND_TIME_BASE_DIV), \ 680 SR(MILLISECOND_TIME_BASE_DIV), \ 681 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 682 SR(RBBMIF_TIMEOUT_DIS), \ 683 SR(RBBMIF_TIMEOUT_DIS_2), \ 684 SR(DCHUBBUB_CRC_CTRL), \ 685 SR(DPP_TOP0_DPP_CRC_CTRL), \ 686 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 687 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 688 SR(MPC_CRC_CTRL), \ 689 SR(MPC_CRC_RESULT_GB), \ 690 SR(MPC_CRC_RESULT_C), \ 691 SR(MPC_CRC_RESULT_AR), \ 692 SR(DOMAIN0_PG_CONFIG), \ 693 SR(DOMAIN1_PG_CONFIG), \ 694 SR(DOMAIN2_PG_CONFIG), \ 695 SR(DOMAIN3_PG_CONFIG), \ 696 SR(DOMAIN16_PG_CONFIG), \ 697 SR(DOMAIN17_PG_CONFIG), \ 698 SR(DOMAIN18_PG_CONFIG), \ 699 SR(DOMAIN19_PG_CONFIG), \ 700 SR(DOMAIN0_PG_STATUS), \ 701 SR(DOMAIN1_PG_STATUS), \ 702 SR(DOMAIN2_PG_STATUS), \ 703 SR(DOMAIN3_PG_STATUS), \ 704 SR(DOMAIN16_PG_STATUS), \ 705 SR(DOMAIN17_PG_STATUS), \ 706 SR(DOMAIN18_PG_STATUS), \ 707 SR(DOMAIN19_PG_STATUS), \ 708 SR(D1VGA_CONTROL), \ 709 SR(D2VGA_CONTROL), \ 710 SR(D3VGA_CONTROL), \ 711 SR(D4VGA_CONTROL), \ 712 SR(D5VGA_CONTROL), \ 713 SR(D6VGA_CONTROL), \ 714 SR(DC_IP_REQUEST_CNTL), \ 715 SR(AZALIA_AUDIO_DTO), \ 716 SR(AZALIA_CONTROLLER_CLOCK_GATING) 717 718 static const struct dce_hwseq_registers hwseq_reg = { 719 HWSEQ_DCN32_REG_LIST() 720 }; 721 722 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 723 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 724 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 725 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 726 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 727 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 728 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 729 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 730 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 731 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 732 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 733 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 734 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 735 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 736 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 737 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 738 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 739 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 740 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 741 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 742 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 745 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 746 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 747 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 748 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 749 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 750 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 751 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 752 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 753 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 754 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 755 756 static const struct dce_hwseq_shift hwseq_shift = { 757 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 758 }; 759 760 static const struct dce_hwseq_mask hwseq_mask = { 761 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 762 }; 763 #define vmid_regs(id)\ 764 [id] = {\ 765 DCN20_VMID_REG_LIST(id)\ 766 } 767 768 static const struct dcn_vmid_registers vmid_regs[] = { 769 vmid_regs(0), 770 vmid_regs(1), 771 vmid_regs(2), 772 vmid_regs(3), 773 vmid_regs(4), 774 vmid_regs(5), 775 vmid_regs(6), 776 vmid_regs(7), 777 vmid_regs(8), 778 vmid_regs(9), 779 vmid_regs(10), 780 vmid_regs(11), 781 vmid_regs(12), 782 vmid_regs(13), 783 vmid_regs(14), 784 vmid_regs(15) 785 }; 786 787 static const struct dcn20_vmid_shift vmid_shifts = { 788 DCN20_VMID_MASK_SH_LIST(__SHIFT) 789 }; 790 791 static const struct dcn20_vmid_mask vmid_masks = { 792 DCN20_VMID_MASK_SH_LIST(_MASK) 793 }; 794 795 static const struct resource_caps res_cap_dcn321 = { 796 .num_timing_generator = 4, 797 .num_opp = 4, 798 .num_video_plane = 4, 799 .num_audio = 5, 800 .num_stream_encoder = 5, 801 .num_hpo_dp_stream_encoder = 4, 802 .num_hpo_dp_link_encoder = 2, 803 .num_pll = 5, 804 .num_dwb = 1, 805 .num_ddc = 5, 806 .num_vmid = 16, 807 .num_mpc_3dlut = 4, 808 .num_dsc = 4, 809 }; 810 811 static const struct dc_plane_cap plane_cap = { 812 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 813 .blends_with_above = true, 814 .blends_with_below = true, 815 .per_pixel_alpha = true, 816 817 .pixel_format_support = { 818 .argb8888 = true, 819 .nv12 = true, 820 .fp16 = true, 821 .p010 = true, 822 .ayuv = false, 823 }, 824 825 .max_upscale_factor = { 826 .argb8888 = 16000, 827 .nv12 = 16000, 828 .fp16 = 16000 829 }, 830 831 // 6:1 downscaling ratio: 1000/6 = 166.666 832 .max_downscale_factor = { 833 .argb8888 = 167, 834 .nv12 = 167, 835 .fp16 = 167 836 }, 837 64, 838 64 839 }; 840 841 static const struct dc_debug_options debug_defaults_drv = { 842 .disable_dmcu = true, 843 .force_abm_enable = false, 844 .timing_trace = false, 845 .clock_trace = true, 846 .disable_pplib_clock_request = false, 847 .pipe_split_policy = MPC_SPLIT_AVOID, 848 .force_single_disp_pipe_split = false, 849 .disable_dcc = DCC_ENABLE, 850 .vsr_support = true, 851 .performance_trace = false, 852 .max_downscale_src_width = 7680,/*upto 8K*/ 853 .disable_pplib_wm_range = false, 854 .scl_reset_length10 = true, 855 .sanity_checks = false, 856 .underflow_assert_delay_us = 0xFFFFFFFF, 857 .dwb_fi_phase = -1, // -1 = disable, 858 .dmub_command_table = true, 859 .enable_mem_low_power = { 860 .bits = { 861 .vga = false, 862 .i2c = false, 863 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 864 .dscl = false, 865 .cm = false, 866 .mpc = false, 867 .optc = true, 868 } 869 }, 870 .use_max_lb = true, 871 .force_disable_subvp = false, 872 .exit_idle_opt_for_cursor_updates = true, 873 .enable_single_display_2to1_odm_policy = true, 874 .enable_dp_dig_pixel_rate_div_policy = 1, 875 }; 876 877 static const struct dc_debug_options debug_defaults_diags = { 878 .disable_dmcu = true, 879 .force_abm_enable = false, 880 .timing_trace = true, 881 .clock_trace = true, 882 .disable_dpp_power_gate = true, 883 .disable_hubp_power_gate = true, 884 .disable_dsc_power_gate = true, 885 .disable_clock_gate = true, 886 .disable_pplib_clock_request = true, 887 .disable_pplib_wm_range = true, 888 .disable_stutter = false, 889 .scl_reset_length10 = true, 890 .dwb_fi_phase = -1, // -1 = disable 891 .dmub_command_table = true, 892 .enable_tri_buf = true, 893 .use_max_lb = true, 894 .force_disable_subvp = true 895 }; 896 897 898 static struct dce_aux *dcn321_aux_engine_create( 899 struct dc_context *ctx, 900 uint32_t inst) 901 { 902 struct aux_engine_dce110 *aux_engine = 903 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 904 905 if (!aux_engine) 906 return NULL; 907 908 dce110_aux_engine_construct(aux_engine, ctx, inst, 909 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 910 &aux_engine_regs[inst], 911 &aux_mask, 912 &aux_shift, 913 ctx->dc->caps.extended_aux_timeout_support); 914 915 return &aux_engine->base; 916 } 917 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 918 919 static const struct dce_i2c_registers i2c_hw_regs[] = { 920 i2c_inst_regs(1), 921 i2c_inst_regs(2), 922 i2c_inst_regs(3), 923 i2c_inst_regs(4), 924 i2c_inst_regs(5), 925 }; 926 927 static const struct dce_i2c_shift i2c_shifts = { 928 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 929 }; 930 931 static const struct dce_i2c_mask i2c_masks = { 932 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 933 }; 934 935 static struct dce_i2c_hw *dcn321_i2c_hw_create( 936 struct dc_context *ctx, 937 uint32_t inst) 938 { 939 struct dce_i2c_hw *dce_i2c_hw = 940 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 941 942 if (!dce_i2c_hw) 943 return NULL; 944 945 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 946 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 947 948 return dce_i2c_hw; 949 } 950 951 static struct clock_source *dcn321_clock_source_create( 952 struct dc_context *ctx, 953 struct dc_bios *bios, 954 enum clock_source_id id, 955 const struct dce110_clk_src_regs *regs, 956 bool dp_clk_src) 957 { 958 struct dce110_clk_src *clk_src = 959 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 960 961 if (!clk_src) 962 return NULL; 963 964 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 965 regs, &cs_shift, &cs_mask)) { 966 clk_src->base.dp_clk_src = dp_clk_src; 967 return &clk_src->base; 968 } 969 970 BREAK_TO_DEBUGGER(); 971 return NULL; 972 } 973 974 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 975 { 976 int i; 977 978 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 979 GFP_KERNEL); 980 981 if (!hubbub2) 982 return NULL; 983 984 hubbub32_construct(hubbub2, ctx, 985 &hubbub_reg, 986 &hubbub_shift, 987 &hubbub_mask, 988 ctx->dc->dml.ip.det_buffer_size_kbytes, 989 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 990 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 991 992 993 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 994 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 995 996 vmid->ctx = ctx; 997 998 vmid->regs = &vmid_regs[i]; 999 vmid->shifts = &vmid_shifts; 1000 vmid->masks = &vmid_masks; 1001 } 1002 1003 return &hubbub2->base; 1004 } 1005 1006 static struct hubp *dcn321_hubp_create( 1007 struct dc_context *ctx, 1008 uint32_t inst) 1009 { 1010 struct dcn20_hubp *hubp2 = 1011 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1012 1013 if (!hubp2) 1014 return NULL; 1015 1016 if (hubp32_construct(hubp2, ctx, inst, 1017 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1018 return &hubp2->base; 1019 1020 BREAK_TO_DEBUGGER(); 1021 kfree(hubp2); 1022 return NULL; 1023 } 1024 1025 static void dcn321_dpp_destroy(struct dpp **dpp) 1026 { 1027 kfree(TO_DCN30_DPP(*dpp)); 1028 *dpp = NULL; 1029 } 1030 1031 static struct dpp *dcn321_dpp_create( 1032 struct dc_context *ctx, 1033 uint32_t inst) 1034 { 1035 struct dcn3_dpp *dpp3 = 1036 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1037 1038 if (!dpp3) 1039 return NULL; 1040 1041 if (dpp32_construct(dpp3, ctx, inst, 1042 &dpp_regs[inst], &tf_shift, &tf_mask)) 1043 return &dpp3->base; 1044 1045 BREAK_TO_DEBUGGER(); 1046 kfree(dpp3); 1047 return NULL; 1048 } 1049 1050 static struct mpc *dcn321_mpc_create( 1051 struct dc_context *ctx, 1052 int num_mpcc, 1053 int num_rmu) 1054 { 1055 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1056 GFP_KERNEL); 1057 1058 if (!mpc30) 1059 return NULL; 1060 1061 dcn32_mpc_construct(mpc30, ctx, 1062 &mpc_regs, 1063 &mpc_shift, 1064 &mpc_mask, 1065 num_mpcc, 1066 num_rmu); 1067 1068 return &mpc30->base; 1069 } 1070 1071 static struct output_pixel_processor *dcn321_opp_create( 1072 struct dc_context *ctx, uint32_t inst) 1073 { 1074 struct dcn20_opp *opp2 = 1075 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1076 1077 if (!opp2) { 1078 BREAK_TO_DEBUGGER(); 1079 return NULL; 1080 } 1081 1082 dcn20_opp_construct(opp2, ctx, inst, 1083 &opp_regs[inst], &opp_shift, &opp_mask); 1084 return &opp2->base; 1085 } 1086 1087 1088 static struct timing_generator *dcn321_timing_generator_create( 1089 struct dc_context *ctx, 1090 uint32_t instance) 1091 { 1092 struct optc *tgn10 = 1093 kzalloc(sizeof(struct optc), GFP_KERNEL); 1094 1095 if (!tgn10) 1096 return NULL; 1097 1098 tgn10->base.inst = instance; 1099 tgn10->base.ctx = ctx; 1100 1101 tgn10->tg_regs = &optc_regs[instance]; 1102 tgn10->tg_shift = &optc_shift; 1103 tgn10->tg_mask = &optc_mask; 1104 1105 dcn32_timing_generator_init(tgn10); 1106 1107 return &tgn10->base; 1108 } 1109 1110 static const struct encoder_feature_support link_enc_feature = { 1111 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1112 .max_hdmi_pixel_clock = 600000, 1113 .hdmi_ycbcr420_supported = true, 1114 .dp_ycbcr420_supported = true, 1115 .fec_supported = true, 1116 .flags.bits.IS_HBR2_CAPABLE = true, 1117 .flags.bits.IS_HBR3_CAPABLE = true, 1118 .flags.bits.IS_TPS3_CAPABLE = true, 1119 .flags.bits.IS_TPS4_CAPABLE = true 1120 }; 1121 1122 static struct link_encoder *dcn321_link_encoder_create( 1123 struct dc_context *ctx, 1124 const struct encoder_init_data *enc_init_data) 1125 { 1126 struct dcn20_link_encoder *enc20 = 1127 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1128 1129 if (!enc20) 1130 return NULL; 1131 1132 dcn321_link_encoder_construct(enc20, 1133 enc_init_data, 1134 &link_enc_feature, 1135 &link_enc_regs[enc_init_data->transmitter], 1136 &link_enc_aux_regs[enc_init_data->channel - 1], 1137 &link_enc_hpd_regs[enc_init_data->hpd_source], 1138 &le_shift, 1139 &le_mask); 1140 1141 return &enc20->enc10.base; 1142 } 1143 1144 static void read_dce_straps( 1145 struct dc_context *ctx, 1146 struct resource_straps *straps) 1147 { 1148 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1149 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1150 1151 } 1152 1153 static struct audio *dcn321_create_audio( 1154 struct dc_context *ctx, unsigned int inst) 1155 { 1156 return dce_audio_create(ctx, inst, 1157 &audio_regs[inst], &audio_shift, &audio_mask); 1158 } 1159 1160 static struct vpg *dcn321_vpg_create( 1161 struct dc_context *ctx, 1162 uint32_t inst) 1163 { 1164 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1165 1166 if (!vpg3) 1167 return NULL; 1168 1169 vpg3_construct(vpg3, ctx, inst, 1170 &vpg_regs[inst], 1171 &vpg_shift, 1172 &vpg_mask); 1173 1174 return &vpg3->base; 1175 } 1176 1177 static struct afmt *dcn321_afmt_create( 1178 struct dc_context *ctx, 1179 uint32_t inst) 1180 { 1181 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1182 1183 if (!afmt3) 1184 return NULL; 1185 1186 afmt3_construct(afmt3, ctx, inst, 1187 &afmt_regs[inst], 1188 &afmt_shift, 1189 &afmt_mask); 1190 1191 return &afmt3->base; 1192 } 1193 1194 static struct apg *dcn321_apg_create( 1195 struct dc_context *ctx, 1196 uint32_t inst) 1197 { 1198 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1199 1200 if (!apg31) 1201 return NULL; 1202 1203 apg31_construct(apg31, ctx, inst, 1204 &apg_regs[inst], 1205 &apg_shift, 1206 &apg_mask); 1207 1208 return &apg31->base; 1209 } 1210 1211 static struct stream_encoder *dcn321_stream_encoder_create( 1212 enum engine_id eng_id, 1213 struct dc_context *ctx) 1214 { 1215 struct dcn10_stream_encoder *enc1; 1216 struct vpg *vpg; 1217 struct afmt *afmt; 1218 int vpg_inst; 1219 int afmt_inst; 1220 1221 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1222 if (eng_id <= ENGINE_ID_DIGF) { 1223 vpg_inst = eng_id; 1224 afmt_inst = eng_id; 1225 } else 1226 return NULL; 1227 1228 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1229 vpg = dcn321_vpg_create(ctx, vpg_inst); 1230 afmt = dcn321_afmt_create(ctx, afmt_inst); 1231 1232 if (!enc1 || !vpg || !afmt) { 1233 kfree(enc1); 1234 kfree(vpg); 1235 kfree(afmt); 1236 return NULL; 1237 } 1238 1239 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1240 eng_id, vpg, afmt, 1241 &stream_enc_regs[eng_id], 1242 &se_shift, &se_mask); 1243 1244 return &enc1->base; 1245 } 1246 1247 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1248 enum engine_id eng_id, 1249 struct dc_context *ctx) 1250 { 1251 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1252 struct vpg *vpg; 1253 struct apg *apg; 1254 uint32_t hpo_dp_inst; 1255 uint32_t vpg_inst; 1256 uint32_t apg_inst; 1257 1258 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1259 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1260 1261 /* Mapping of VPG register blocks to HPO DP block instance: 1262 * VPG[6] -> HPO_DP[0] 1263 * VPG[7] -> HPO_DP[1] 1264 * VPG[8] -> HPO_DP[2] 1265 * VPG[9] -> HPO_DP[3] 1266 */ 1267 vpg_inst = hpo_dp_inst + 6; 1268 1269 /* Mapping of APG register blocks to HPO DP block instance: 1270 * APG[0] -> HPO_DP[0] 1271 * APG[1] -> HPO_DP[1] 1272 * APG[2] -> HPO_DP[2] 1273 * APG[3] -> HPO_DP[3] 1274 */ 1275 apg_inst = hpo_dp_inst; 1276 1277 /* allocate HPO stream encoder and create VPG sub-block */ 1278 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1279 vpg = dcn321_vpg_create(ctx, vpg_inst); 1280 apg = dcn321_apg_create(ctx, apg_inst); 1281 1282 if (!hpo_dp_enc31 || !vpg || !apg) { 1283 kfree(hpo_dp_enc31); 1284 kfree(vpg); 1285 kfree(apg); 1286 return NULL; 1287 } 1288 1289 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1290 hpo_dp_inst, eng_id, vpg, apg, 1291 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1292 &hpo_dp_se_shift, &hpo_dp_se_mask); 1293 1294 return &hpo_dp_enc31->base; 1295 } 1296 1297 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1298 uint8_t inst, 1299 struct dc_context *ctx) 1300 { 1301 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1302 1303 /* allocate HPO link encoder */ 1304 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1305 1306 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1307 &hpo_dp_link_enc_regs[inst], 1308 &hpo_dp_le_shift, &hpo_dp_le_mask); 1309 1310 return &hpo_dp_enc31->base; 1311 } 1312 1313 static struct dce_hwseq *dcn321_hwseq_create( 1314 struct dc_context *ctx) 1315 { 1316 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1317 1318 if (hws) { 1319 hws->ctx = ctx; 1320 hws->regs = &hwseq_reg; 1321 hws->shifts = &hwseq_shift; 1322 hws->masks = &hwseq_mask; 1323 } 1324 return hws; 1325 } 1326 static const struct resource_create_funcs res_create_funcs = { 1327 .read_dce_straps = read_dce_straps, 1328 .create_audio = dcn321_create_audio, 1329 .create_stream_encoder = dcn321_stream_encoder_create, 1330 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1331 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1332 .create_hwseq = dcn321_hwseq_create, 1333 }; 1334 1335 static const struct resource_create_funcs res_create_maximus_funcs = { 1336 .read_dce_straps = NULL, 1337 .create_audio = NULL, 1338 .create_stream_encoder = NULL, 1339 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1340 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1341 .create_hwseq = dcn321_hwseq_create, 1342 }; 1343 1344 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1345 { 1346 unsigned int i; 1347 1348 for (i = 0; i < pool->base.stream_enc_count; i++) { 1349 if (pool->base.stream_enc[i] != NULL) { 1350 if (pool->base.stream_enc[i]->vpg != NULL) { 1351 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1352 pool->base.stream_enc[i]->vpg = NULL; 1353 } 1354 if (pool->base.stream_enc[i]->afmt != NULL) { 1355 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1356 pool->base.stream_enc[i]->afmt = NULL; 1357 } 1358 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1359 pool->base.stream_enc[i] = NULL; 1360 } 1361 } 1362 1363 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1364 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1365 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1366 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1367 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1368 } 1369 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1370 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1371 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1372 } 1373 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1374 pool->base.hpo_dp_stream_enc[i] = NULL; 1375 } 1376 } 1377 1378 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1379 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1380 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1381 pool->base.hpo_dp_link_enc[i] = NULL; 1382 } 1383 } 1384 1385 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1386 if (pool->base.dscs[i] != NULL) 1387 dcn20_dsc_destroy(&pool->base.dscs[i]); 1388 } 1389 1390 if (pool->base.mpc != NULL) { 1391 kfree(TO_DCN20_MPC(pool->base.mpc)); 1392 pool->base.mpc = NULL; 1393 } 1394 if (pool->base.hubbub != NULL) { 1395 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1396 pool->base.hubbub = NULL; 1397 } 1398 for (i = 0; i < pool->base.pipe_count; i++) { 1399 if (pool->base.dpps[i] != NULL) 1400 dcn321_dpp_destroy(&pool->base.dpps[i]); 1401 1402 if (pool->base.ipps[i] != NULL) 1403 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1404 1405 if (pool->base.hubps[i] != NULL) { 1406 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1407 pool->base.hubps[i] = NULL; 1408 } 1409 1410 if (pool->base.irqs != NULL) 1411 dal_irq_service_destroy(&pool->base.irqs); 1412 } 1413 1414 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1415 if (pool->base.engines[i] != NULL) 1416 dce110_engine_destroy(&pool->base.engines[i]); 1417 if (pool->base.hw_i2cs[i] != NULL) { 1418 kfree(pool->base.hw_i2cs[i]); 1419 pool->base.hw_i2cs[i] = NULL; 1420 } 1421 if (pool->base.sw_i2cs[i] != NULL) { 1422 kfree(pool->base.sw_i2cs[i]); 1423 pool->base.sw_i2cs[i] = NULL; 1424 } 1425 } 1426 1427 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1428 if (pool->base.opps[i] != NULL) 1429 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1430 } 1431 1432 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1433 if (pool->base.timing_generators[i] != NULL) { 1434 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1435 pool->base.timing_generators[i] = NULL; 1436 } 1437 } 1438 1439 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1440 if (pool->base.dwbc[i] != NULL) { 1441 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1442 pool->base.dwbc[i] = NULL; 1443 } 1444 if (pool->base.mcif_wb[i] != NULL) { 1445 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1446 pool->base.mcif_wb[i] = NULL; 1447 } 1448 } 1449 1450 for (i = 0; i < pool->base.audio_count; i++) { 1451 if (pool->base.audios[i]) 1452 dce_aud_destroy(&pool->base.audios[i]); 1453 } 1454 1455 for (i = 0; i < pool->base.clk_src_count; i++) { 1456 if (pool->base.clock_sources[i] != NULL) { 1457 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1458 pool->base.clock_sources[i] = NULL; 1459 } 1460 } 1461 1462 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1463 if (pool->base.mpc_lut[i] != NULL) { 1464 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1465 pool->base.mpc_lut[i] = NULL; 1466 } 1467 if (pool->base.mpc_shaper[i] != NULL) { 1468 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1469 pool->base.mpc_shaper[i] = NULL; 1470 } 1471 } 1472 1473 if (pool->base.dp_clock_source != NULL) { 1474 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1475 pool->base.dp_clock_source = NULL; 1476 } 1477 1478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1479 if (pool->base.multiple_abms[i] != NULL) 1480 dce_abm_destroy(&pool->base.multiple_abms[i]); 1481 } 1482 1483 if (pool->base.psr != NULL) 1484 dmub_psr_destroy(&pool->base.psr); 1485 1486 if (pool->base.dccg != NULL) 1487 dcn_dccg_destroy(&pool->base.dccg); 1488 1489 if (pool->base.oem_device != NULL) 1490 dal_ddc_service_destroy(&pool->base.oem_device); 1491 } 1492 1493 1494 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1495 { 1496 int i; 1497 uint32_t dwb_count = pool->res_cap->num_dwb; 1498 1499 for (i = 0; i < dwb_count; i++) { 1500 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1501 GFP_KERNEL); 1502 1503 if (!dwbc30) { 1504 dm_error("DC: failed to create dwbc30!\n"); 1505 return false; 1506 } 1507 1508 dcn30_dwbc_construct(dwbc30, ctx, 1509 &dwbc30_regs[i], 1510 &dwbc30_shift, 1511 &dwbc30_mask, 1512 i); 1513 1514 pool->dwbc[i] = &dwbc30->base; 1515 } 1516 return true; 1517 } 1518 1519 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1520 { 1521 int i; 1522 uint32_t dwb_count = pool->res_cap->num_dwb; 1523 1524 for (i = 0; i < dwb_count; i++) { 1525 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1526 GFP_KERNEL); 1527 1528 if (!mcif_wb30) { 1529 dm_error("DC: failed to create mcif_wb30!\n"); 1530 return false; 1531 } 1532 1533 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1534 &mcif_wb30_regs[i], 1535 &mcif_wb30_shift, 1536 &mcif_wb30_mask, 1537 i); 1538 1539 pool->mcif_wb[i] = &mcif_wb30->base; 1540 } 1541 return true; 1542 } 1543 1544 static struct display_stream_compressor *dcn321_dsc_create( 1545 struct dc_context *ctx, uint32_t inst) 1546 { 1547 struct dcn20_dsc *dsc = 1548 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1549 1550 if (!dsc) { 1551 BREAK_TO_DEBUGGER(); 1552 return NULL; 1553 } 1554 1555 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1556 1557 dsc->max_image_width = 6016; 1558 1559 return &dsc->base; 1560 } 1561 1562 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1563 { 1564 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1565 1566 dcn321_resource_destruct(dcn321_pool); 1567 kfree(dcn321_pool); 1568 *pool = NULL; 1569 } 1570 1571 static struct dc_cap_funcs cap_funcs = { 1572 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1573 }; 1574 1575 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1576 { 1577 DC_FP_START(); 1578 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1579 DC_FP_END(); 1580 } 1581 1582 static struct resource_funcs dcn321_res_pool_funcs = { 1583 .destroy = dcn321_destroy_resource_pool, 1584 .link_enc_create = dcn321_link_encoder_create, 1585 .link_enc_create_minimal = NULL, 1586 .panel_cntl_create = dcn32_panel_cntl_create, 1587 .validate_bandwidth = dcn32_validate_bandwidth, 1588 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1589 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1590 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1591 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1592 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1593 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1594 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1595 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1596 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1597 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1598 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1599 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1600 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1601 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1602 .add_phantom_pipes = dcn32_add_phantom_pipes, 1603 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1604 }; 1605 1606 1607 static bool dcn321_resource_construct( 1608 uint8_t num_virtual_links, 1609 struct dc *dc, 1610 struct dcn321_resource_pool *pool) 1611 { 1612 int i, j; 1613 struct dc_context *ctx = dc->ctx; 1614 struct irq_service_init_data init_data; 1615 struct ddc_service_init_data ddc_init_data = {0}; 1616 uint32_t pipe_fuses = 0; 1617 uint32_t num_pipes = 4; 1618 1619 ctx->dc_bios->regs = &bios_regs; 1620 1621 pool->base.res_cap = &res_cap_dcn321; 1622 /* max number of pipes for ASIC before checking for pipe fuses */ 1623 num_pipes = pool->base.res_cap->num_timing_generator; 1624 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1625 1626 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1627 if (pipe_fuses & 1 << i) 1628 num_pipes--; 1629 1630 if (pipe_fuses & 1) 1631 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1632 1633 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1634 ASSERT(0); //Entire DCN is harvested! 1635 1636 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1637 * value will be changed, update max_num_dpp and max_num_otg for dml. 1638 */ 1639 dcn3_21_ip.max_num_dpp = num_pipes; 1640 dcn3_21_ip.max_num_otg = num_pipes; 1641 1642 pool->base.funcs = &dcn321_res_pool_funcs; 1643 1644 /************************************************* 1645 * Resource + asic cap harcoding * 1646 *************************************************/ 1647 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1648 pool->base.timing_generator_count = num_pipes; 1649 pool->base.pipe_count = num_pipes; 1650 pool->base.mpcc_count = num_pipes; 1651 dc->caps.max_downscale_ratio = 600; 1652 dc->caps.i2c_speed_in_khz = 100; 1653 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1654 dc->caps.max_cursor_size = 256; 1655 dc->caps.min_horizontal_blanking_period = 80; 1656 dc->caps.dmdata_alloc_size = 2048; 1657 dc->caps.mall_size_per_mem_channel = 0; 1658 dc->caps.mall_size_total = 0; 1659 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1660 dc->caps.cache_line_size = 64; 1661 dc->caps.cache_num_ways = 16; 1662 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 1663 dc->caps.subvp_fw_processing_delay_us = 15; 1664 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1665 dc->caps.subvp_swath_height_margin_lines = 16; 1666 dc->caps.subvp_pstate_allow_width_us = 20; 1667 dc->caps.subvp_vertical_int_margin_us = 30; 1668 dc->caps.max_slave_planes = 1; 1669 dc->caps.max_slave_yuv_planes = 1; 1670 dc->caps.max_slave_rgb_planes = 1; 1671 dc->caps.post_blend_color_processing = true; 1672 dc->caps.force_dp_tps4_for_cp2520 = true; 1673 dc->caps.dp_hpo = true; 1674 dc->caps.dp_hdmi21_pcon_support = true; 1675 dc->caps.edp_dsc_support = true; 1676 dc->caps.extended_aux_timeout_support = true; 1677 dc->caps.dmcub_support = true; 1678 1679 /* Color pipeline capabilities */ 1680 dc->caps.color.dpp.dcn_arch = 1; 1681 dc->caps.color.dpp.input_lut_shared = 0; 1682 dc->caps.color.dpp.icsc = 1; 1683 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1684 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1685 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1686 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1687 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1688 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1689 dc->caps.color.dpp.post_csc = 1; 1690 dc->caps.color.dpp.gamma_corr = 1; 1691 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1692 1693 dc->caps.color.dpp.hw_3d_lut = 1; 1694 dc->caps.color.dpp.ogam_ram = 1; 1695 // no OGAM ROM on DCN2 and later ASICs 1696 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1697 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1698 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1699 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1700 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1701 dc->caps.color.dpp.ocsc = 0; 1702 1703 dc->caps.color.mpc.gamut_remap = 1; 1704 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1705 dc->caps.color.mpc.ogam_ram = 1; 1706 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1707 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1708 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1709 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1710 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1711 dc->caps.color.mpc.ocsc = 1; 1712 1713 /* read VBIOS LTTPR caps */ 1714 { 1715 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1716 enum bp_result bp_query_result; 1717 uint8_t is_vbios_lttpr_enable = 0; 1718 1719 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1720 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1721 } 1722 1723 /* interop bit is implicit */ 1724 { 1725 dc->caps.vbios_lttpr_aware = true; 1726 } 1727 } 1728 1729 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1730 dc->debug = debug_defaults_drv; 1731 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1732 dc->debug = debug_defaults_diags; 1733 } else 1734 dc->debug = debug_defaults_diags; 1735 // Init the vm_helper 1736 if (dc->vm_helper) 1737 vm_helper_init(dc->vm_helper, 16); 1738 1739 /************************************************* 1740 * Create resources * 1741 *************************************************/ 1742 1743 /* Clock Sources for Pixel Clock*/ 1744 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1745 dcn321_clock_source_create(ctx, ctx->dc_bios, 1746 CLOCK_SOURCE_COMBO_PHY_PLL0, 1747 &clk_src_regs[0], false); 1748 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1749 dcn321_clock_source_create(ctx, ctx->dc_bios, 1750 CLOCK_SOURCE_COMBO_PHY_PLL1, 1751 &clk_src_regs[1], false); 1752 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1753 dcn321_clock_source_create(ctx, ctx->dc_bios, 1754 CLOCK_SOURCE_COMBO_PHY_PLL2, 1755 &clk_src_regs[2], false); 1756 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1757 dcn321_clock_source_create(ctx, ctx->dc_bios, 1758 CLOCK_SOURCE_COMBO_PHY_PLL3, 1759 &clk_src_regs[3], false); 1760 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1761 dcn321_clock_source_create(ctx, ctx->dc_bios, 1762 CLOCK_SOURCE_COMBO_PHY_PLL4, 1763 &clk_src_regs[4], false); 1764 1765 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1766 1767 /* todo: not reuse phy_pll registers */ 1768 pool->base.dp_clock_source = 1769 dcn321_clock_source_create(ctx, ctx->dc_bios, 1770 CLOCK_SOURCE_ID_DP_DTO, 1771 &clk_src_regs[0], true); 1772 1773 for (i = 0; i < pool->base.clk_src_count; i++) { 1774 if (pool->base.clock_sources[i] == NULL) { 1775 dm_error("DC: failed to create clock sources!\n"); 1776 BREAK_TO_DEBUGGER(); 1777 goto create_fail; 1778 } 1779 } 1780 1781 /* DCCG */ 1782 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1783 if (pool->base.dccg == NULL) { 1784 dm_error("DC: failed to create dccg!\n"); 1785 BREAK_TO_DEBUGGER(); 1786 goto create_fail; 1787 } 1788 1789 /* DML */ 1790 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1791 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1792 1793 /* IRQ Service */ 1794 init_data.ctx = dc->ctx; 1795 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1796 if (!pool->base.irqs) 1797 goto create_fail; 1798 1799 /* HUBBUB */ 1800 pool->base.hubbub = dcn321_hubbub_create(ctx); 1801 if (pool->base.hubbub == NULL) { 1802 BREAK_TO_DEBUGGER(); 1803 dm_error("DC: failed to create hubbub!\n"); 1804 goto create_fail; 1805 } 1806 1807 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1808 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1809 1810 /* if pipe is disabled, skip instance of HW pipe, 1811 * i.e, skip ASIC register instance 1812 */ 1813 if (pipe_fuses & 1 << i) 1814 continue; 1815 1816 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1817 if (pool->base.hubps[j] == NULL) { 1818 BREAK_TO_DEBUGGER(); 1819 dm_error( 1820 "DC: failed to create hubps!\n"); 1821 goto create_fail; 1822 } 1823 1824 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1825 if (pool->base.dpps[j] == NULL) { 1826 BREAK_TO_DEBUGGER(); 1827 dm_error( 1828 "DC: failed to create dpps!\n"); 1829 goto create_fail; 1830 } 1831 1832 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1833 if (pool->base.opps[j] == NULL) { 1834 BREAK_TO_DEBUGGER(); 1835 dm_error( 1836 "DC: failed to create output pixel processor!\n"); 1837 goto create_fail; 1838 } 1839 1840 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1841 ctx, i); 1842 if (pool->base.timing_generators[j] == NULL) { 1843 BREAK_TO_DEBUGGER(); 1844 dm_error("DC: failed to create tg!\n"); 1845 goto create_fail; 1846 } 1847 1848 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1849 &abm_regs[i], 1850 &abm_shift, 1851 &abm_mask); 1852 if (pool->base.multiple_abms[j] == NULL) { 1853 dm_error("DC: failed to create abm for pipe %d!\n", i); 1854 BREAK_TO_DEBUGGER(); 1855 goto create_fail; 1856 } 1857 1858 /* index for resource pool arrays for next valid pipe */ 1859 j++; 1860 } 1861 1862 /* PSR */ 1863 pool->base.psr = dmub_psr_create(ctx); 1864 if (pool->base.psr == NULL) { 1865 dm_error("DC: failed to create psr obj!\n"); 1866 BREAK_TO_DEBUGGER(); 1867 goto create_fail; 1868 } 1869 1870 /* MPCCs */ 1871 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1872 if (pool->base.mpc == NULL) { 1873 BREAK_TO_DEBUGGER(); 1874 dm_error("DC: failed to create mpc!\n"); 1875 goto create_fail; 1876 } 1877 1878 /* DSCs */ 1879 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1880 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1881 if (pool->base.dscs[i] == NULL) { 1882 BREAK_TO_DEBUGGER(); 1883 dm_error("DC: failed to create display stream compressor %d!\n", i); 1884 goto create_fail; 1885 } 1886 } 1887 1888 /* DWB */ 1889 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1890 BREAK_TO_DEBUGGER(); 1891 dm_error("DC: failed to create dwbc!\n"); 1892 goto create_fail; 1893 } 1894 1895 /* MMHUBBUB */ 1896 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1897 BREAK_TO_DEBUGGER(); 1898 dm_error("DC: failed to create mcif_wb!\n"); 1899 goto create_fail; 1900 } 1901 1902 /* AUX and I2C */ 1903 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1904 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1905 if (pool->base.engines[i] == NULL) { 1906 BREAK_TO_DEBUGGER(); 1907 dm_error( 1908 "DC:failed to create aux engine!!\n"); 1909 goto create_fail; 1910 } 1911 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1912 if (pool->base.hw_i2cs[i] == NULL) { 1913 BREAK_TO_DEBUGGER(); 1914 dm_error( 1915 "DC:failed to create hw i2c!!\n"); 1916 goto create_fail; 1917 } 1918 pool->base.sw_i2cs[i] = NULL; 1919 } 1920 1921 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1922 if (!resource_construct(num_virtual_links, dc, &pool->base, 1923 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1924 &res_create_funcs : &res_create_maximus_funcs))) 1925 goto create_fail; 1926 1927 /* HW Sequencer init functions and Plane caps */ 1928 dcn32_hw_sequencer_init_functions(dc); 1929 1930 dc->caps.max_planes = pool->base.pipe_count; 1931 1932 for (i = 0; i < dc->caps.max_planes; ++i) 1933 dc->caps.planes[i] = plane_cap; 1934 1935 dc->cap_funcs = cap_funcs; 1936 1937 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1938 ddc_init_data.ctx = dc->ctx; 1939 ddc_init_data.link = NULL; 1940 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1941 ddc_init_data.id.enum_id = 0; 1942 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1943 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 1944 } else { 1945 pool->base.oem_device = NULL; 1946 } 1947 1948 return true; 1949 1950 create_fail: 1951 1952 dcn321_resource_destruct(pool); 1953 1954 return false; 1955 } 1956 1957 struct resource_pool *dcn321_create_resource_pool( 1958 const struct dc_init_data *init_data, 1959 struct dc *dc) 1960 { 1961 struct dcn321_resource_pool *pool = 1962 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 1963 1964 if (!pool) 1965 return NULL; 1966 1967 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 1968 return &pool->base; 1969 1970 BREAK_TO_DEBUGGER(); 1971 kfree(pool); 1972 return NULL; 1973 } 1974