1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn32/dcn32_hubbub.h" 44 #include "dcn32/dcn32_mpc.h" 45 #include "dcn32/dcn32_hubp.h" 46 #include "irq/dcn32/irq_service_dcn32.h" 47 #include "dcn32/dcn32_dpp.h" 48 #include "dcn32/dcn32_optc.h" 49 #include "dcn20/dcn20_hwseq.h" 50 #include "dcn30/dcn30_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dcn30/dcn30_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dcn30/dcn30_afmt.h" 56 #include "dcn30/dcn30_dio_stream_encoder.h" 57 #include "dcn32/dcn32_dio_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 59 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 60 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 61 #include "dc_link_dp.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_dio_link_encoder.h" 64 #include "dcn32/dcn32_dio_link_encoder.h" 65 #include "dcn321_dio_link_encoder.h" 66 #include "dce/dce_clock_source.h" 67 #include "dce/dce_audio.h" 68 #include "dce/dce_hwseq.h" 69 #include "clk_mgr.h" 70 #include "virtual/virtual_stream_encoder.h" 71 #include "dml/display_mode_vba.h" 72 #include "dcn32/dcn32_dccg.h" 73 #include "dcn10/dcn10_resource.h" 74 #include "dc_link_ddc.h" 75 #include "dcn31/dcn31_panel_cntl.h" 76 77 #include "dcn30/dcn30_dwb.h" 78 #include "dcn32/dcn32_mmhubbub.h" 79 80 #include "dcn/dcn_3_2_1_offset.h" 81 #include "dcn/dcn_3_2_1_sh_mask.h" 82 #include "nbio/nbio_4_3_0_offset.h" 83 84 #include "reg_helper.h" 85 #include "dce/dmub_abm.h" 86 #include "dce/dmub_psr.h" 87 #include "dce/dce_aux.h" 88 #include "dce/dce_i2c.h" 89 90 #include "dml/dcn30/display_mode_vba_30.h" 91 #include "vm_helper.h" 92 #include "dcn20/dcn20_vmid.h" 93 94 #define DCN_BASE__INST0_SEG1 0x000000C0 95 #define DCN_BASE__INST0_SEG2 0x000034C0 96 #define DCN_BASE__INST0_SEG3 0x00009000 97 #define NBIO_BASE__INST0_SEG1 0x00000014 98 99 #define MAX_INSTANCE 8 100 #define MAX_SEGMENT 6 101 102 struct IP_BASE_INSTANCE { 103 unsigned int segment[MAX_SEGMENT]; 104 }; 105 106 struct IP_BASE { 107 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 108 }; 109 110 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } } } }; 118 119 #define DC_LOGGER_INIT(logger) 120 #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) 121 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 122 123 #define DCN3_2_DEFAULT_DET_SIZE 256 124 125 struct _vcs_dpi_ip_params_st dcn3_21_ip = { 126 .gpuvm_enable = 1, 127 .gpuvm_max_page_table_levels = 1, 128 .hostvm_enable = 0, 129 .rob_buffer_size_kbytes = 128, 130 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 131 .config_return_buffer_size_in_kbytes = 1280, 132 .compressed_buffer_segment_size_in_kbytes = 64, 133 .meta_fifo_size_in_kentries = 22, 134 .zero_size_buffer_entries = 512, 135 .compbuf_reserved_space_64b = 256, 136 .compbuf_reserved_space_zs = 64, 137 .dpp_output_buffer_pixels = 2560, 138 .opp_output_buffer_lines = 1, 139 .pixel_chunk_size_kbytes = 8, 140 .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team 141 .min_pixel_chunk_size_bytes = 1024, 142 .dcc_meta_buffer_size_bytes = 6272, 143 .meta_chunk_size_kbytes = 2, 144 .min_meta_chunk_size_bytes = 256, 145 .writeback_chunk_size_kbytes = 8, 146 .ptoi_supported = false, 147 .num_dsc = 4, 148 .maximum_dsc_bits_per_component = 12, 149 .maximum_pixels_per_line_per_dsc_unit = 6016, 150 .dsc422_native_support = true, 151 .is_line_buffer_bpp_fixed = true, 152 .line_buffer_fixed_bpp = 57, 153 .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp 154 .max_line_buffer_lines = 32, 155 .writeback_interface_buffer_size_kbytes = 90, 156 .max_num_dpp = 4, 157 .max_num_otg = 4, 158 .max_num_hdmi_frl_outputs = 1, 159 .max_num_wb = 1, 160 .max_dchub_pscl_bw_pix_per_clk = 4, 161 .max_pscl_lb_bw_pix_per_clk = 2, 162 .max_lb_vscl_bw_pix_per_clk = 4, 163 .max_vscl_hscl_bw_pix_per_clk = 4, 164 .max_hscl_ratio = 6, 165 .max_vscl_ratio = 6, 166 .max_hscl_taps = 8, 167 .max_vscl_taps = 8, 168 .dpte_buffer_size_in_pte_reqs_luma = 64, 169 .dpte_buffer_size_in_pte_reqs_chroma = 34, 170 .dispclk_ramp_margin_percent = 1, 171 .max_inter_dcn_tile_repeaters = 8, 172 .cursor_buffer_size = 16, 173 .cursor_chunk_size = 2, 174 .writeback_line_buffer_buffer_size = 0, 175 .writeback_min_hscl_ratio = 1, 176 .writeback_min_vscl_ratio = 1, 177 .writeback_max_hscl_ratio = 1, 178 .writeback_max_vscl_ratio = 1, 179 .writeback_max_hscl_taps = 1, 180 .writeback_max_vscl_taps = 1, 181 .dppclk_delay_subtotal = 47, 182 .dppclk_delay_scl = 50, 183 .dppclk_delay_scl_lb_only = 16, 184 .dppclk_delay_cnvc_formatter = 28, 185 .dppclk_delay_cnvc_cursor = 6, 186 .dispclk_delay_subtotal = 125, 187 .dynamic_metadata_vm_enabled = false, 188 .odm_combine_4to1_supported = false, 189 .dcc_supported = true, 190 .max_num_dp2p0_outputs = 2, 191 .max_num_dp2p0_streams = 4, 192 }; 193 194 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 195 .clock_limits = { 196 { 197 .state = 0, 198 .dcfclk_mhz = 1564.0, 199 .fabricclk_mhz = 400.0, 200 .dispclk_mhz = 2150.0, 201 .dppclk_mhz = 2150.0, 202 .phyclk_mhz = 810.0, 203 .phyclk_d18_mhz = 667.0, 204 .phyclk_d32_mhz = 625.0, 205 .socclk_mhz = 1200.0, 206 .dscclk_mhz = 716.667, 207 .dram_speed_mts = 1600.0, 208 .dtbclk_mhz = 1564.0, 209 }, 210 }, 211 .num_states = 1, 212 .sr_exit_time_us = 5.20, 213 .sr_enter_plus_exit_time_us = 9.60, 214 .sr_exit_z8_time_us = 285.0, 215 .sr_enter_plus_exit_z8_time_us = 320, 216 .writeback_latency_us = 12.0, 217 .round_trip_ping_latency_dcfclk_cycles = 263, 218 .urgent_latency_pixel_data_only_us = 4.0, 219 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 220 .urgent_latency_vm_data_only_us = 4.0, 221 .fclk_change_latency_us = 20, 222 .usr_retraining_latency_us = 2, 223 .smn_latency_us = 2, 224 .mall_allocated_for_dcn_mbytes = 64, 225 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 226 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 227 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 228 .pct_ideal_sdp_bw_after_urgent = 100.0, 229 .pct_ideal_fabric_bw_after_urgent = 67.0, 230 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 231 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 232 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 233 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 234 .max_avg_sdp_bw_use_normal_percent = 80.0, 235 .max_avg_fabric_bw_use_normal_percent = 60.0, 236 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 237 .max_avg_dram_bw_use_normal_percent = 15.0, 238 .num_chans = 8, 239 .dram_channel_width_bytes = 2, 240 .fabric_datapath_to_dcn_data_return_bytes = 64, 241 .return_bus_width_bytes = 64, 242 .downspread_percent = 0.38, 243 .dcn_downspread_percent = 0.5, 244 .dram_clock_change_latency_us = 400, 245 .dispclk_dppclk_vco_speed_mhz = 4300.0, 246 .do_urgent_latency_adjustment = true, 247 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 248 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 249 }; 250 251 enum dcn321_clk_src_array_id { 252 DCN321_CLK_SRC_PLL0, 253 DCN321_CLK_SRC_PLL1, 254 DCN321_CLK_SRC_PLL2, 255 DCN321_CLK_SRC_PLL3, 256 DCN321_CLK_SRC_PLL4, 257 DCN321_CLK_SRC_TOTAL 258 }; 259 260 /* begin ********************* 261 * macros to expend register list macro defined in HW object header file 262 */ 263 264 /* DCN */ 265 /* TODO awful hack. fixup dcn20_dwb.h */ 266 #undef BASE_INNER 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 268 269 #define BASE(seg) BASE_INNER(seg) 270 271 #define SR(reg_name)\ 272 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 273 reg ## reg_name 274 275 #define SRI(reg_name, block, id)\ 276 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 277 reg ## block ## id ## _ ## reg_name 278 279 #define SRI2(reg_name, block, id)\ 280 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 281 reg ## reg_name 282 283 #define SRIR(var_name, reg_name, block, id)\ 284 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 285 reg ## block ## id ## _ ## reg_name 286 287 #define SRII(reg_name, block, id)\ 288 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 reg ## block ## id ## _ ## reg_name 290 291 #define SRII_MPC_RMU(reg_name, block, id)\ 292 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 293 reg ## block ## id ## _ ## reg_name 294 295 #define SRII_DWB(reg_name, temp_name, block, id)\ 296 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 297 reg ## block ## id ## _ ## temp_name 298 299 #define DCCG_SRII(reg_name, block, id)\ 300 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 301 reg ## block ## id ## _ ## reg_name 302 303 #define VUPDATE_SRII(reg_name, block, id)\ 304 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 305 reg ## reg_name ## _ ## block ## id 306 307 /* NBIO */ 308 #define NBIO_BASE_INNER(seg) \ 309 NBIO_BASE__INST0_SEG ## seg 310 311 #define NBIO_BASE(seg) \ 312 NBIO_BASE_INNER(seg) 313 314 #define NBIO_SR(reg_name)\ 315 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 316 regBIF_BX0_ ## reg_name 317 318 #define CTX ctx 319 #define REG(reg_name) \ 320 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 321 322 static const struct bios_registers bios_regs = { 323 NBIO_SR(BIOS_SCRATCH_3), 324 NBIO_SR(BIOS_SCRATCH_6) 325 }; 326 327 #define clk_src_regs(index, pllid)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E) 338 }; 339 340 static const struct dce110_clk_src_shift cs_shift = { 341 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 342 }; 343 344 static const struct dce110_clk_src_mask cs_mask = { 345 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 346 }; 347 348 #define abm_regs(id)\ 349 [id] = {\ 350 ABM_DCN32_REG_LIST(id)\ 351 } 352 353 static const struct dce_abm_registers abm_regs[] = { 354 abm_regs(0), 355 abm_regs(1), 356 abm_regs(2), 357 abm_regs(3), 358 }; 359 360 static const struct dce_abm_shift abm_shift = { 361 ABM_MASK_SH_LIST_DCN32(__SHIFT) 362 }; 363 364 static const struct dce_abm_mask abm_mask = { 365 ABM_MASK_SH_LIST_DCN32(_MASK) 366 }; 367 368 #define audio_regs(id)\ 369 [id] = {\ 370 AUD_COMMON_REG_LIST(id)\ 371 } 372 373 static const struct dce_audio_registers audio_regs[] = { 374 audio_regs(0), 375 audio_regs(1), 376 audio_regs(2), 377 audio_regs(3), 378 audio_regs(4) 379 }; 380 381 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 382 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 384 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 385 386 static const struct dce_audio_shift audio_shift = { 387 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 388 }; 389 390 static const struct dce_audio_mask audio_mask = { 391 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 392 }; 393 394 #define vpg_regs(id)\ 395 [id] = {\ 396 VPG_DCN3_REG_LIST(id)\ 397 } 398 399 static const struct dcn30_vpg_registers vpg_regs[] = { 400 vpg_regs(0), 401 vpg_regs(1), 402 vpg_regs(2), 403 vpg_regs(3), 404 vpg_regs(4), 405 vpg_regs(5), 406 vpg_regs(6), 407 vpg_regs(7), 408 vpg_regs(8), 409 vpg_regs(9), 410 }; 411 412 static const struct dcn30_vpg_shift vpg_shift = { 413 DCN3_VPG_MASK_SH_LIST(__SHIFT) 414 }; 415 416 static const struct dcn30_vpg_mask vpg_mask = { 417 DCN3_VPG_MASK_SH_LIST(_MASK) 418 }; 419 420 #define afmt_regs(id)\ 421 [id] = {\ 422 AFMT_DCN3_REG_LIST(id)\ 423 } 424 425 static const struct dcn30_afmt_registers afmt_regs[] = { 426 afmt_regs(0), 427 afmt_regs(1), 428 afmt_regs(2), 429 afmt_regs(3), 430 afmt_regs(4), 431 afmt_regs(5) 432 }; 433 434 static const struct dcn30_afmt_shift afmt_shift = { 435 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 436 }; 437 438 static const struct dcn30_afmt_mask afmt_mask = { 439 DCN3_AFMT_MASK_SH_LIST(_MASK) 440 }; 441 442 #define apg_regs(id)\ 443 [id] = {\ 444 APG_DCN31_REG_LIST(id)\ 445 } 446 447 static const struct dcn31_apg_registers apg_regs[] = { 448 apg_regs(0), 449 apg_regs(1), 450 apg_regs(2), 451 apg_regs(3) 452 }; 453 454 static const struct dcn31_apg_shift apg_shift = { 455 DCN31_APG_MASK_SH_LIST(__SHIFT) 456 }; 457 458 static const struct dcn31_apg_mask apg_mask = { 459 DCN31_APG_MASK_SH_LIST(_MASK) 460 }; 461 462 #define stream_enc_regs(id)\ 463 [id] = {\ 464 SE_DCN32_REG_LIST(id)\ 465 } 466 467 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 468 stream_enc_regs(0), 469 stream_enc_regs(1), 470 stream_enc_regs(2), 471 stream_enc_regs(3), 472 stream_enc_regs(4) 473 }; 474 475 static const struct dcn10_stream_encoder_shift se_shift = { 476 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 477 }; 478 479 static const struct dcn10_stream_encoder_mask se_mask = { 480 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 481 }; 482 483 484 #define aux_regs(id)\ 485 [id] = {\ 486 DCN2_AUX_REG_LIST(id)\ 487 } 488 489 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 490 aux_regs(0), 491 aux_regs(1), 492 aux_regs(2), 493 aux_regs(3), 494 aux_regs(4) 495 }; 496 497 #define hpd_regs(id)\ 498 [id] = {\ 499 HPD_REG_LIST(id)\ 500 } 501 502 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 503 hpd_regs(0), 504 hpd_regs(1), 505 hpd_regs(2), 506 hpd_regs(3), 507 hpd_regs(4) 508 }; 509 510 #define link_regs(id, phyid)\ 511 [id] = {\ 512 LE_DCN31_REG_LIST(id), \ 513 UNIPHY_DCN2_REG_LIST(phyid), \ 514 /*DPCS_DCN31_REG_LIST(id),*/ \ 515 } 516 517 static const struct dcn10_link_enc_registers link_enc_regs[] = { 518 link_regs(0, A), 519 link_regs(1, B), 520 link_regs(2, C), 521 link_regs(3, D), 522 link_regs(4, E) 523 }; 524 525 static const struct dcn10_link_enc_shift le_shift = { 526 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 527 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 528 }; 529 530 static const struct dcn10_link_enc_mask le_mask = { 531 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 532 // DPCS_DCN31_MASK_SH_LIST(_MASK) 533 }; 534 535 #define hpo_dp_stream_encoder_reg_list(id)\ 536 [id] = {\ 537 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 538 } 539 540 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 541 hpo_dp_stream_encoder_reg_list(0), 542 hpo_dp_stream_encoder_reg_list(1), 543 hpo_dp_stream_encoder_reg_list(2), 544 hpo_dp_stream_encoder_reg_list(3), 545 }; 546 547 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 548 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 549 }; 550 551 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 552 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 553 }; 554 555 556 #define hpo_dp_link_encoder_reg_list(id)\ 557 [id] = {\ 558 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 559 /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ 560 /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ 561 /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ 562 /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ 563 /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ 564 } 565 566 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 567 hpo_dp_link_encoder_reg_list(0), 568 hpo_dp_link_encoder_reg_list(1), 569 }; 570 571 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 572 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 573 }; 574 575 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 576 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 577 }; 578 579 #define dpp_regs(id)\ 580 [id] = {\ 581 DPP_REG_LIST_DCN30_COMMON(id),\ 582 } 583 584 static const struct dcn3_dpp_registers dpp_regs[] = { 585 dpp_regs(0), 586 dpp_regs(1), 587 dpp_regs(2), 588 dpp_regs(3) 589 }; 590 591 static const struct dcn3_dpp_shift tf_shift = { 592 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 593 }; 594 595 static const struct dcn3_dpp_mask tf_mask = { 596 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 597 }; 598 599 600 #define opp_regs(id)\ 601 [id] = {\ 602 OPP_REG_LIST_DCN30(id),\ 603 } 604 605 static const struct dcn20_opp_registers opp_regs[] = { 606 opp_regs(0), 607 opp_regs(1), 608 opp_regs(2), 609 opp_regs(3) 610 }; 611 612 static const struct dcn20_opp_shift opp_shift = { 613 OPP_MASK_SH_LIST_DCN20(__SHIFT) 614 }; 615 616 static const struct dcn20_opp_mask opp_mask = { 617 OPP_MASK_SH_LIST_DCN20(_MASK) 618 }; 619 620 #define aux_engine_regs(id)\ 621 [id] = {\ 622 AUX_COMMON_REG_LIST0(id), \ 623 .AUXN_IMPCAL = 0, \ 624 .AUXP_IMPCAL = 0, \ 625 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 626 } 627 628 static const struct dce110_aux_registers aux_engine_regs[] = { 629 aux_engine_regs(0), 630 aux_engine_regs(1), 631 aux_engine_regs(2), 632 aux_engine_regs(3), 633 aux_engine_regs(4) 634 }; 635 636 static const struct dce110_aux_registers_shift aux_shift = { 637 DCN_AUX_MASK_SH_LIST(__SHIFT) 638 }; 639 640 static const struct dce110_aux_registers_mask aux_mask = { 641 DCN_AUX_MASK_SH_LIST(_MASK) 642 }; 643 644 645 #define dwbc_regs_dcn3(id)\ 646 [id] = {\ 647 DWBC_COMMON_REG_LIST_DCN30(id),\ 648 } 649 650 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 651 dwbc_regs_dcn3(0), 652 }; 653 654 static const struct dcn30_dwbc_shift dwbc30_shift = { 655 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 656 }; 657 658 static const struct dcn30_dwbc_mask dwbc30_mask = { 659 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 660 }; 661 662 #define mcif_wb_regs_dcn3(id)\ 663 [id] = {\ 664 MCIF_WB_COMMON_REG_LIST_DCN32(id),\ 665 } 666 667 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 668 mcif_wb_regs_dcn3(0) 669 }; 670 671 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 672 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 673 }; 674 675 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 676 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 677 }; 678 679 #define dsc_regsDCN20(id)\ 680 [id] = {\ 681 DSC_REG_LIST_DCN20(id)\ 682 } 683 684 static const struct dcn20_dsc_registers dsc_regs[] = { 685 dsc_regsDCN20(0), 686 dsc_regsDCN20(1), 687 dsc_regsDCN20(2), 688 dsc_regsDCN20(3) 689 }; 690 691 static const struct dcn20_dsc_shift dsc_shift = { 692 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 693 }; 694 695 static const struct dcn20_dsc_mask dsc_mask = { 696 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 697 }; 698 699 static const struct dcn30_mpc_registers mpc_regs = { 700 MPC_REG_LIST_DCN3_0(0), 701 MPC_REG_LIST_DCN3_0(1), 702 MPC_REG_LIST_DCN3_0(2), 703 MPC_REG_LIST_DCN3_0(3), 704 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 705 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 706 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 707 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 708 MPC_MCM_REG_LIST_DCN32(0), 709 MPC_MCM_REG_LIST_DCN32(1), 710 MPC_MCM_REG_LIST_DCN32(2), 711 MPC_MCM_REG_LIST_DCN32(3), 712 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 713 }; 714 715 static const struct dcn30_mpc_shift mpc_shift = { 716 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 717 }; 718 719 static const struct dcn30_mpc_mask mpc_mask = { 720 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 721 }; 722 723 #define optc_regs(id)\ 724 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} 725 726 static const struct dcn_optc_registers optc_regs[] = { 727 optc_regs(0), 728 optc_regs(1), 729 optc_regs(2), 730 optc_regs(3) 731 }; 732 733 static const struct dcn_optc_shift optc_shift = { 734 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 735 }; 736 737 static const struct dcn_optc_mask optc_mask = { 738 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 739 }; 740 741 #define hubp_regs(id)\ 742 [id] = {\ 743 HUBP_REG_LIST_DCN32(id)\ 744 } 745 746 static const struct dcn_hubp2_registers hubp_regs[] = { 747 hubp_regs(0), 748 hubp_regs(1), 749 hubp_regs(2), 750 hubp_regs(3) 751 }; 752 753 754 static const struct dcn_hubp2_shift hubp_shift = { 755 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 756 }; 757 758 static const struct dcn_hubp2_mask hubp_mask = { 759 HUBP_MASK_SH_LIST_DCN32(_MASK) 760 }; 761 static const struct dcn_hubbub_registers hubbub_reg = { 762 HUBBUB_REG_LIST_DCN32(0) 763 }; 764 765 static const struct dcn_hubbub_shift hubbub_shift = { 766 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 767 }; 768 769 static const struct dcn_hubbub_mask hubbub_mask = { 770 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 771 }; 772 773 static const struct dccg_registers dccg_regs = { 774 DCCG_REG_LIST_DCN32() 775 }; 776 777 static const struct dccg_shift dccg_shift = { 778 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 779 }; 780 781 static const struct dccg_mask dccg_mask = { 782 DCCG_MASK_SH_LIST_DCN32(_MASK) 783 }; 784 785 786 #define SRII2(reg_name_pre, reg_name_post, id)\ 787 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 788 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 789 reg ## reg_name_pre ## id ## _ ## reg_name_post 790 791 792 #define HWSEQ_DCN32_REG_LIST()\ 793 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 794 SR(DIO_MEM_PWR_CTRL), \ 795 SR(ODM_MEM_PWR_CTRL3), \ 796 SR(MMHUBBUB_MEM_PWR_CNTL), \ 797 SR(DCCG_GATE_DISABLE_CNTL), \ 798 SR(DCCG_GATE_DISABLE_CNTL2), \ 799 SR(DCFCLK_CNTL),\ 800 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 801 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 802 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 803 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 804 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 805 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 806 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 807 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 808 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 809 SR(MICROSECOND_TIME_BASE_DIV), \ 810 SR(MILLISECOND_TIME_BASE_DIV), \ 811 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 812 SR(RBBMIF_TIMEOUT_DIS), \ 813 SR(RBBMIF_TIMEOUT_DIS_2), \ 814 SR(DCHUBBUB_CRC_CTRL), \ 815 SR(DPP_TOP0_DPP_CRC_CTRL), \ 816 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 817 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 818 SR(MPC_CRC_CTRL), \ 819 SR(MPC_CRC_RESULT_GB), \ 820 SR(MPC_CRC_RESULT_C), \ 821 SR(MPC_CRC_RESULT_AR), \ 822 SR(DOMAIN0_PG_CONFIG), \ 823 SR(DOMAIN1_PG_CONFIG), \ 824 SR(DOMAIN2_PG_CONFIG), \ 825 SR(DOMAIN3_PG_CONFIG), \ 826 SR(DOMAIN16_PG_CONFIG), \ 827 SR(DOMAIN17_PG_CONFIG), \ 828 SR(DOMAIN18_PG_CONFIG), \ 829 SR(DOMAIN19_PG_CONFIG), \ 830 SR(DOMAIN0_PG_STATUS), \ 831 SR(DOMAIN1_PG_STATUS), \ 832 SR(DOMAIN2_PG_STATUS), \ 833 SR(DOMAIN3_PG_STATUS), \ 834 SR(DOMAIN16_PG_STATUS), \ 835 SR(DOMAIN17_PG_STATUS), \ 836 SR(DOMAIN18_PG_STATUS), \ 837 SR(DOMAIN19_PG_STATUS), \ 838 SR(D1VGA_CONTROL), \ 839 SR(D2VGA_CONTROL), \ 840 SR(D3VGA_CONTROL), \ 841 SR(D4VGA_CONTROL), \ 842 SR(D5VGA_CONTROL), \ 843 SR(D6VGA_CONTROL), \ 844 SR(DC_IP_REQUEST_CNTL), \ 845 SR(AZALIA_AUDIO_DTO), \ 846 SR(AZALIA_CONTROLLER_CLOCK_GATING) 847 848 static const struct dce_hwseq_registers hwseq_reg = { 849 HWSEQ_DCN32_REG_LIST() 850 }; 851 852 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 853 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 854 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 855 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 856 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 857 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 858 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 859 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 860 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 861 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 862 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 863 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 864 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 865 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 866 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 867 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 868 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 869 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 870 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 871 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 872 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 873 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 874 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 875 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 876 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 877 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 878 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 879 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 880 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 881 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 882 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 883 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 884 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 885 886 static const struct dce_hwseq_shift hwseq_shift = { 887 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 888 }; 889 890 static const struct dce_hwseq_mask hwseq_mask = { 891 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 892 }; 893 #define vmid_regs(id)\ 894 [id] = {\ 895 DCN20_VMID_REG_LIST(id)\ 896 } 897 898 static const struct dcn_vmid_registers vmid_regs[] = { 899 vmid_regs(0), 900 vmid_regs(1), 901 vmid_regs(2), 902 vmid_regs(3), 903 vmid_regs(4), 904 vmid_regs(5), 905 vmid_regs(6), 906 vmid_regs(7), 907 vmid_regs(8), 908 vmid_regs(9), 909 vmid_regs(10), 910 vmid_regs(11), 911 vmid_regs(12), 912 vmid_regs(13), 913 vmid_regs(14), 914 vmid_regs(15) 915 }; 916 917 static const struct dcn20_vmid_shift vmid_shifts = { 918 DCN20_VMID_MASK_SH_LIST(__SHIFT) 919 }; 920 921 static const struct dcn20_vmid_mask vmid_masks = { 922 DCN20_VMID_MASK_SH_LIST(_MASK) 923 }; 924 925 static const struct resource_caps res_cap_dcn321 = { 926 .num_timing_generator = 4, 927 .num_opp = 4, 928 .num_video_plane = 4, 929 .num_audio = 5, 930 .num_stream_encoder = 5, 931 .num_hpo_dp_stream_encoder = 4, 932 .num_hpo_dp_link_encoder = 2, 933 .num_pll = 5, 934 .num_dwb = 1, 935 .num_ddc = 5, 936 .num_vmid = 16, 937 .num_mpc_3dlut = 4, 938 .num_dsc = 4, 939 }; 940 941 static const struct dc_plane_cap plane_cap = { 942 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 943 .blends_with_above = true, 944 .blends_with_below = true, 945 .per_pixel_alpha = true, 946 947 .pixel_format_support = { 948 .argb8888 = true, 949 .nv12 = true, 950 .fp16 = true, 951 .p010 = true, 952 .ayuv = false, 953 }, 954 955 .max_upscale_factor = { 956 .argb8888 = 16000, 957 .nv12 = 16000, 958 .fp16 = 16000 959 }, 960 961 // 6:1 downscaling ratio: 1000/6 = 166.666 962 .max_downscale_factor = { 963 .argb8888 = 167, 964 .nv12 = 167, 965 .fp16 = 167 966 }, 967 64, 968 64 969 }; 970 971 static const struct dc_debug_options debug_defaults_drv = { 972 .disable_dmcu = true, 973 .force_abm_enable = false, 974 .timing_trace = false, 975 .clock_trace = true, 976 .disable_pplib_clock_request = false, 977 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 978 .force_single_disp_pipe_split = false, 979 .disable_dcc = DCC_ENABLE, 980 .vsr_support = true, 981 .performance_trace = false, 982 .max_downscale_src_width = 7680,/*upto 8K*/ 983 .disable_pplib_wm_range = false, 984 .scl_reset_length10 = true, 985 .sanity_checks = false, 986 .underflow_assert_delay_us = 0xFFFFFFFF, 987 .dwb_fi_phase = -1, // -1 = disable, 988 .dmub_command_table = true, 989 .enable_mem_low_power = { 990 .bits = { 991 .vga = false, 992 .i2c = false, 993 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 994 .dscl = false, 995 .cm = false, 996 .mpc = false, 997 .optc = true, 998 } 999 }, 1000 .use_max_lb = true, 1001 .force_disable_subvp = true 1002 }; 1003 1004 static const struct dc_debug_options debug_defaults_diags = { 1005 .disable_dmcu = true, 1006 .force_abm_enable = false, 1007 .timing_trace = true, 1008 .clock_trace = true, 1009 .disable_dpp_power_gate = true, 1010 .disable_hubp_power_gate = true, 1011 .disable_dsc_power_gate = true, 1012 .disable_clock_gate = true, 1013 .disable_pplib_clock_request = true, 1014 .disable_pplib_wm_range = true, 1015 .disable_stutter = false, 1016 .scl_reset_length10 = true, 1017 .dwb_fi_phase = -1, // -1 = disable 1018 .dmub_command_table = true, 1019 .enable_tri_buf = true, 1020 .use_max_lb = true, 1021 .force_disable_subvp = true 1022 }; 1023 1024 1025 static struct dce_aux *dcn321_aux_engine_create( 1026 struct dc_context *ctx, 1027 uint32_t inst) 1028 { 1029 struct aux_engine_dce110 *aux_engine = 1030 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1031 1032 if (!aux_engine) 1033 return NULL; 1034 1035 dce110_aux_engine_construct(aux_engine, ctx, inst, 1036 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1037 &aux_engine_regs[inst], 1038 &aux_mask, 1039 &aux_shift, 1040 ctx->dc->caps.extended_aux_timeout_support); 1041 1042 return &aux_engine->base; 1043 } 1044 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1045 1046 static const struct dce_i2c_registers i2c_hw_regs[] = { 1047 i2c_inst_regs(1), 1048 i2c_inst_regs(2), 1049 i2c_inst_regs(3), 1050 i2c_inst_regs(4), 1051 i2c_inst_regs(5), 1052 }; 1053 1054 static const struct dce_i2c_shift i2c_shifts = { 1055 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1056 }; 1057 1058 static const struct dce_i2c_mask i2c_masks = { 1059 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1060 }; 1061 1062 static struct dce_i2c_hw *dcn321_i2c_hw_create( 1063 struct dc_context *ctx, 1064 uint32_t inst) 1065 { 1066 struct dce_i2c_hw *dce_i2c_hw = 1067 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1068 1069 if (!dce_i2c_hw) 1070 return NULL; 1071 1072 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1073 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1074 1075 return dce_i2c_hw; 1076 } 1077 1078 static struct clock_source *dcn321_clock_source_create( 1079 struct dc_context *ctx, 1080 struct dc_bios *bios, 1081 enum clock_source_id id, 1082 const struct dce110_clk_src_regs *regs, 1083 bool dp_clk_src) 1084 { 1085 struct dce110_clk_src *clk_src = 1086 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1087 1088 if (!clk_src) 1089 return NULL; 1090 1091 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1092 regs, &cs_shift, &cs_mask)) { 1093 clk_src->base.dp_clk_src = dp_clk_src; 1094 return &clk_src->base; 1095 } 1096 1097 BREAK_TO_DEBUGGER(); 1098 return NULL; 1099 } 1100 1101 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 1102 { 1103 int i; 1104 1105 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 1106 GFP_KERNEL); 1107 1108 if (!hubbub2) 1109 return NULL; 1110 1111 hubbub32_construct(hubbub2, ctx, 1112 &hubbub_reg, 1113 &hubbub_shift, 1114 &hubbub_mask, 1115 ctx->dc->dml.ip.det_buffer_size_kbytes, 1116 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 1117 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 1118 1119 1120 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 1121 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 1122 1123 vmid->ctx = ctx; 1124 1125 vmid->regs = &vmid_regs[i]; 1126 vmid->shifts = &vmid_shifts; 1127 vmid->masks = &vmid_masks; 1128 } 1129 1130 return &hubbub2->base; 1131 } 1132 1133 static struct hubp *dcn321_hubp_create( 1134 struct dc_context *ctx, 1135 uint32_t inst) 1136 { 1137 struct dcn20_hubp *hubp2 = 1138 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1139 1140 if (!hubp2) 1141 return NULL; 1142 1143 if (hubp32_construct(hubp2, ctx, inst, 1144 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1145 return &hubp2->base; 1146 1147 BREAK_TO_DEBUGGER(); 1148 kfree(hubp2); 1149 return NULL; 1150 } 1151 1152 static void dcn321_dpp_destroy(struct dpp **dpp) 1153 { 1154 kfree(TO_DCN30_DPP(*dpp)); 1155 *dpp = NULL; 1156 } 1157 1158 static struct dpp *dcn321_dpp_create( 1159 struct dc_context *ctx, 1160 uint32_t inst) 1161 { 1162 struct dcn3_dpp *dpp3 = 1163 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1164 1165 if (!dpp3) 1166 return NULL; 1167 1168 if (dpp32_construct(dpp3, ctx, inst, 1169 &dpp_regs[inst], &tf_shift, &tf_mask)) 1170 return &dpp3->base; 1171 1172 BREAK_TO_DEBUGGER(); 1173 kfree(dpp3); 1174 return NULL; 1175 } 1176 1177 static struct mpc *dcn321_mpc_create( 1178 struct dc_context *ctx, 1179 int num_mpcc, 1180 int num_rmu) 1181 { 1182 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1183 GFP_KERNEL); 1184 1185 if (!mpc30) 1186 return NULL; 1187 1188 dcn32_mpc_construct(mpc30, ctx, 1189 &mpc_regs, 1190 &mpc_shift, 1191 &mpc_mask, 1192 num_mpcc, 1193 num_rmu); 1194 1195 return &mpc30->base; 1196 } 1197 1198 static struct output_pixel_processor *dcn321_opp_create( 1199 struct dc_context *ctx, uint32_t inst) 1200 { 1201 struct dcn20_opp *opp2 = 1202 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1203 1204 if (!opp2) { 1205 BREAK_TO_DEBUGGER(); 1206 return NULL; 1207 } 1208 1209 dcn20_opp_construct(opp2, ctx, inst, 1210 &opp_regs[inst], &opp_shift, &opp_mask); 1211 return &opp2->base; 1212 } 1213 1214 1215 static struct timing_generator *dcn321_timing_generator_create( 1216 struct dc_context *ctx, 1217 uint32_t instance) 1218 { 1219 struct optc *tgn10 = 1220 kzalloc(sizeof(struct optc), GFP_KERNEL); 1221 1222 if (!tgn10) 1223 return NULL; 1224 1225 tgn10->base.inst = instance; 1226 tgn10->base.ctx = ctx; 1227 1228 tgn10->tg_regs = &optc_regs[instance]; 1229 tgn10->tg_shift = &optc_shift; 1230 tgn10->tg_mask = &optc_mask; 1231 1232 dcn32_timing_generator_init(tgn10); 1233 1234 return &tgn10->base; 1235 } 1236 1237 static const struct encoder_feature_support link_enc_feature = { 1238 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1239 .max_hdmi_pixel_clock = 600000, 1240 .hdmi_ycbcr420_supported = true, 1241 .dp_ycbcr420_supported = true, 1242 .fec_supported = true, 1243 .flags.bits.IS_HBR2_CAPABLE = true, 1244 .flags.bits.IS_HBR3_CAPABLE = true, 1245 .flags.bits.IS_TPS3_CAPABLE = true, 1246 .flags.bits.IS_TPS4_CAPABLE = true 1247 }; 1248 1249 static struct link_encoder *dcn321_link_encoder_create( 1250 const struct encoder_init_data *enc_init_data) 1251 { 1252 struct dcn20_link_encoder *enc20 = 1253 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1254 1255 if (!enc20) 1256 return NULL; 1257 1258 dcn321_link_encoder_construct(enc20, 1259 enc_init_data, 1260 &link_enc_feature, 1261 &link_enc_regs[enc_init_data->transmitter], 1262 &link_enc_aux_regs[enc_init_data->channel - 1], 1263 &link_enc_hpd_regs[enc_init_data->hpd_source], 1264 &le_shift, 1265 &le_mask); 1266 1267 return &enc20->enc10.base; 1268 } 1269 1270 static void read_dce_straps( 1271 struct dc_context *ctx, 1272 struct resource_straps *straps) 1273 { 1274 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1275 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1276 1277 } 1278 1279 static struct audio *dcn321_create_audio( 1280 struct dc_context *ctx, unsigned int inst) 1281 { 1282 return dce_audio_create(ctx, inst, 1283 &audio_regs[inst], &audio_shift, &audio_mask); 1284 } 1285 1286 static struct vpg *dcn321_vpg_create( 1287 struct dc_context *ctx, 1288 uint32_t inst) 1289 { 1290 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1291 1292 if (!vpg3) 1293 return NULL; 1294 1295 vpg3_construct(vpg3, ctx, inst, 1296 &vpg_regs[inst], 1297 &vpg_shift, 1298 &vpg_mask); 1299 1300 return &vpg3->base; 1301 } 1302 1303 static struct afmt *dcn321_afmt_create( 1304 struct dc_context *ctx, 1305 uint32_t inst) 1306 { 1307 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1308 1309 if (!afmt3) 1310 return NULL; 1311 1312 afmt3_construct(afmt3, ctx, inst, 1313 &afmt_regs[inst], 1314 &afmt_shift, 1315 &afmt_mask); 1316 1317 return &afmt3->base; 1318 } 1319 1320 static struct apg *dcn321_apg_create( 1321 struct dc_context *ctx, 1322 uint32_t inst) 1323 { 1324 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1325 1326 if (!apg31) 1327 return NULL; 1328 1329 apg31_construct(apg31, ctx, inst, 1330 &apg_regs[inst], 1331 &apg_shift, 1332 &apg_mask); 1333 1334 return &apg31->base; 1335 } 1336 1337 static struct stream_encoder *dcn321_stream_encoder_create( 1338 enum engine_id eng_id, 1339 struct dc_context *ctx) 1340 { 1341 struct dcn10_stream_encoder *enc1; 1342 struct vpg *vpg; 1343 struct afmt *afmt; 1344 int vpg_inst; 1345 int afmt_inst; 1346 1347 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1348 if (eng_id <= ENGINE_ID_DIGF) { 1349 vpg_inst = eng_id; 1350 afmt_inst = eng_id; 1351 } else 1352 return NULL; 1353 1354 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1355 vpg = dcn321_vpg_create(ctx, vpg_inst); 1356 afmt = dcn321_afmt_create(ctx, afmt_inst); 1357 1358 if (!enc1 || !vpg || !afmt) { 1359 kfree(enc1); 1360 kfree(vpg); 1361 kfree(afmt); 1362 return NULL; 1363 } 1364 1365 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1366 eng_id, vpg, afmt, 1367 &stream_enc_regs[eng_id], 1368 &se_shift, &se_mask); 1369 1370 return &enc1->base; 1371 } 1372 1373 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1374 enum engine_id eng_id, 1375 struct dc_context *ctx) 1376 { 1377 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1378 struct vpg *vpg; 1379 struct apg *apg; 1380 uint32_t hpo_dp_inst; 1381 uint32_t vpg_inst; 1382 uint32_t apg_inst; 1383 1384 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1385 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1386 1387 /* Mapping of VPG register blocks to HPO DP block instance: 1388 * VPG[6] -> HPO_DP[0] 1389 * VPG[7] -> HPO_DP[1] 1390 * VPG[8] -> HPO_DP[2] 1391 * VPG[9] -> HPO_DP[3] 1392 */ 1393 vpg_inst = hpo_dp_inst + 6; 1394 1395 /* Mapping of APG register blocks to HPO DP block instance: 1396 * APG[0] -> HPO_DP[0] 1397 * APG[1] -> HPO_DP[1] 1398 * APG[2] -> HPO_DP[2] 1399 * APG[3] -> HPO_DP[3] 1400 */ 1401 apg_inst = hpo_dp_inst; 1402 1403 /* allocate HPO stream encoder and create VPG sub-block */ 1404 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1405 vpg = dcn321_vpg_create(ctx, vpg_inst); 1406 apg = dcn321_apg_create(ctx, apg_inst); 1407 1408 if (!hpo_dp_enc31 || !vpg || !apg) { 1409 kfree(hpo_dp_enc31); 1410 kfree(vpg); 1411 kfree(apg); 1412 return NULL; 1413 } 1414 1415 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1416 hpo_dp_inst, eng_id, vpg, apg, 1417 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1418 &hpo_dp_se_shift, &hpo_dp_se_mask); 1419 1420 return &hpo_dp_enc31->base; 1421 } 1422 1423 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1424 uint8_t inst, 1425 struct dc_context *ctx) 1426 { 1427 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1428 1429 /* allocate HPO link encoder */ 1430 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1431 1432 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1433 &hpo_dp_link_enc_regs[inst], 1434 &hpo_dp_le_shift, &hpo_dp_le_mask); 1435 1436 return &hpo_dp_enc31->base; 1437 } 1438 1439 static struct dce_hwseq *dcn321_hwseq_create( 1440 struct dc_context *ctx) 1441 { 1442 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1443 1444 if (hws) { 1445 hws->ctx = ctx; 1446 hws->regs = &hwseq_reg; 1447 hws->shifts = &hwseq_shift; 1448 hws->masks = &hwseq_mask; 1449 } 1450 return hws; 1451 } 1452 static const struct resource_create_funcs res_create_funcs = { 1453 .read_dce_straps = read_dce_straps, 1454 .create_audio = dcn321_create_audio, 1455 .create_stream_encoder = dcn321_stream_encoder_create, 1456 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1457 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1458 .create_hwseq = dcn321_hwseq_create, 1459 }; 1460 1461 static const struct resource_create_funcs res_create_maximus_funcs = { 1462 .read_dce_straps = NULL, 1463 .create_audio = NULL, 1464 .create_stream_encoder = NULL, 1465 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1466 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1467 .create_hwseq = dcn321_hwseq_create, 1468 }; 1469 1470 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1471 { 1472 unsigned int i; 1473 1474 for (i = 0; i < pool->base.stream_enc_count; i++) { 1475 if (pool->base.stream_enc[i] != NULL) { 1476 if (pool->base.stream_enc[i]->vpg != NULL) { 1477 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1478 pool->base.stream_enc[i]->vpg = NULL; 1479 } 1480 if (pool->base.stream_enc[i]->afmt != NULL) { 1481 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1482 pool->base.stream_enc[i]->afmt = NULL; 1483 } 1484 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1485 pool->base.stream_enc[i] = NULL; 1486 } 1487 } 1488 1489 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1490 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1491 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1492 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1493 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1494 } 1495 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1496 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1497 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1498 } 1499 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1500 pool->base.hpo_dp_stream_enc[i] = NULL; 1501 } 1502 } 1503 1504 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1505 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1506 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1507 pool->base.hpo_dp_link_enc[i] = NULL; 1508 } 1509 } 1510 1511 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1512 if (pool->base.dscs[i] != NULL) 1513 dcn20_dsc_destroy(&pool->base.dscs[i]); 1514 } 1515 1516 if (pool->base.mpc != NULL) { 1517 kfree(TO_DCN20_MPC(pool->base.mpc)); 1518 pool->base.mpc = NULL; 1519 } 1520 if (pool->base.hubbub != NULL) { 1521 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1522 pool->base.hubbub = NULL; 1523 } 1524 for (i = 0; i < pool->base.pipe_count; i++) { 1525 if (pool->base.dpps[i] != NULL) 1526 dcn321_dpp_destroy(&pool->base.dpps[i]); 1527 1528 if (pool->base.ipps[i] != NULL) 1529 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1530 1531 if (pool->base.hubps[i] != NULL) { 1532 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1533 pool->base.hubps[i] = NULL; 1534 } 1535 1536 if (pool->base.irqs != NULL) 1537 dal_irq_service_destroy(&pool->base.irqs); 1538 } 1539 1540 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1541 if (pool->base.engines[i] != NULL) 1542 dce110_engine_destroy(&pool->base.engines[i]); 1543 if (pool->base.hw_i2cs[i] != NULL) { 1544 kfree(pool->base.hw_i2cs[i]); 1545 pool->base.hw_i2cs[i] = NULL; 1546 } 1547 if (pool->base.sw_i2cs[i] != NULL) { 1548 kfree(pool->base.sw_i2cs[i]); 1549 pool->base.sw_i2cs[i] = NULL; 1550 } 1551 } 1552 1553 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1554 if (pool->base.opps[i] != NULL) 1555 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1556 } 1557 1558 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1559 if (pool->base.timing_generators[i] != NULL) { 1560 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1561 pool->base.timing_generators[i] = NULL; 1562 } 1563 } 1564 1565 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1566 if (pool->base.dwbc[i] != NULL) { 1567 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1568 pool->base.dwbc[i] = NULL; 1569 } 1570 if (pool->base.mcif_wb[i] != NULL) { 1571 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1572 pool->base.mcif_wb[i] = NULL; 1573 } 1574 } 1575 1576 for (i = 0; i < pool->base.audio_count; i++) { 1577 if (pool->base.audios[i]) 1578 dce_aud_destroy(&pool->base.audios[i]); 1579 } 1580 1581 for (i = 0; i < pool->base.clk_src_count; i++) { 1582 if (pool->base.clock_sources[i] != NULL) { 1583 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1584 pool->base.clock_sources[i] = NULL; 1585 } 1586 } 1587 1588 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1589 if (pool->base.mpc_lut[i] != NULL) { 1590 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1591 pool->base.mpc_lut[i] = NULL; 1592 } 1593 if (pool->base.mpc_shaper[i] != NULL) { 1594 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1595 pool->base.mpc_shaper[i] = NULL; 1596 } 1597 } 1598 1599 if (pool->base.dp_clock_source != NULL) { 1600 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1601 pool->base.dp_clock_source = NULL; 1602 } 1603 1604 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1605 if (pool->base.multiple_abms[i] != NULL) 1606 dce_abm_destroy(&pool->base.multiple_abms[i]); 1607 } 1608 1609 if (pool->base.psr != NULL) 1610 dmub_psr_destroy(&pool->base.psr); 1611 1612 if (pool->base.dccg != NULL) 1613 dcn_dccg_destroy(&pool->base.dccg); 1614 1615 if (pool->base.oem_device != NULL) 1616 dal_ddc_service_destroy(&pool->base.oem_device); 1617 } 1618 1619 1620 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1621 { 1622 int i; 1623 uint32_t dwb_count = pool->res_cap->num_dwb; 1624 1625 for (i = 0; i < dwb_count; i++) { 1626 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1627 GFP_KERNEL); 1628 1629 if (!dwbc30) { 1630 dm_error("DC: failed to create dwbc30!\n"); 1631 return false; 1632 } 1633 1634 dcn30_dwbc_construct(dwbc30, ctx, 1635 &dwbc30_regs[i], 1636 &dwbc30_shift, 1637 &dwbc30_mask, 1638 i); 1639 1640 pool->dwbc[i] = &dwbc30->base; 1641 } 1642 return true; 1643 } 1644 1645 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1646 { 1647 int i; 1648 uint32_t dwb_count = pool->res_cap->num_dwb; 1649 1650 for (i = 0; i < dwb_count; i++) { 1651 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1652 GFP_KERNEL); 1653 1654 if (!mcif_wb30) { 1655 dm_error("DC: failed to create mcif_wb30!\n"); 1656 return false; 1657 } 1658 1659 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1660 &mcif_wb30_regs[i], 1661 &mcif_wb30_shift, 1662 &mcif_wb30_mask, 1663 i); 1664 1665 pool->mcif_wb[i] = &mcif_wb30->base; 1666 } 1667 return true; 1668 } 1669 1670 static struct display_stream_compressor *dcn321_dsc_create( 1671 struct dc_context *ctx, uint32_t inst) 1672 { 1673 struct dcn20_dsc *dsc = 1674 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1675 1676 if (!dsc) { 1677 BREAK_TO_DEBUGGER(); 1678 return NULL; 1679 } 1680 1681 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1682 1683 dsc->max_image_width = 6016; 1684 1685 return &dsc->base; 1686 } 1687 1688 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1689 { 1690 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1691 1692 dcn321_resource_destruct(dcn321_pool); 1693 kfree(dcn321_pool); 1694 *pool = NULL; 1695 } 1696 1697 static struct dc_cap_funcs cap_funcs = { 1698 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1699 }; 1700 1701 1702 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1703 unsigned int *optimal_dcfclk, 1704 unsigned int *optimal_fclk) 1705 { 1706 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1707 1708 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * 1709 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); 1710 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * 1711 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); 1712 1713 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1714 1715 if (optimal_fclk) 1716 *optimal_fclk = bw_from_dram / 1717 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1718 1719 if (optimal_dcfclk) 1720 *optimal_dcfclk = bw_from_dram / 1721 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1722 } 1723 1724 /* dcn321_update_bw_bounding_box 1725 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet 1726 * with actual values as per dGPU SKU: 1727 * -with passed few options from dc->config 1728 * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) 1729 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes 1730 * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU 1731 * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) 1732 * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different 1733 * clocks (which might differ for certain dGPU SKU of the same ASIC) 1734 */ 1735 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1736 { 1737 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1738 /* Overrides from dc->config options */ 1739 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1740 1741 /* Override from passed dc->bb_overrides if available*/ 1742 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 1743 && dc->bb_overrides.sr_exit_time_ns) { 1744 dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 1745 } 1746 1747 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) 1748 != dc->bb_overrides.sr_enter_plus_exit_time_ns 1749 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1750 dcn3_21_soc.sr_enter_plus_exit_time_us = 1751 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1752 } 1753 1754 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 1755 && dc->bb_overrides.urgent_latency_ns) { 1756 dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1757 } 1758 1759 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) 1760 != dc->bb_overrides.dram_clock_change_latency_ns 1761 && dc->bb_overrides.dram_clock_change_latency_ns) { 1762 dcn3_21_soc.dram_clock_change_latency_us = 1763 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1764 } 1765 1766 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) 1767 != dc->bb_overrides.dummy_clock_change_latency_ns 1768 && dc->bb_overrides.dummy_clock_change_latency_ns) { 1769 dcn3_21_soc.dummy_pstate_latency_us = 1770 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 1771 } 1772 1773 /* Override from VBIOS if VBIOS bb_info available */ 1774 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1775 struct bp_soc_bb_info bb_info = {0}; 1776 1777 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1778 if (bb_info.dram_clock_change_latency_100ns > 0) 1779 dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 1780 1781 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1782 dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 1783 1784 if (bb_info.dram_sr_exit_latency_100ns > 0) 1785 dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 1786 } 1787 } 1788 1789 /* Override from VBIOS for num_chan */ 1790 if (dc->ctx->dc_bios->vram_info.num_chans) 1791 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1792 1793 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1794 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1795 1796 } 1797 1798 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 1799 dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1800 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1801 1802 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 1803 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 1804 unsigned int i = 0, j = 0, num_states = 0; 1805 1806 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1807 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1808 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1809 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1810 1811 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; 1812 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 1813 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1814 1815 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1816 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1817 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1818 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1819 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1820 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1821 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1822 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1823 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1824 } 1825 if (!max_dcfclk_mhz) 1826 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; 1827 if (!max_dispclk_mhz) 1828 max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; 1829 if (!max_dppclk_mhz) 1830 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; 1831 if (!max_phyclk_mhz) 1832 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 1833 1834 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1835 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 1836 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1837 num_dcfclk_sta_targets++; 1838 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1839 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 1840 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1841 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1842 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1843 break; 1844 } 1845 } 1846 // Update size of array since we "removed" duplicates 1847 num_dcfclk_sta_targets = i + 1; 1848 } 1849 1850 num_uclk_states = bw_params->clk_table.num_entries; 1851 1852 // Calculate optimal dcfclk for each uclk 1853 for (i = 0; i < num_uclk_states; i++) { 1854 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1855 &optimal_dcfclk_for_uclk[i], NULL); 1856 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 1857 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1858 } 1859 } 1860 1861 // Calculate optimal uclk for each dcfclk sta target 1862 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1863 for (j = 0; j < num_uclk_states; j++) { 1864 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1865 optimal_uclk_for_dcfclk_sta_targets[i] = 1866 bw_params->clk_table.entries[j].memclk_mhz * 16; 1867 break; 1868 } 1869 } 1870 } 1871 1872 i = 0; 1873 j = 0; 1874 // create the final dcfclk and uclk table 1875 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1876 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1877 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1878 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1879 } else { 1880 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1881 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1882 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1883 } else { 1884 j = num_uclk_states; 1885 } 1886 } 1887 } 1888 1889 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1890 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1891 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1892 } 1893 1894 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1895 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1896 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1897 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1898 } 1899 1900 dcn3_21_soc.num_states = num_states; 1901 for (i = 0; i < dcn3_21_soc.num_states; i++) { 1902 dcn3_21_soc.clock_limits[i].state = i; 1903 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1904 dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1905 1906 /* Fill all states with max values of all these clocks */ 1907 dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1908 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1909 dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1910 dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 1911 1912 /* Populate from bw_params for DTBCLK, SOCCLK */ 1913 if (i > 0) { 1914 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 1915 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; 1916 } else { 1917 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 1918 } 1919 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 1920 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 1921 } 1922 1923 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 1924 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; 1925 else 1926 dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 1927 1928 if (!dram_speed_mts[i] && i > 0) 1929 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; 1930 else 1931 dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1932 1933 /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ 1934 /* PHYCLK_D18, PHYCLK_D32 */ 1935 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 1936 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 1937 } 1938 1939 /* Re-init DML with updated bb */ 1940 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1941 if (dc->current_state) 1942 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1943 } 1944 } 1945 1946 static struct resource_funcs dcn321_res_pool_funcs = { 1947 .destroy = dcn321_destroy_resource_pool, 1948 .link_enc_create = dcn321_link_encoder_create, 1949 .link_enc_create_minimal = NULL, 1950 .panel_cntl_create = dcn32_panel_cntl_create, 1951 .validate_bandwidth = dcn32_validate_bandwidth, 1952 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1953 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1954 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1955 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1956 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1957 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1958 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1959 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1960 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1961 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1962 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1963 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1964 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1965 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1966 .add_phantom_pipes = dcn32_add_phantom_pipes, 1967 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1968 }; 1969 1970 1971 static bool dcn321_resource_construct( 1972 uint8_t num_virtual_links, 1973 struct dc *dc, 1974 struct dcn321_resource_pool *pool) 1975 { 1976 int i, j; 1977 struct dc_context *ctx = dc->ctx; 1978 struct irq_service_init_data init_data; 1979 struct ddc_service_init_data ddc_init_data = {0}; 1980 uint32_t pipe_fuses = 0; 1981 uint32_t num_pipes = 4; 1982 1983 ctx->dc_bios->regs = &bios_regs; 1984 1985 pool->base.res_cap = &res_cap_dcn321; 1986 /* max number of pipes for ASIC before checking for pipe fuses */ 1987 num_pipes = pool->base.res_cap->num_timing_generator; 1988 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1989 1990 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1991 if (pipe_fuses & 1 << i) 1992 num_pipes--; 1993 1994 if (pipe_fuses & 1) 1995 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1996 1997 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1998 ASSERT(0); //Entire DCN is harvested! 1999 2000 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2001 * value will be changed, update max_num_dpp and max_num_otg for dml. 2002 */ 2003 dcn3_21_ip.max_num_dpp = num_pipes; 2004 dcn3_21_ip.max_num_otg = num_pipes; 2005 2006 pool->base.funcs = &dcn321_res_pool_funcs; 2007 2008 /************************************************* 2009 * Resource + asic cap harcoding * 2010 *************************************************/ 2011 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2012 pool->base.timing_generator_count = num_pipes; 2013 pool->base.pipe_count = num_pipes; 2014 pool->base.mpcc_count = num_pipes; 2015 dc->caps.max_downscale_ratio = 600; 2016 dc->caps.i2c_speed_in_khz = 100; 2017 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2018 dc->caps.max_cursor_size = 256; 2019 dc->caps.min_horizontal_blanking_period = 80; 2020 dc->caps.dmdata_alloc_size = 2048; 2021 dc->caps.mall_size_per_mem_channel = 0; 2022 dc->caps.mall_size_total = 0; 2023 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2024 dc->caps.cache_line_size = 64; 2025 dc->caps.cache_num_ways = 16; 2026 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 2027 dc->caps.subvp_fw_processing_delay_us = 15; 2028 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2029 dc->caps.subvp_pstate_allow_width_us = 20; 2030 2031 dc->caps.max_slave_planes = 1; 2032 dc->caps.max_slave_yuv_planes = 1; 2033 dc->caps.max_slave_rgb_planes = 1; 2034 dc->caps.post_blend_color_processing = true; 2035 dc->caps.force_dp_tps4_for_cp2520 = true; 2036 dc->caps.dp_hpo = true; 2037 dc->caps.edp_dsc_support = true; 2038 dc->caps.extended_aux_timeout_support = true; 2039 dc->caps.dmcub_support = true; 2040 2041 /* Color pipeline capabilities */ 2042 dc->caps.color.dpp.dcn_arch = 1; 2043 dc->caps.color.dpp.input_lut_shared = 0; 2044 dc->caps.color.dpp.icsc = 1; 2045 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2046 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2047 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2048 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2049 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2050 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2051 dc->caps.color.dpp.post_csc = 1; 2052 dc->caps.color.dpp.gamma_corr = 1; 2053 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2054 2055 dc->caps.color.dpp.hw_3d_lut = 0; //3DLUT removed from DPP 2056 dc->caps.color.dpp.ogam_ram = 0; //Blnd Gam also removed 2057 // no OGAM ROM on DCN2 and later ASICs 2058 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2059 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2060 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2061 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2062 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2063 dc->caps.color.dpp.ocsc = 0; 2064 2065 dc->caps.color.mpc.gamut_remap = 1; 2066 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2067 dc->caps.color.mpc.ogam_ram = 1; 2068 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2069 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2070 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2071 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2072 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2073 dc->caps.color.mpc.ocsc = 1; 2074 2075 /* read VBIOS LTTPR caps */ 2076 { 2077 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2078 enum bp_result bp_query_result; 2079 uint8_t is_vbios_lttpr_enable = 0; 2080 2081 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2082 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2083 } 2084 2085 /* interop bit is implicit */ 2086 { 2087 dc->caps.vbios_lttpr_aware = true; 2088 } 2089 } 2090 2091 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2092 dc->debug = debug_defaults_drv; 2093 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2094 dc->debug = debug_defaults_diags; 2095 } else 2096 dc->debug = debug_defaults_diags; 2097 // Init the vm_helper 2098 if (dc->vm_helper) 2099 vm_helper_init(dc->vm_helper, 16); 2100 2101 /************************************************* 2102 * Create resources * 2103 *************************************************/ 2104 2105 /* Clock Sources for Pixel Clock*/ 2106 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 2107 dcn321_clock_source_create(ctx, ctx->dc_bios, 2108 CLOCK_SOURCE_COMBO_PHY_PLL0, 2109 &clk_src_regs[0], false); 2110 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 2111 dcn321_clock_source_create(ctx, ctx->dc_bios, 2112 CLOCK_SOURCE_COMBO_PHY_PLL1, 2113 &clk_src_regs[1], false); 2114 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 2115 dcn321_clock_source_create(ctx, ctx->dc_bios, 2116 CLOCK_SOURCE_COMBO_PHY_PLL2, 2117 &clk_src_regs[2], false); 2118 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 2119 dcn321_clock_source_create(ctx, ctx->dc_bios, 2120 CLOCK_SOURCE_COMBO_PHY_PLL3, 2121 &clk_src_regs[3], false); 2122 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 2123 dcn321_clock_source_create(ctx, ctx->dc_bios, 2124 CLOCK_SOURCE_COMBO_PHY_PLL4, 2125 &clk_src_regs[4], false); 2126 2127 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 2128 2129 /* todo: not reuse phy_pll registers */ 2130 pool->base.dp_clock_source = 2131 dcn321_clock_source_create(ctx, ctx->dc_bios, 2132 CLOCK_SOURCE_ID_DP_DTO, 2133 &clk_src_regs[0], true); 2134 2135 for (i = 0; i < pool->base.clk_src_count; i++) { 2136 if (pool->base.clock_sources[i] == NULL) { 2137 dm_error("DC: failed to create clock sources!\n"); 2138 BREAK_TO_DEBUGGER(); 2139 goto create_fail; 2140 } 2141 } 2142 2143 /* DCCG */ 2144 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2145 if (pool->base.dccg == NULL) { 2146 dm_error("DC: failed to create dccg!\n"); 2147 BREAK_TO_DEBUGGER(); 2148 goto create_fail; 2149 } 2150 2151 /* DML */ 2152 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2153 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 2154 2155 /* IRQ Service */ 2156 init_data.ctx = dc->ctx; 2157 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2158 if (!pool->base.irqs) 2159 goto create_fail; 2160 2161 /* HUBBUB */ 2162 pool->base.hubbub = dcn321_hubbub_create(ctx); 2163 if (pool->base.hubbub == NULL) { 2164 BREAK_TO_DEBUGGER(); 2165 dm_error("DC: failed to create hubbub!\n"); 2166 goto create_fail; 2167 } 2168 2169 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2170 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2171 2172 /* if pipe is disabled, skip instance of HW pipe, 2173 * i.e, skip ASIC register instance 2174 */ 2175 if (pipe_fuses & 1 << i) 2176 continue; 2177 2178 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 2179 if (pool->base.hubps[j] == NULL) { 2180 BREAK_TO_DEBUGGER(); 2181 dm_error( 2182 "DC: failed to create hubps!\n"); 2183 goto create_fail; 2184 } 2185 2186 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 2187 if (pool->base.dpps[j] == NULL) { 2188 BREAK_TO_DEBUGGER(); 2189 dm_error( 2190 "DC: failed to create dpps!\n"); 2191 goto create_fail; 2192 } 2193 2194 pool->base.opps[j] = dcn321_opp_create(ctx, i); 2195 if (pool->base.opps[j] == NULL) { 2196 BREAK_TO_DEBUGGER(); 2197 dm_error( 2198 "DC: failed to create output pixel processor!\n"); 2199 goto create_fail; 2200 } 2201 2202 pool->base.timing_generators[j] = dcn321_timing_generator_create( 2203 ctx, i); 2204 if (pool->base.timing_generators[j] == NULL) { 2205 BREAK_TO_DEBUGGER(); 2206 dm_error("DC: failed to create tg!\n"); 2207 goto create_fail; 2208 } 2209 2210 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2211 &abm_regs[i], 2212 &abm_shift, 2213 &abm_mask); 2214 if (pool->base.multiple_abms[j] == NULL) { 2215 dm_error("DC: failed to create abm for pipe %d!\n", i); 2216 BREAK_TO_DEBUGGER(); 2217 goto create_fail; 2218 } 2219 2220 /* index for resource pool arrays for next valid pipe */ 2221 j++; 2222 } 2223 2224 /* PSR */ 2225 pool->base.psr = dmub_psr_create(ctx); 2226 if (pool->base.psr == NULL) { 2227 dm_error("DC: failed to create psr obj!\n"); 2228 BREAK_TO_DEBUGGER(); 2229 goto create_fail; 2230 } 2231 2232 /* MPCCs */ 2233 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2234 if (pool->base.mpc == NULL) { 2235 BREAK_TO_DEBUGGER(); 2236 dm_error("DC: failed to create mpc!\n"); 2237 goto create_fail; 2238 } 2239 2240 /* DSCs */ 2241 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2242 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 2243 if (pool->base.dscs[i] == NULL) { 2244 BREAK_TO_DEBUGGER(); 2245 dm_error("DC: failed to create display stream compressor %d!\n", i); 2246 goto create_fail; 2247 } 2248 } 2249 2250 /* DWB */ 2251 if (!dcn321_dwbc_create(ctx, &pool->base)) { 2252 BREAK_TO_DEBUGGER(); 2253 dm_error("DC: failed to create dwbc!\n"); 2254 goto create_fail; 2255 } 2256 2257 /* MMHUBBUB */ 2258 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 2259 BREAK_TO_DEBUGGER(); 2260 dm_error("DC: failed to create mcif_wb!\n"); 2261 goto create_fail; 2262 } 2263 2264 /* AUX and I2C */ 2265 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2266 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 2267 if (pool->base.engines[i] == NULL) { 2268 BREAK_TO_DEBUGGER(); 2269 dm_error( 2270 "DC:failed to create aux engine!!\n"); 2271 goto create_fail; 2272 } 2273 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 2274 if (pool->base.hw_i2cs[i] == NULL) { 2275 BREAK_TO_DEBUGGER(); 2276 dm_error( 2277 "DC:failed to create hw i2c!!\n"); 2278 goto create_fail; 2279 } 2280 pool->base.sw_i2cs[i] = NULL; 2281 } 2282 2283 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2284 if (!resource_construct(num_virtual_links, dc, &pool->base, 2285 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2286 &res_create_funcs : &res_create_maximus_funcs))) 2287 goto create_fail; 2288 2289 /* HW Sequencer init functions and Plane caps */ 2290 dcn32_hw_sequencer_init_functions(dc); 2291 2292 dc->caps.max_planes = pool->base.pipe_count; 2293 2294 for (i = 0; i < dc->caps.max_planes; ++i) 2295 dc->caps.planes[i] = plane_cap; 2296 2297 dc->cap_funcs = cap_funcs; 2298 2299 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2300 ddc_init_data.ctx = dc->ctx; 2301 ddc_init_data.link = NULL; 2302 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2303 ddc_init_data.id.enum_id = 0; 2304 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2305 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2306 } else { 2307 pool->base.oem_device = NULL; 2308 } 2309 2310 return true; 2311 2312 create_fail: 2313 2314 dcn321_resource_destruct(pool); 2315 2316 return false; 2317 } 2318 2319 struct resource_pool *dcn321_create_resource_pool( 2320 const struct dc_init_data *init_data, 2321 struct dc *dc) 2322 { 2323 struct dcn321_resource_pool *pool = 2324 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2325 2326 if (!pool) 2327 return NULL; 2328 2329 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2330 return &pool->base; 2331 2332 BREAK_TO_DEBUGGER(); 2333 kfree(pool); 2334 return NULL; 2335 } 2336