1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dcn31/dcn31_apg.h" 64 #include "dcn31/dcn31_dio_link_encoder.h" 65 #include "dcn32/dcn32_dio_link_encoder.h" 66 #include "dcn321_dio_link_encoder.h" 67 #include "dce/dce_clock_source.h" 68 #include "dce/dce_audio.h" 69 #include "dce/dce_hwseq.h" 70 #include "clk_mgr.h" 71 #include "virtual/virtual_stream_encoder.h" 72 #include "dml/display_mode_vba.h" 73 #include "dcn32/dcn32_dccg.h" 74 #include "dcn10/dcn10_resource.h" 75 #include "link.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 78 #include "dcn30/dcn30_dwb.h" 79 #include "dcn32/dcn32_mmhubbub.h" 80 81 #include "dcn/dcn_3_2_1_offset.h" 82 #include "dcn/dcn_3_2_1_sh_mask.h" 83 #include "nbio/nbio_4_3_0_offset.h" 84 85 #include "reg_helper.h" 86 #include "dce/dmub_abm.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dce_aux.h" 89 #include "dce/dce_i2c.h" 90 91 #include "dml/dcn30/display_mode_vba_30.h" 92 #include "vm_helper.h" 93 #include "dcn20/dcn20_vmid.h" 94 95 #define DC_LOGGER_INIT(logger) 96 97 enum dcn321_clk_src_array_id { 98 DCN321_CLK_SRC_PLL0, 99 DCN321_CLK_SRC_PLL1, 100 DCN321_CLK_SRC_PLL2, 101 DCN321_CLK_SRC_PLL3, 102 DCN321_CLK_SRC_PLL4, 103 DCN321_CLK_SRC_TOTAL 104 }; 105 106 /* begin ********************* 107 * macros to expend register list macro defined in HW object header file 108 */ 109 110 /* DCN */ 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id)\ 119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR_INIT(reg_name, id, value)\ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 175 .field_name = reg_name ## __ ## field_name ## post_fix 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 183 184 #define NBIO_BASE(seg) \ 185 NBIO_BASE_INNER(seg) 186 187 #define NBIO_SR(reg_name)\ 188 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 #define NBIO_SR_ARR(reg_name, id)\ 191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 192 regBIF_BX0_ ## reg_name 193 194 #define CTX ctx 195 #define REG(reg_name) \ 196 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 197 198 static struct bios_registers bios_regs; 199 200 #define bios_regs_init() \ 201 ( \ 202 NBIO_SR(BIOS_SCRATCH_3),\ 203 NBIO_SR(BIOS_SCRATCH_6)\ 204 ) 205 206 #define clk_src_regs_init(index, pllid)\ 207 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 208 209 static struct dce110_clk_src_regs clk_src_regs[5]; 210 211 static const struct dce110_clk_src_shift cs_shift = { 212 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 213 }; 214 215 static const struct dce110_clk_src_mask cs_mask = { 216 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 217 }; 218 219 #define abm_regs_init(id)\ 220 ABM_DCN32_REG_LIST_RI(id) 221 222 static struct dce_abm_registers abm_regs[4]; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN32(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN32(_MASK) 230 }; 231 232 #define audio_regs_init(id)\ 233 AUD_COMMON_REG_LIST_RI(id) 234 235 static struct dce_audio_registers audio_regs[5]; 236 237 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 238 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 240 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 241 242 static const struct dce_audio_shift audio_shift = { 243 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 244 }; 245 246 static const struct dce_audio_mask audio_mask = { 247 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 248 }; 249 250 #define vpg_regs_init(id)\ 251 VPG_DCN3_REG_LIST_RI(id) 252 253 static struct dcn30_vpg_registers vpg_regs[10]; 254 255 static const struct dcn30_vpg_shift vpg_shift = { 256 DCN3_VPG_MASK_SH_LIST(__SHIFT) 257 }; 258 259 static const struct dcn30_vpg_mask vpg_mask = { 260 DCN3_VPG_MASK_SH_LIST(_MASK) 261 }; 262 263 #define afmt_regs_init(id)\ 264 AFMT_DCN3_REG_LIST_RI(id) 265 266 static struct dcn30_afmt_registers afmt_regs[6]; 267 268 static const struct dcn30_afmt_shift afmt_shift = { 269 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 270 }; 271 272 static const struct dcn30_afmt_mask afmt_mask = { 273 DCN3_AFMT_MASK_SH_LIST(_MASK) 274 }; 275 276 #define apg_regs_init(id)\ 277 APG_DCN31_REG_LIST_RI(id) 278 279 static struct dcn31_apg_registers apg_regs[4]; 280 281 static const struct dcn31_apg_shift apg_shift = { 282 DCN31_APG_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dcn31_apg_mask apg_mask = { 286 DCN31_APG_MASK_SH_LIST(_MASK) 287 }; 288 289 #define stream_enc_regs_init(id)\ 290 SE_DCN32_REG_LIST_RI(id) 291 292 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 293 294 static const struct dcn10_stream_encoder_shift se_shift = { 295 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 296 }; 297 298 static const struct dcn10_stream_encoder_mask se_mask = { 299 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 300 }; 301 302 303 #define aux_regs_init(id)\ 304 DCN2_AUX_REG_LIST_RI(id) 305 306 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 307 308 #define hpd_regs_init(id)\ 309 HPD_REG_LIST_RI(id) 310 311 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 312 313 #define link_regs_init(id, phyid)\ 314 ( \ 315 LE_DCN31_REG_LIST_RI(id), \ 316 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 317 ) 318 /*DPCS_DCN31_REG_LIST(id),*/ \ 319 320 static struct dcn10_link_enc_registers link_enc_regs[5]; 321 322 static const struct dcn10_link_enc_shift le_shift = { 323 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 324 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dcn10_link_enc_mask le_mask = { 328 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 329 // DPCS_DCN31_MASK_SH_LIST(_MASK) 330 }; 331 332 #define hpo_dp_stream_encoder_reg_init(id)\ 333 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 334 335 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 336 337 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 338 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 343 }; 344 345 346 #define hpo_dp_link_encoder_reg_init(id)\ 347 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 352 353 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 354 355 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 356 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 361 }; 362 363 #define dpp_regs_init(id)\ 364 DPP_REG_LIST_DCN30_COMMON_RI(id) 365 366 static struct dcn3_dpp_registers dpp_regs[4]; 367 368 static const struct dcn3_dpp_shift tf_shift = { 369 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 370 }; 371 372 static const struct dcn3_dpp_mask tf_mask = { 373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 374 }; 375 376 377 #define opp_regs_init(id)\ 378 OPP_REG_LIST_DCN30_RI(id) 379 380 static struct dcn20_opp_registers opp_regs[4]; 381 382 static const struct dcn20_opp_shift opp_shift = { 383 OPP_MASK_SH_LIST_DCN20(__SHIFT) 384 }; 385 386 static const struct dcn20_opp_mask opp_mask = { 387 OPP_MASK_SH_LIST_DCN20(_MASK) 388 }; 389 390 #define aux_engine_regs_init(id) \ 391 ( \ 392 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 #define dcn_mpc_regs_init()\ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id) \ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 static const struct dcn_hubp2_shift hubp_shift = { 486 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 487 }; 488 489 static const struct dcn_hubp2_mask hubp_mask = { 490 HUBP_MASK_SH_LIST_DCN32(_MASK) 491 }; 492 493 static struct dcn_hubbub_registers hubbub_reg; 494 #define hubbub_reg_init()\ 495 HUBBUB_REG_LIST_DCN32_RI(0) 496 497 static const struct dcn_hubbub_shift hubbub_shift = { 498 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 499 }; 500 501 static const struct dcn_hubbub_mask hubbub_mask = { 502 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 503 }; 504 505 static struct dccg_registers dccg_regs; 506 507 #define dccg_regs_init()\ 508 DCCG_REG_LIST_DCN32_RI() 509 510 static const struct dccg_shift dccg_shift = { 511 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 512 }; 513 514 static const struct dccg_mask dccg_mask = { 515 DCCG_MASK_SH_LIST_DCN32(_MASK) 516 }; 517 518 519 #define SRII2(reg_name_pre, reg_name_post, id)\ 520 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 521 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 522 reg ## reg_name_pre ## id ## _ ## reg_name_post 523 524 525 #define HWSEQ_DCN32_REG_LIST()\ 526 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 527 SR(DIO_MEM_PWR_CTRL), \ 528 SR(ODM_MEM_PWR_CTRL3), \ 529 SR(MMHUBBUB_MEM_PWR_CNTL), \ 530 SR(DCCG_GATE_DISABLE_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL2), \ 532 SR(DCFCLK_CNTL),\ 533 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 534 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 536 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 542 SR(MICROSECOND_TIME_BASE_DIV), \ 543 SR(MILLISECOND_TIME_BASE_DIV), \ 544 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 545 SR(RBBMIF_TIMEOUT_DIS), \ 546 SR(RBBMIF_TIMEOUT_DIS_2), \ 547 SR(DCHUBBUB_CRC_CTRL), \ 548 SR(DPP_TOP0_DPP_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 551 SR(MPC_CRC_CTRL), \ 552 SR(MPC_CRC_RESULT_GB), \ 553 SR(MPC_CRC_RESULT_C), \ 554 SR(MPC_CRC_RESULT_AR), \ 555 SR(DOMAIN0_PG_CONFIG), \ 556 SR(DOMAIN1_PG_CONFIG), \ 557 SR(DOMAIN2_PG_CONFIG), \ 558 SR(DOMAIN3_PG_CONFIG), \ 559 SR(DOMAIN16_PG_CONFIG), \ 560 SR(DOMAIN17_PG_CONFIG), \ 561 SR(DOMAIN18_PG_CONFIG), \ 562 SR(DOMAIN19_PG_CONFIG), \ 563 SR(DOMAIN0_PG_STATUS), \ 564 SR(DOMAIN1_PG_STATUS), \ 565 SR(DOMAIN2_PG_STATUS), \ 566 SR(DOMAIN3_PG_STATUS), \ 567 SR(DOMAIN16_PG_STATUS), \ 568 SR(DOMAIN17_PG_STATUS), \ 569 SR(DOMAIN18_PG_STATUS), \ 570 SR(DOMAIN19_PG_STATUS), \ 571 SR(D1VGA_CONTROL), \ 572 SR(D2VGA_CONTROL), \ 573 SR(D3VGA_CONTROL), \ 574 SR(D4VGA_CONTROL), \ 575 SR(D5VGA_CONTROL), \ 576 SR(D6VGA_CONTROL), \ 577 SR(DC_IP_REQUEST_CNTL), \ 578 SR(AZALIA_AUDIO_DTO), \ 579 SR(AZALIA_CONTROLLER_CLOCK_GATING) 580 581 static struct dce_hwseq_registers hwseq_reg; 582 583 #define hwseq_reg_init()\ 584 HWSEQ_DCN32_REG_LIST() 585 586 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 587 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 588 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 589 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 591 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 606 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 616 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 618 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 619 620 static const struct dce_hwseq_shift hwseq_shift = { 621 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 622 }; 623 624 static const struct dce_hwseq_mask hwseq_mask = { 625 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 626 }; 627 #define vmid_regs_init(id)\ 628 DCN20_VMID_REG_LIST_RI(id) 629 630 static struct dcn_vmid_registers vmid_regs[16]; 631 632 static const struct dcn20_vmid_shift vmid_shifts = { 633 DCN20_VMID_MASK_SH_LIST(__SHIFT) 634 }; 635 636 static const struct dcn20_vmid_mask vmid_masks = { 637 DCN20_VMID_MASK_SH_LIST(_MASK) 638 }; 639 640 static const struct resource_caps res_cap_dcn321 = { 641 .num_timing_generator = 4, 642 .num_opp = 4, 643 .num_video_plane = 4, 644 .num_audio = 5, 645 .num_stream_encoder = 5, 646 .num_hpo_dp_stream_encoder = 4, 647 .num_hpo_dp_link_encoder = 2, 648 .num_pll = 5, 649 .num_dwb = 1, 650 .num_ddc = 5, 651 .num_vmid = 16, 652 .num_mpc_3dlut = 4, 653 .num_dsc = 4, 654 }; 655 656 static const struct dc_plane_cap plane_cap = { 657 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 658 .blends_with_above = true, 659 .blends_with_below = true, 660 .per_pixel_alpha = true, 661 662 .pixel_format_support = { 663 .argb8888 = true, 664 .nv12 = true, 665 .fp16 = true, 666 .p010 = true, 667 .ayuv = false, 668 }, 669 670 .max_upscale_factor = { 671 .argb8888 = 16000, 672 .nv12 = 16000, 673 .fp16 = 16000 674 }, 675 676 // 6:1 downscaling ratio: 1000/6 = 166.666 677 .max_downscale_factor = { 678 .argb8888 = 167, 679 .nv12 = 167, 680 .fp16 = 167 681 }, 682 64, 683 64 684 }; 685 686 static const struct dc_debug_options debug_defaults_drv = { 687 .disable_dmcu = true, 688 .force_abm_enable = false, 689 .timing_trace = false, 690 .clock_trace = true, 691 .disable_pplib_clock_request = false, 692 .pipe_split_policy = MPC_SPLIT_AVOID, 693 .force_single_disp_pipe_split = false, 694 .disable_dcc = DCC_ENABLE, 695 .vsr_support = true, 696 .performance_trace = false, 697 .max_downscale_src_width = 7680,/*upto 8K*/ 698 .disable_pplib_wm_range = false, 699 .scl_reset_length10 = true, 700 .sanity_checks = false, 701 .underflow_assert_delay_us = 0xFFFFFFFF, 702 .dwb_fi_phase = -1, // -1 = disable, 703 .dmub_command_table = true, 704 .enable_mem_low_power = { 705 .bits = { 706 .vga = false, 707 .i2c = false, 708 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 709 .dscl = false, 710 .cm = false, 711 .mpc = false, 712 .optc = true, 713 } 714 }, 715 .use_max_lb = true, 716 .force_disable_subvp = false, 717 .exit_idle_opt_for_cursor_updates = true, 718 .enable_single_display_2to1_odm_policy = true, 719 720 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 721 .enable_double_buffered_dsc_pg_support = true, 722 .enable_dp_dig_pixel_rate_div_policy = 1, 723 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 724 .alloc_extra_way_for_cursor = true, 725 .min_prefetch_in_strobe_ns = 60000, // 60us 726 .disable_unbounded_requesting = false, 727 }; 728 729 static const struct dc_debug_options debug_defaults_diags = { 730 .disable_dmcu = true, 731 .force_abm_enable = false, 732 .timing_trace = true, 733 .clock_trace = true, 734 .disable_dpp_power_gate = true, 735 .disable_hubp_power_gate = true, 736 .disable_dsc_power_gate = true, 737 .disable_clock_gate = true, 738 .disable_pplib_clock_request = true, 739 .disable_pplib_wm_range = true, 740 .disable_stutter = false, 741 .scl_reset_length10 = true, 742 .dwb_fi_phase = -1, // -1 = disable 743 .dmub_command_table = true, 744 .enable_tri_buf = true, 745 .use_max_lb = true, 746 .force_disable_subvp = true, 747 }; 748 749 750 static struct dce_aux *dcn321_aux_engine_create( 751 struct dc_context *ctx, 752 uint32_t inst) 753 { 754 struct aux_engine_dce110 *aux_engine = 755 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 756 757 if (!aux_engine) 758 return NULL; 759 760 #undef REG_STRUCT 761 #define REG_STRUCT aux_engine_regs 762 aux_engine_regs_init(0), 763 aux_engine_regs_init(1), 764 aux_engine_regs_init(2), 765 aux_engine_regs_init(3), 766 aux_engine_regs_init(4); 767 768 dce110_aux_engine_construct(aux_engine, ctx, inst, 769 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 770 &aux_engine_regs[inst], 771 &aux_mask, 772 &aux_shift, 773 ctx->dc->caps.extended_aux_timeout_support); 774 775 return &aux_engine->base; 776 } 777 #define i2c_inst_regs_init(id)\ 778 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 779 780 static struct dce_i2c_registers i2c_hw_regs[5]; 781 782 static const struct dce_i2c_shift i2c_shifts = { 783 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 784 }; 785 786 static const struct dce_i2c_mask i2c_masks = { 787 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 788 }; 789 790 static struct dce_i2c_hw *dcn321_i2c_hw_create( 791 struct dc_context *ctx, 792 uint32_t inst) 793 { 794 struct dce_i2c_hw *dce_i2c_hw = 795 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 796 797 if (!dce_i2c_hw) 798 return NULL; 799 800 #undef REG_STRUCT 801 #define REG_STRUCT i2c_hw_regs 802 i2c_inst_regs_init(1), 803 i2c_inst_regs_init(2), 804 i2c_inst_regs_init(3), 805 i2c_inst_regs_init(4), 806 i2c_inst_regs_init(5); 807 808 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 809 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 810 811 return dce_i2c_hw; 812 } 813 814 static struct clock_source *dcn321_clock_source_create( 815 struct dc_context *ctx, 816 struct dc_bios *bios, 817 enum clock_source_id id, 818 const struct dce110_clk_src_regs *regs, 819 bool dp_clk_src) 820 { 821 struct dce110_clk_src *clk_src = 822 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 823 824 if (!clk_src) 825 return NULL; 826 827 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 828 regs, &cs_shift, &cs_mask)) { 829 clk_src->base.dp_clk_src = dp_clk_src; 830 return &clk_src->base; 831 } 832 833 kfree(clk_src); 834 BREAK_TO_DEBUGGER(); 835 return NULL; 836 } 837 838 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 839 { 840 int i; 841 842 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 843 GFP_KERNEL); 844 845 if (!hubbub2) 846 return NULL; 847 848 #undef REG_STRUCT 849 #define REG_STRUCT hubbub_reg 850 hubbub_reg_init(); 851 852 #undef REG_STRUCT 853 #define REG_STRUCT vmid_regs 854 vmid_regs_init(0), 855 vmid_regs_init(1), 856 vmid_regs_init(2), 857 vmid_regs_init(3), 858 vmid_regs_init(4), 859 vmid_regs_init(5), 860 vmid_regs_init(6), 861 vmid_regs_init(7), 862 vmid_regs_init(8), 863 vmid_regs_init(9), 864 vmid_regs_init(10), 865 vmid_regs_init(11), 866 vmid_regs_init(12), 867 vmid_regs_init(13), 868 vmid_regs_init(14), 869 vmid_regs_init(15); 870 871 hubbub32_construct(hubbub2, ctx, 872 &hubbub_reg, 873 &hubbub_shift, 874 &hubbub_mask, 875 ctx->dc->dml.ip.det_buffer_size_kbytes, 876 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 877 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 878 879 880 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 881 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 882 883 vmid->ctx = ctx; 884 885 vmid->regs = &vmid_regs[i]; 886 vmid->shifts = &vmid_shifts; 887 vmid->masks = &vmid_masks; 888 } 889 890 return &hubbub2->base; 891 } 892 893 static struct hubp *dcn321_hubp_create( 894 struct dc_context *ctx, 895 uint32_t inst) 896 { 897 struct dcn20_hubp *hubp2 = 898 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 899 900 if (!hubp2) 901 return NULL; 902 903 #undef REG_STRUCT 904 #define REG_STRUCT hubp_regs 905 hubp_regs_init(0), 906 hubp_regs_init(1), 907 hubp_regs_init(2), 908 hubp_regs_init(3); 909 910 if (hubp32_construct(hubp2, ctx, inst, 911 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 912 return &hubp2->base; 913 914 BREAK_TO_DEBUGGER(); 915 kfree(hubp2); 916 return NULL; 917 } 918 919 static void dcn321_dpp_destroy(struct dpp **dpp) 920 { 921 kfree(TO_DCN30_DPP(*dpp)); 922 *dpp = NULL; 923 } 924 925 static struct dpp *dcn321_dpp_create( 926 struct dc_context *ctx, 927 uint32_t inst) 928 { 929 struct dcn3_dpp *dpp3 = 930 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 931 932 if (!dpp3) 933 return NULL; 934 935 #undef REG_STRUCT 936 #define REG_STRUCT dpp_regs 937 dpp_regs_init(0), 938 dpp_regs_init(1), 939 dpp_regs_init(2), 940 dpp_regs_init(3); 941 942 if (dpp32_construct(dpp3, ctx, inst, 943 &dpp_regs[inst], &tf_shift, &tf_mask)) 944 return &dpp3->base; 945 946 BREAK_TO_DEBUGGER(); 947 kfree(dpp3); 948 return NULL; 949 } 950 951 static struct mpc *dcn321_mpc_create( 952 struct dc_context *ctx, 953 int num_mpcc, 954 int num_rmu) 955 { 956 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 957 GFP_KERNEL); 958 959 if (!mpc30) 960 return NULL; 961 962 #undef REG_STRUCT 963 #define REG_STRUCT mpc_regs 964 dcn_mpc_regs_init(); 965 966 dcn32_mpc_construct(mpc30, ctx, 967 &mpc_regs, 968 &mpc_shift, 969 &mpc_mask, 970 num_mpcc, 971 num_rmu); 972 973 return &mpc30->base; 974 } 975 976 static struct output_pixel_processor *dcn321_opp_create( 977 struct dc_context *ctx, uint32_t inst) 978 { 979 struct dcn20_opp *opp2 = 980 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 981 982 if (!opp2) { 983 BREAK_TO_DEBUGGER(); 984 return NULL; 985 } 986 987 #undef REG_STRUCT 988 #define REG_STRUCT opp_regs 989 opp_regs_init(0), 990 opp_regs_init(1), 991 opp_regs_init(2), 992 opp_regs_init(3); 993 994 dcn20_opp_construct(opp2, ctx, inst, 995 &opp_regs[inst], &opp_shift, &opp_mask); 996 return &opp2->base; 997 } 998 999 1000 static struct timing_generator *dcn321_timing_generator_create( 1001 struct dc_context *ctx, 1002 uint32_t instance) 1003 { 1004 struct optc *tgn10 = 1005 kzalloc(sizeof(struct optc), GFP_KERNEL); 1006 1007 if (!tgn10) 1008 return NULL; 1009 1010 #undef REG_STRUCT 1011 #define REG_STRUCT optc_regs 1012 optc_regs_init(0), 1013 optc_regs_init(1), 1014 optc_regs_init(2), 1015 optc_regs_init(3); 1016 1017 tgn10->base.inst = instance; 1018 tgn10->base.ctx = ctx; 1019 1020 tgn10->tg_regs = &optc_regs[instance]; 1021 tgn10->tg_shift = &optc_shift; 1022 tgn10->tg_mask = &optc_mask; 1023 1024 dcn32_timing_generator_init(tgn10); 1025 1026 return &tgn10->base; 1027 } 1028 1029 static const struct encoder_feature_support link_enc_feature = { 1030 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1031 .max_hdmi_pixel_clock = 600000, 1032 .hdmi_ycbcr420_supported = true, 1033 .dp_ycbcr420_supported = true, 1034 .fec_supported = true, 1035 .flags.bits.IS_HBR2_CAPABLE = true, 1036 .flags.bits.IS_HBR3_CAPABLE = true, 1037 .flags.bits.IS_TPS3_CAPABLE = true, 1038 .flags.bits.IS_TPS4_CAPABLE = true 1039 }; 1040 1041 static struct link_encoder *dcn321_link_encoder_create( 1042 struct dc_context *ctx, 1043 const struct encoder_init_data *enc_init_data) 1044 { 1045 struct dcn20_link_encoder *enc20 = 1046 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1047 1048 if (!enc20) 1049 return NULL; 1050 1051 #undef REG_STRUCT 1052 #define REG_STRUCT link_enc_aux_regs 1053 aux_regs_init(0), 1054 aux_regs_init(1), 1055 aux_regs_init(2), 1056 aux_regs_init(3), 1057 aux_regs_init(4); 1058 1059 #undef REG_STRUCT 1060 #define REG_STRUCT link_enc_hpd_regs 1061 hpd_regs_init(0), 1062 hpd_regs_init(1), 1063 hpd_regs_init(2), 1064 hpd_regs_init(3), 1065 hpd_regs_init(4); 1066 1067 #undef REG_STRUCT 1068 #define REG_STRUCT link_enc_regs 1069 link_regs_init(0, A), 1070 link_regs_init(1, B), 1071 link_regs_init(2, C), 1072 link_regs_init(3, D), 1073 link_regs_init(4, E); 1074 1075 dcn321_link_encoder_construct(enc20, 1076 enc_init_data, 1077 &link_enc_feature, 1078 &link_enc_regs[enc_init_data->transmitter], 1079 &link_enc_aux_regs[enc_init_data->channel - 1], 1080 &link_enc_hpd_regs[enc_init_data->hpd_source], 1081 &le_shift, 1082 &le_mask); 1083 1084 return &enc20->enc10.base; 1085 } 1086 1087 static void read_dce_straps( 1088 struct dc_context *ctx, 1089 struct resource_straps *straps) 1090 { 1091 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1092 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1093 1094 } 1095 1096 static struct audio *dcn321_create_audio( 1097 struct dc_context *ctx, unsigned int inst) 1098 { 1099 1100 #undef REG_STRUCT 1101 #define REG_STRUCT audio_regs 1102 audio_regs_init(0), 1103 audio_regs_init(1), 1104 audio_regs_init(2), 1105 audio_regs_init(3), 1106 audio_regs_init(4); 1107 1108 return dce_audio_create(ctx, inst, 1109 &audio_regs[inst], &audio_shift, &audio_mask); 1110 } 1111 1112 static struct vpg *dcn321_vpg_create( 1113 struct dc_context *ctx, 1114 uint32_t inst) 1115 { 1116 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1117 1118 if (!vpg3) 1119 return NULL; 1120 1121 #undef REG_STRUCT 1122 #define REG_STRUCT vpg_regs 1123 vpg_regs_init(0), 1124 vpg_regs_init(1), 1125 vpg_regs_init(2), 1126 vpg_regs_init(3), 1127 vpg_regs_init(4), 1128 vpg_regs_init(5), 1129 vpg_regs_init(6), 1130 vpg_regs_init(7), 1131 vpg_regs_init(8), 1132 vpg_regs_init(9); 1133 1134 vpg3_construct(vpg3, ctx, inst, 1135 &vpg_regs[inst], 1136 &vpg_shift, 1137 &vpg_mask); 1138 1139 return &vpg3->base; 1140 } 1141 1142 static struct afmt *dcn321_afmt_create( 1143 struct dc_context *ctx, 1144 uint32_t inst) 1145 { 1146 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1147 1148 if (!afmt3) 1149 return NULL; 1150 1151 #undef REG_STRUCT 1152 #define REG_STRUCT afmt_regs 1153 afmt_regs_init(0), 1154 afmt_regs_init(1), 1155 afmt_regs_init(2), 1156 afmt_regs_init(3), 1157 afmt_regs_init(4), 1158 afmt_regs_init(5); 1159 1160 afmt3_construct(afmt3, ctx, inst, 1161 &afmt_regs[inst], 1162 &afmt_shift, 1163 &afmt_mask); 1164 1165 return &afmt3->base; 1166 } 1167 1168 static struct apg *dcn321_apg_create( 1169 struct dc_context *ctx, 1170 uint32_t inst) 1171 { 1172 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1173 1174 if (!apg31) 1175 return NULL; 1176 1177 #undef REG_STRUCT 1178 #define REG_STRUCT apg_regs 1179 apg_regs_init(0), 1180 apg_regs_init(1), 1181 apg_regs_init(2), 1182 apg_regs_init(3); 1183 1184 apg31_construct(apg31, ctx, inst, 1185 &apg_regs[inst], 1186 &apg_shift, 1187 &apg_mask); 1188 1189 return &apg31->base; 1190 } 1191 1192 static struct stream_encoder *dcn321_stream_encoder_create( 1193 enum engine_id eng_id, 1194 struct dc_context *ctx) 1195 { 1196 struct dcn10_stream_encoder *enc1; 1197 struct vpg *vpg; 1198 struct afmt *afmt; 1199 int vpg_inst; 1200 int afmt_inst; 1201 1202 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1203 if (eng_id <= ENGINE_ID_DIGF) { 1204 vpg_inst = eng_id; 1205 afmt_inst = eng_id; 1206 } else 1207 return NULL; 1208 1209 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1210 vpg = dcn321_vpg_create(ctx, vpg_inst); 1211 afmt = dcn321_afmt_create(ctx, afmt_inst); 1212 1213 if (!enc1 || !vpg || !afmt) { 1214 kfree(enc1); 1215 kfree(vpg); 1216 kfree(afmt); 1217 return NULL; 1218 } 1219 1220 #undef REG_STRUCT 1221 #define REG_STRUCT stream_enc_regs 1222 stream_enc_regs_init(0), 1223 stream_enc_regs_init(1), 1224 stream_enc_regs_init(2), 1225 stream_enc_regs_init(3), 1226 stream_enc_regs_init(4); 1227 1228 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1229 eng_id, vpg, afmt, 1230 &stream_enc_regs[eng_id], 1231 &se_shift, &se_mask); 1232 1233 return &enc1->base; 1234 } 1235 1236 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1237 enum engine_id eng_id, 1238 struct dc_context *ctx) 1239 { 1240 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1241 struct vpg *vpg; 1242 struct apg *apg; 1243 uint32_t hpo_dp_inst; 1244 uint32_t vpg_inst; 1245 uint32_t apg_inst; 1246 1247 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1248 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1249 1250 /* Mapping of VPG register blocks to HPO DP block instance: 1251 * VPG[6] -> HPO_DP[0] 1252 * VPG[7] -> HPO_DP[1] 1253 * VPG[8] -> HPO_DP[2] 1254 * VPG[9] -> HPO_DP[3] 1255 */ 1256 vpg_inst = hpo_dp_inst + 6; 1257 1258 /* Mapping of APG register blocks to HPO DP block instance: 1259 * APG[0] -> HPO_DP[0] 1260 * APG[1] -> HPO_DP[1] 1261 * APG[2] -> HPO_DP[2] 1262 * APG[3] -> HPO_DP[3] 1263 */ 1264 apg_inst = hpo_dp_inst; 1265 1266 /* allocate HPO stream encoder and create VPG sub-block */ 1267 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1268 vpg = dcn321_vpg_create(ctx, vpg_inst); 1269 apg = dcn321_apg_create(ctx, apg_inst); 1270 1271 if (!hpo_dp_enc31 || !vpg || !apg) { 1272 kfree(hpo_dp_enc31); 1273 kfree(vpg); 1274 kfree(apg); 1275 return NULL; 1276 } 1277 1278 #undef REG_STRUCT 1279 #define REG_STRUCT hpo_dp_stream_enc_regs 1280 hpo_dp_stream_encoder_reg_init(0), 1281 hpo_dp_stream_encoder_reg_init(1), 1282 hpo_dp_stream_encoder_reg_init(2), 1283 hpo_dp_stream_encoder_reg_init(3); 1284 1285 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1286 hpo_dp_inst, eng_id, vpg, apg, 1287 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1288 &hpo_dp_se_shift, &hpo_dp_se_mask); 1289 1290 return &hpo_dp_enc31->base; 1291 } 1292 1293 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1294 uint8_t inst, 1295 struct dc_context *ctx) 1296 { 1297 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1298 1299 /* allocate HPO link encoder */ 1300 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1301 1302 #undef REG_STRUCT 1303 #define REG_STRUCT hpo_dp_link_enc_regs 1304 hpo_dp_link_encoder_reg_init(0), 1305 hpo_dp_link_encoder_reg_init(1); 1306 1307 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1308 &hpo_dp_link_enc_regs[inst], 1309 &hpo_dp_le_shift, &hpo_dp_le_mask); 1310 1311 return &hpo_dp_enc31->base; 1312 } 1313 1314 static struct dce_hwseq *dcn321_hwseq_create( 1315 struct dc_context *ctx) 1316 { 1317 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1318 1319 #undef REG_STRUCT 1320 #define REG_STRUCT hwseq_reg 1321 hwseq_reg_init(); 1322 1323 if (hws) { 1324 hws->ctx = ctx; 1325 hws->regs = &hwseq_reg; 1326 hws->shifts = &hwseq_shift; 1327 hws->masks = &hwseq_mask; 1328 } 1329 return hws; 1330 } 1331 static const struct resource_create_funcs res_create_funcs = { 1332 .read_dce_straps = read_dce_straps, 1333 .create_audio = dcn321_create_audio, 1334 .create_stream_encoder = dcn321_stream_encoder_create, 1335 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1336 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1337 .create_hwseq = dcn321_hwseq_create, 1338 }; 1339 1340 static const struct resource_create_funcs res_create_maximus_funcs = { 1341 .read_dce_straps = NULL, 1342 .create_audio = NULL, 1343 .create_stream_encoder = NULL, 1344 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1345 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1346 .create_hwseq = dcn321_hwseq_create, 1347 }; 1348 1349 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1350 { 1351 unsigned int i; 1352 1353 for (i = 0; i < pool->base.stream_enc_count; i++) { 1354 if (pool->base.stream_enc[i] != NULL) { 1355 if (pool->base.stream_enc[i]->vpg != NULL) { 1356 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1357 pool->base.stream_enc[i]->vpg = NULL; 1358 } 1359 if (pool->base.stream_enc[i]->afmt != NULL) { 1360 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1361 pool->base.stream_enc[i]->afmt = NULL; 1362 } 1363 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1364 pool->base.stream_enc[i] = NULL; 1365 } 1366 } 1367 1368 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1369 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1370 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1371 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1372 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1373 } 1374 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1375 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1376 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1377 } 1378 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1379 pool->base.hpo_dp_stream_enc[i] = NULL; 1380 } 1381 } 1382 1383 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1384 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1385 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1386 pool->base.hpo_dp_link_enc[i] = NULL; 1387 } 1388 } 1389 1390 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1391 if (pool->base.dscs[i] != NULL) 1392 dcn20_dsc_destroy(&pool->base.dscs[i]); 1393 } 1394 1395 if (pool->base.mpc != NULL) { 1396 kfree(TO_DCN20_MPC(pool->base.mpc)); 1397 pool->base.mpc = NULL; 1398 } 1399 if (pool->base.hubbub != NULL) { 1400 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1401 pool->base.hubbub = NULL; 1402 } 1403 for (i = 0; i < pool->base.pipe_count; i++) { 1404 if (pool->base.dpps[i] != NULL) 1405 dcn321_dpp_destroy(&pool->base.dpps[i]); 1406 1407 if (pool->base.ipps[i] != NULL) 1408 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1409 1410 if (pool->base.hubps[i] != NULL) { 1411 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1412 pool->base.hubps[i] = NULL; 1413 } 1414 1415 if (pool->base.irqs != NULL) 1416 dal_irq_service_destroy(&pool->base.irqs); 1417 } 1418 1419 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1420 if (pool->base.engines[i] != NULL) 1421 dce110_engine_destroy(&pool->base.engines[i]); 1422 if (pool->base.hw_i2cs[i] != NULL) { 1423 kfree(pool->base.hw_i2cs[i]); 1424 pool->base.hw_i2cs[i] = NULL; 1425 } 1426 if (pool->base.sw_i2cs[i] != NULL) { 1427 kfree(pool->base.sw_i2cs[i]); 1428 pool->base.sw_i2cs[i] = NULL; 1429 } 1430 } 1431 1432 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1433 if (pool->base.opps[i] != NULL) 1434 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1438 if (pool->base.timing_generators[i] != NULL) { 1439 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1440 pool->base.timing_generators[i] = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1445 if (pool->base.dwbc[i] != NULL) { 1446 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1447 pool->base.dwbc[i] = NULL; 1448 } 1449 if (pool->base.mcif_wb[i] != NULL) { 1450 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1451 pool->base.mcif_wb[i] = NULL; 1452 } 1453 } 1454 1455 for (i = 0; i < pool->base.audio_count; i++) { 1456 if (pool->base.audios[i]) 1457 dce_aud_destroy(&pool->base.audios[i]); 1458 } 1459 1460 for (i = 0; i < pool->base.clk_src_count; i++) { 1461 if (pool->base.clock_sources[i] != NULL) { 1462 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1463 pool->base.clock_sources[i] = NULL; 1464 } 1465 } 1466 1467 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1468 if (pool->base.mpc_lut[i] != NULL) { 1469 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1470 pool->base.mpc_lut[i] = NULL; 1471 } 1472 if (pool->base.mpc_shaper[i] != NULL) { 1473 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1474 pool->base.mpc_shaper[i] = NULL; 1475 } 1476 } 1477 1478 if (pool->base.dp_clock_source != NULL) { 1479 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1480 pool->base.dp_clock_source = NULL; 1481 } 1482 1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1484 if (pool->base.multiple_abms[i] != NULL) 1485 dce_abm_destroy(&pool->base.multiple_abms[i]); 1486 } 1487 1488 if (pool->base.psr != NULL) 1489 dmub_psr_destroy(&pool->base.psr); 1490 1491 if (pool->base.dccg != NULL) 1492 dcn_dccg_destroy(&pool->base.dccg); 1493 1494 if (pool->base.oem_device != NULL) 1495 link_destroy_ddc_service(&pool->base.oem_device); 1496 } 1497 1498 1499 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1500 { 1501 int i; 1502 uint32_t dwb_count = pool->res_cap->num_dwb; 1503 1504 for (i = 0; i < dwb_count; i++) { 1505 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1506 GFP_KERNEL); 1507 1508 if (!dwbc30) { 1509 dm_error("DC: failed to create dwbc30!\n"); 1510 return false; 1511 } 1512 1513 #undef REG_STRUCT 1514 #define REG_STRUCT dwbc30_regs 1515 dwbc_regs_dcn3_init(0); 1516 1517 dcn30_dwbc_construct(dwbc30, ctx, 1518 &dwbc30_regs[i], 1519 &dwbc30_shift, 1520 &dwbc30_mask, 1521 i); 1522 1523 pool->dwbc[i] = &dwbc30->base; 1524 } 1525 return true; 1526 } 1527 1528 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1529 { 1530 int i; 1531 uint32_t dwb_count = pool->res_cap->num_dwb; 1532 1533 for (i = 0; i < dwb_count; i++) { 1534 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1535 GFP_KERNEL); 1536 1537 if (!mcif_wb30) { 1538 dm_error("DC: failed to create mcif_wb30!\n"); 1539 return false; 1540 } 1541 1542 #undef REG_STRUCT 1543 #define REG_STRUCT mcif_wb30_regs 1544 mcif_wb_regs_dcn3_init(0); 1545 1546 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1547 &mcif_wb30_regs[i], 1548 &mcif_wb30_shift, 1549 &mcif_wb30_mask, 1550 i); 1551 1552 pool->mcif_wb[i] = &mcif_wb30->base; 1553 } 1554 return true; 1555 } 1556 1557 static struct display_stream_compressor *dcn321_dsc_create( 1558 struct dc_context *ctx, uint32_t inst) 1559 { 1560 struct dcn20_dsc *dsc = 1561 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1562 1563 if (!dsc) { 1564 BREAK_TO_DEBUGGER(); 1565 return NULL; 1566 } 1567 1568 #undef REG_STRUCT 1569 #define REG_STRUCT dsc_regs 1570 dsc_regsDCN20_init(0), 1571 dsc_regsDCN20_init(1), 1572 dsc_regsDCN20_init(2), 1573 dsc_regsDCN20_init(3); 1574 1575 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1576 1577 dsc->max_image_width = 6016; 1578 1579 return &dsc->base; 1580 } 1581 1582 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1583 { 1584 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1585 1586 dcn321_resource_destruct(dcn321_pool); 1587 kfree(dcn321_pool); 1588 *pool = NULL; 1589 } 1590 1591 static struct dc_cap_funcs cap_funcs = { 1592 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1593 }; 1594 1595 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1596 { 1597 DC_FP_START(); 1598 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1599 DC_FP_END(); 1600 } 1601 1602 static struct resource_funcs dcn321_res_pool_funcs = { 1603 .destroy = dcn321_destroy_resource_pool, 1604 .link_enc_create = dcn321_link_encoder_create, 1605 .link_enc_create_minimal = NULL, 1606 .panel_cntl_create = dcn32_panel_cntl_create, 1607 .validate_bandwidth = dcn32_validate_bandwidth, 1608 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1609 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1610 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1611 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1612 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1613 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1614 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1615 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1616 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1617 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1618 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1619 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1620 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1621 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1622 .add_phantom_pipes = dcn32_add_phantom_pipes, 1623 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1624 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 1625 .save_mall_state = dcn32_save_mall_state, 1626 .restore_mall_state = dcn32_restore_mall_state, 1627 }; 1628 1629 1630 static bool dcn321_resource_construct( 1631 uint8_t num_virtual_links, 1632 struct dc *dc, 1633 struct dcn321_resource_pool *pool) 1634 { 1635 int i, j; 1636 struct dc_context *ctx = dc->ctx; 1637 struct irq_service_init_data init_data; 1638 struct ddc_service_init_data ddc_init_data = {0}; 1639 uint32_t pipe_fuses = 0; 1640 uint32_t num_pipes = 4; 1641 1642 #undef REG_STRUCT 1643 #define REG_STRUCT bios_regs 1644 bios_regs_init(); 1645 1646 #undef REG_STRUCT 1647 #define REG_STRUCT clk_src_regs 1648 clk_src_regs_init(0, A), 1649 clk_src_regs_init(1, B), 1650 clk_src_regs_init(2, C), 1651 clk_src_regs_init(3, D), 1652 clk_src_regs_init(4, E); 1653 1654 #undef REG_STRUCT 1655 #define REG_STRUCT abm_regs 1656 abm_regs_init(0), 1657 abm_regs_init(1), 1658 abm_regs_init(2), 1659 abm_regs_init(3); 1660 1661 #undef REG_STRUCT 1662 #define REG_STRUCT dccg_regs 1663 dccg_regs_init(); 1664 1665 1666 ctx->dc_bios->regs = &bios_regs; 1667 1668 pool->base.res_cap = &res_cap_dcn321; 1669 /* max number of pipes for ASIC before checking for pipe fuses */ 1670 num_pipes = pool->base.res_cap->num_timing_generator; 1671 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1672 1673 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1674 if (pipe_fuses & 1 << i) 1675 num_pipes--; 1676 1677 if (pipe_fuses & 1) 1678 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1679 1680 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1681 ASSERT(0); //Entire DCN is harvested! 1682 1683 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1684 * value will be changed, update max_num_dpp and max_num_otg for dml. 1685 */ 1686 dcn3_21_ip.max_num_dpp = num_pipes; 1687 dcn3_21_ip.max_num_otg = num_pipes; 1688 1689 pool->base.funcs = &dcn321_res_pool_funcs; 1690 1691 /************************************************* 1692 * Resource + asic cap harcoding * 1693 *************************************************/ 1694 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1695 pool->base.timing_generator_count = num_pipes; 1696 pool->base.pipe_count = num_pipes; 1697 pool->base.mpcc_count = num_pipes; 1698 dc->caps.max_downscale_ratio = 600; 1699 dc->caps.i2c_speed_in_khz = 100; 1700 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1701 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1702 dc->caps.max_cursor_size = 64; 1703 dc->caps.min_horizontal_blanking_period = 80; 1704 dc->caps.dmdata_alloc_size = 2048; 1705 dc->caps.mall_size_per_mem_channel = 4; 1706 dc->caps.mall_size_total = 0; 1707 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1708 dc->caps.cache_line_size = 64; 1709 dc->caps.cache_num_ways = 16; 1710 1711 /* Calculate the available MALL space */ 1712 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 1713 dc, dc->ctx->dc_bios->vram_info.num_chans) * 1714 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1715 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1716 1717 dc->caps.subvp_fw_processing_delay_us = 15; 1718 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1719 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1720 dc->caps.subvp_swath_height_margin_lines = 16; 1721 dc->caps.subvp_pstate_allow_width_us = 20; 1722 dc->caps.subvp_vertical_int_margin_us = 30; 1723 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1724 dc->caps.max_slave_planes = 1; 1725 dc->caps.max_slave_yuv_planes = 1; 1726 dc->caps.max_slave_rgb_planes = 1; 1727 dc->caps.post_blend_color_processing = true; 1728 dc->caps.force_dp_tps4_for_cp2520 = true; 1729 dc->caps.dp_hpo = true; 1730 dc->caps.dp_hdmi21_pcon_support = true; 1731 dc->caps.edp_dsc_support = true; 1732 dc->caps.extended_aux_timeout_support = true; 1733 dc->caps.dmcub_support = true; 1734 1735 /* Color pipeline capabilities */ 1736 dc->caps.color.dpp.dcn_arch = 1; 1737 dc->caps.color.dpp.input_lut_shared = 0; 1738 dc->caps.color.dpp.icsc = 1; 1739 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1740 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1741 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1742 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1743 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1744 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1745 dc->caps.color.dpp.post_csc = 1; 1746 dc->caps.color.dpp.gamma_corr = 1; 1747 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1748 1749 dc->caps.color.dpp.hw_3d_lut = 1; 1750 dc->caps.color.dpp.ogam_ram = 1; 1751 // no OGAM ROM on DCN2 and later ASICs 1752 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1753 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1754 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1755 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1756 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1757 dc->caps.color.dpp.ocsc = 0; 1758 1759 dc->caps.color.mpc.gamut_remap = 1; 1760 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1761 dc->caps.color.mpc.ogam_ram = 1; 1762 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1763 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1764 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1765 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1766 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1767 dc->caps.color.mpc.ocsc = 1; 1768 1769 /* read VBIOS LTTPR caps */ 1770 { 1771 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1772 enum bp_result bp_query_result; 1773 uint8_t is_vbios_lttpr_enable = 0; 1774 1775 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1776 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1777 } 1778 1779 /* interop bit is implicit */ 1780 { 1781 dc->caps.vbios_lttpr_aware = true; 1782 } 1783 } 1784 1785 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1786 dc->debug = debug_defaults_drv; 1787 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1788 dc->debug = debug_defaults_diags; 1789 } else 1790 dc->debug = debug_defaults_diags; 1791 // Init the vm_helper 1792 if (dc->vm_helper) 1793 vm_helper_init(dc->vm_helper, 16); 1794 1795 /************************************************* 1796 * Create resources * 1797 *************************************************/ 1798 1799 /* Clock Sources for Pixel Clock*/ 1800 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1801 dcn321_clock_source_create(ctx, ctx->dc_bios, 1802 CLOCK_SOURCE_COMBO_PHY_PLL0, 1803 &clk_src_regs[0], false); 1804 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1805 dcn321_clock_source_create(ctx, ctx->dc_bios, 1806 CLOCK_SOURCE_COMBO_PHY_PLL1, 1807 &clk_src_regs[1], false); 1808 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1809 dcn321_clock_source_create(ctx, ctx->dc_bios, 1810 CLOCK_SOURCE_COMBO_PHY_PLL2, 1811 &clk_src_regs[2], false); 1812 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1813 dcn321_clock_source_create(ctx, ctx->dc_bios, 1814 CLOCK_SOURCE_COMBO_PHY_PLL3, 1815 &clk_src_regs[3], false); 1816 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1817 dcn321_clock_source_create(ctx, ctx->dc_bios, 1818 CLOCK_SOURCE_COMBO_PHY_PLL4, 1819 &clk_src_regs[4], false); 1820 1821 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1822 1823 /* todo: not reuse phy_pll registers */ 1824 pool->base.dp_clock_source = 1825 dcn321_clock_source_create(ctx, ctx->dc_bios, 1826 CLOCK_SOURCE_ID_DP_DTO, 1827 &clk_src_regs[0], true); 1828 1829 for (i = 0; i < pool->base.clk_src_count; i++) { 1830 if (pool->base.clock_sources[i] == NULL) { 1831 dm_error("DC: failed to create clock sources!\n"); 1832 BREAK_TO_DEBUGGER(); 1833 goto create_fail; 1834 } 1835 } 1836 1837 /* DCCG */ 1838 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1839 if (pool->base.dccg == NULL) { 1840 dm_error("DC: failed to create dccg!\n"); 1841 BREAK_TO_DEBUGGER(); 1842 goto create_fail; 1843 } 1844 1845 /* DML */ 1846 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1847 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1848 1849 /* IRQ Service */ 1850 init_data.ctx = dc->ctx; 1851 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1852 if (!pool->base.irqs) 1853 goto create_fail; 1854 1855 /* HUBBUB */ 1856 pool->base.hubbub = dcn321_hubbub_create(ctx); 1857 if (pool->base.hubbub == NULL) { 1858 BREAK_TO_DEBUGGER(); 1859 dm_error("DC: failed to create hubbub!\n"); 1860 goto create_fail; 1861 } 1862 1863 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1864 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1865 1866 /* if pipe is disabled, skip instance of HW pipe, 1867 * i.e, skip ASIC register instance 1868 */ 1869 if (pipe_fuses & 1 << i) 1870 continue; 1871 1872 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1873 if (pool->base.hubps[j] == NULL) { 1874 BREAK_TO_DEBUGGER(); 1875 dm_error( 1876 "DC: failed to create hubps!\n"); 1877 goto create_fail; 1878 } 1879 1880 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1881 if (pool->base.dpps[j] == NULL) { 1882 BREAK_TO_DEBUGGER(); 1883 dm_error( 1884 "DC: failed to create dpps!\n"); 1885 goto create_fail; 1886 } 1887 1888 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1889 if (pool->base.opps[j] == NULL) { 1890 BREAK_TO_DEBUGGER(); 1891 dm_error( 1892 "DC: failed to create output pixel processor!\n"); 1893 goto create_fail; 1894 } 1895 1896 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1897 ctx, i); 1898 if (pool->base.timing_generators[j] == NULL) { 1899 BREAK_TO_DEBUGGER(); 1900 dm_error("DC: failed to create tg!\n"); 1901 goto create_fail; 1902 } 1903 1904 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1905 &abm_regs[i], 1906 &abm_shift, 1907 &abm_mask); 1908 if (pool->base.multiple_abms[j] == NULL) { 1909 dm_error("DC: failed to create abm for pipe %d!\n", i); 1910 BREAK_TO_DEBUGGER(); 1911 goto create_fail; 1912 } 1913 1914 /* index for resource pool arrays for next valid pipe */ 1915 j++; 1916 } 1917 1918 /* PSR */ 1919 pool->base.psr = dmub_psr_create(ctx); 1920 if (pool->base.psr == NULL) { 1921 dm_error("DC: failed to create psr obj!\n"); 1922 BREAK_TO_DEBUGGER(); 1923 goto create_fail; 1924 } 1925 1926 /* MPCCs */ 1927 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1928 if (pool->base.mpc == NULL) { 1929 BREAK_TO_DEBUGGER(); 1930 dm_error("DC: failed to create mpc!\n"); 1931 goto create_fail; 1932 } 1933 1934 /* DSCs */ 1935 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1936 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1937 if (pool->base.dscs[i] == NULL) { 1938 BREAK_TO_DEBUGGER(); 1939 dm_error("DC: failed to create display stream compressor %d!\n", i); 1940 goto create_fail; 1941 } 1942 } 1943 1944 /* DWB */ 1945 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1946 BREAK_TO_DEBUGGER(); 1947 dm_error("DC: failed to create dwbc!\n"); 1948 goto create_fail; 1949 } 1950 1951 /* MMHUBBUB */ 1952 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1953 BREAK_TO_DEBUGGER(); 1954 dm_error("DC: failed to create mcif_wb!\n"); 1955 goto create_fail; 1956 } 1957 1958 /* AUX and I2C */ 1959 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1960 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1961 if (pool->base.engines[i] == NULL) { 1962 BREAK_TO_DEBUGGER(); 1963 dm_error( 1964 "DC:failed to create aux engine!!\n"); 1965 goto create_fail; 1966 } 1967 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1968 if (pool->base.hw_i2cs[i] == NULL) { 1969 BREAK_TO_DEBUGGER(); 1970 dm_error( 1971 "DC:failed to create hw i2c!!\n"); 1972 goto create_fail; 1973 } 1974 pool->base.sw_i2cs[i] = NULL; 1975 } 1976 1977 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1978 if (!resource_construct(num_virtual_links, dc, &pool->base, 1979 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1980 &res_create_funcs : &res_create_maximus_funcs))) 1981 goto create_fail; 1982 1983 /* HW Sequencer init functions and Plane caps */ 1984 dcn32_hw_sequencer_init_functions(dc); 1985 1986 dc->caps.max_planes = pool->base.pipe_count; 1987 1988 for (i = 0; i < dc->caps.max_planes; ++i) 1989 dc->caps.planes[i] = plane_cap; 1990 1991 dc->cap_funcs = cap_funcs; 1992 1993 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1994 ddc_init_data.ctx = dc->ctx; 1995 ddc_init_data.link = NULL; 1996 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1997 ddc_init_data.id.enum_id = 0; 1998 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1999 pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2000 } else { 2001 pool->base.oem_device = NULL; 2002 } 2003 2004 return true; 2005 2006 create_fail: 2007 2008 dcn321_resource_destruct(pool); 2009 2010 return false; 2011 } 2012 2013 struct resource_pool *dcn321_create_resource_pool( 2014 const struct dc_init_data *init_data, 2015 struct dc *dc) 2016 { 2017 struct dcn321_resource_pool *pool = 2018 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2019 2020 if (!pool) 2021 return NULL; 2022 2023 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2024 return &pool->base; 2025 2026 BREAK_TO_DEBUGGER(); 2027 kfree(pool); 2028 return NULL; 2029 } 2030