1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dml/dcn321/dcn321_fpu.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn32/dcn32_hubbub.h" 46 #include "dcn32/dcn32_mpc.h" 47 #include "dcn32/dcn32_hubp.h" 48 #include "irq/dcn32/irq_service_dcn32.h" 49 #include "dcn32/dcn32_dpp.h" 50 #include "dcn32/dcn32_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn30/dcn30_dio_stream_encoder.h" 59 #include "dcn32/dcn32_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 63 #include "dc_link_dp.h" 64 #include "dcn31/dcn31_apg.h" 65 #include "dcn31/dcn31_dio_link_encoder.h" 66 #include "dcn32/dcn32_dio_link_encoder.h" 67 #include "dcn321_dio_link_encoder.h" 68 #include "dce/dce_clock_source.h" 69 #include "dce/dce_audio.h" 70 #include "dce/dce_hwseq.h" 71 #include "clk_mgr.h" 72 #include "virtual/virtual_stream_encoder.h" 73 #include "dml/display_mode_vba.h" 74 #include "dcn32/dcn32_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dc_link_ddc.h" 77 #include "dcn31/dcn31_panel_cntl.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn32/dcn32_mmhubbub.h" 81 82 #include "dcn/dcn_3_2_1_offset.h" 83 #include "dcn/dcn_3_2_1_sh_mask.h" 84 #include "nbio/nbio_4_3_0_offset.h" 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #define DCN_BASE__INST0_SEG1 0x000000C0 97 #define DCN_BASE__INST0_SEG2 0x000034C0 98 #define DCN_BASE__INST0_SEG3 0x00009000 99 #define NBIO_BASE__INST0_SEG1 0x00000014 100 101 #define MAX_INSTANCE 8 102 #define MAX_SEGMENT 6 103 104 struct IP_BASE_INSTANCE { 105 unsigned int segment[MAX_SEGMENT]; 106 }; 107 108 struct IP_BASE { 109 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 110 }; 111 112 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } } } }; 120 121 #define DC_LOGGER_INIT(logger) 122 #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) 123 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 124 125 enum dcn321_clk_src_array_id { 126 DCN321_CLK_SRC_PLL0, 127 DCN321_CLK_SRC_PLL1, 128 DCN321_CLK_SRC_PLL2, 129 DCN321_CLK_SRC_PLL3, 130 DCN321_CLK_SRC_PLL4, 131 DCN321_CLK_SRC_TOTAL 132 }; 133 134 /* begin ********************* 135 * macros to expend register list macro defined in HW object header file 136 */ 137 138 /* DCN */ 139 /* TODO awful hack. fixup dcn20_dwb.h */ 140 #undef BASE_INNER 141 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 142 143 #define BASE(seg) BASE_INNER(seg) 144 145 #define SR(reg_name)\ 146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 147 reg ## reg_name 148 149 #define SRI(reg_name, block, id)\ 150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 151 reg ## block ## id ## _ ## reg_name 152 153 #define SRI2(reg_name, block, id)\ 154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 155 reg ## reg_name 156 157 #define SRIR(var_name, reg_name, block, id)\ 158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161 #define SRII(reg_name, block, id)\ 162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165 #define SRII_MPC_RMU(reg_name, block, id)\ 166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169 #define SRII_DWB(reg_name, temp_name, block, id)\ 170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## temp_name 172 173 #define DCCG_SRII(reg_name, block, id)\ 174 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) \ 183 NBIO_BASE__INST0_SEG ## seg 184 185 #define NBIO_BASE(seg) \ 186 NBIO_BASE_INNER(seg) 187 188 #define NBIO_SR(reg_name)\ 189 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 190 regBIF_BX0_ ## reg_name 191 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static const struct bios_registers bios_regs = { 197 NBIO_SR(BIOS_SCRATCH_3), 198 NBIO_SR(BIOS_SCRATCH_6) 199 }; 200 201 #define clk_src_regs(index, pllid)\ 202 [index] = {\ 203 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 204 } 205 206 static const struct dce110_clk_src_regs clk_src_regs[] = { 207 clk_src_regs(0, A), 208 clk_src_regs(1, B), 209 clk_src_regs(2, C), 210 clk_src_regs(3, D), 211 clk_src_regs(4, E) 212 }; 213 214 static const struct dce110_clk_src_shift cs_shift = { 215 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 216 }; 217 218 static const struct dce110_clk_src_mask cs_mask = { 219 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 220 }; 221 222 #define abm_regs(id)\ 223 [id] = {\ 224 ABM_DCN32_REG_LIST(id)\ 225 } 226 227 static const struct dce_abm_registers abm_regs[] = { 228 abm_regs(0), 229 abm_regs(1), 230 abm_regs(2), 231 abm_regs(3), 232 }; 233 234 static const struct dce_abm_shift abm_shift = { 235 ABM_MASK_SH_LIST_DCN32(__SHIFT) 236 }; 237 238 static const struct dce_abm_mask abm_mask = { 239 ABM_MASK_SH_LIST_DCN32(_MASK) 240 }; 241 242 #define audio_regs(id)\ 243 [id] = {\ 244 AUD_COMMON_REG_LIST(id)\ 245 } 246 247 static const struct dce_audio_registers audio_regs[] = { 248 audio_regs(0), 249 audio_regs(1), 250 audio_regs(2), 251 audio_regs(3), 252 audio_regs(4) 253 }; 254 255 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 257 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 258 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 259 260 static const struct dce_audio_shift audio_shift = { 261 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 262 }; 263 264 static const struct dce_audio_mask audio_mask = { 265 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 266 }; 267 268 #define vpg_regs(id)\ 269 [id] = {\ 270 VPG_DCN3_REG_LIST(id)\ 271 } 272 273 static const struct dcn30_vpg_registers vpg_regs[] = { 274 vpg_regs(0), 275 vpg_regs(1), 276 vpg_regs(2), 277 vpg_regs(3), 278 vpg_regs(4), 279 vpg_regs(5), 280 vpg_regs(6), 281 vpg_regs(7), 282 vpg_regs(8), 283 vpg_regs(9), 284 }; 285 286 static const struct dcn30_vpg_shift vpg_shift = { 287 DCN3_VPG_MASK_SH_LIST(__SHIFT) 288 }; 289 290 static const struct dcn30_vpg_mask vpg_mask = { 291 DCN3_VPG_MASK_SH_LIST(_MASK) 292 }; 293 294 #define afmt_regs(id)\ 295 [id] = {\ 296 AFMT_DCN3_REG_LIST(id)\ 297 } 298 299 static const struct dcn30_afmt_registers afmt_regs[] = { 300 afmt_regs(0), 301 afmt_regs(1), 302 afmt_regs(2), 303 afmt_regs(3), 304 afmt_regs(4), 305 afmt_regs(5) 306 }; 307 308 static const struct dcn30_afmt_shift afmt_shift = { 309 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 310 }; 311 312 static const struct dcn30_afmt_mask afmt_mask = { 313 DCN3_AFMT_MASK_SH_LIST(_MASK) 314 }; 315 316 #define apg_regs(id)\ 317 [id] = {\ 318 APG_DCN31_REG_LIST(id)\ 319 } 320 321 static const struct dcn31_apg_registers apg_regs[] = { 322 apg_regs(0), 323 apg_regs(1), 324 apg_regs(2), 325 apg_regs(3) 326 }; 327 328 static const struct dcn31_apg_shift apg_shift = { 329 DCN31_APG_MASK_SH_LIST(__SHIFT) 330 }; 331 332 static const struct dcn31_apg_mask apg_mask = { 333 DCN31_APG_MASK_SH_LIST(_MASK) 334 }; 335 336 #define stream_enc_regs(id)\ 337 [id] = {\ 338 SE_DCN32_REG_LIST(id)\ 339 } 340 341 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 342 stream_enc_regs(0), 343 stream_enc_regs(1), 344 stream_enc_regs(2), 345 stream_enc_regs(3), 346 stream_enc_regs(4) 347 }; 348 349 static const struct dcn10_stream_encoder_shift se_shift = { 350 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 351 }; 352 353 static const struct dcn10_stream_encoder_mask se_mask = { 354 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 355 }; 356 357 358 #define aux_regs(id)\ 359 [id] = {\ 360 DCN2_AUX_REG_LIST(id)\ 361 } 362 363 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 364 aux_regs(0), 365 aux_regs(1), 366 aux_regs(2), 367 aux_regs(3), 368 aux_regs(4) 369 }; 370 371 #define hpd_regs(id)\ 372 [id] = {\ 373 HPD_REG_LIST(id)\ 374 } 375 376 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 377 hpd_regs(0), 378 hpd_regs(1), 379 hpd_regs(2), 380 hpd_regs(3), 381 hpd_regs(4) 382 }; 383 384 #define link_regs(id, phyid)\ 385 [id] = {\ 386 LE_DCN31_REG_LIST(id), \ 387 UNIPHY_DCN2_REG_LIST(phyid), \ 388 /*DPCS_DCN31_REG_LIST(id),*/ \ 389 } 390 391 static const struct dcn10_link_enc_registers link_enc_regs[] = { 392 link_regs(0, A), 393 link_regs(1, B), 394 link_regs(2, C), 395 link_regs(3, D), 396 link_regs(4, E) 397 }; 398 399 static const struct dcn10_link_enc_shift le_shift = { 400 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 401 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dcn10_link_enc_mask le_mask = { 405 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 406 // DPCS_DCN31_MASK_SH_LIST(_MASK) 407 }; 408 409 #define hpo_dp_stream_encoder_reg_list(id)\ 410 [id] = {\ 411 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 412 } 413 414 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 415 hpo_dp_stream_encoder_reg_list(0), 416 hpo_dp_stream_encoder_reg_list(1), 417 hpo_dp_stream_encoder_reg_list(2), 418 hpo_dp_stream_encoder_reg_list(3), 419 }; 420 421 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 422 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 423 }; 424 425 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 426 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 427 }; 428 429 430 #define hpo_dp_link_encoder_reg_list(id)\ 431 [id] = {\ 432 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 433 /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ 434 /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ 435 /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ 436 /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ 437 /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ 438 } 439 440 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 441 hpo_dp_link_encoder_reg_list(0), 442 hpo_dp_link_encoder_reg_list(1), 443 }; 444 445 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 446 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 450 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 451 }; 452 453 #define dpp_regs(id)\ 454 [id] = {\ 455 DPP_REG_LIST_DCN30_COMMON(id),\ 456 } 457 458 static const struct dcn3_dpp_registers dpp_regs[] = { 459 dpp_regs(0), 460 dpp_regs(1), 461 dpp_regs(2), 462 dpp_regs(3) 463 }; 464 465 static const struct dcn3_dpp_shift tf_shift = { 466 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 467 }; 468 469 static const struct dcn3_dpp_mask tf_mask = { 470 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 471 }; 472 473 474 #define opp_regs(id)\ 475 [id] = {\ 476 OPP_REG_LIST_DCN30(id),\ 477 } 478 479 static const struct dcn20_opp_registers opp_regs[] = { 480 opp_regs(0), 481 opp_regs(1), 482 opp_regs(2), 483 opp_regs(3) 484 }; 485 486 static const struct dcn20_opp_shift opp_shift = { 487 OPP_MASK_SH_LIST_DCN20(__SHIFT) 488 }; 489 490 static const struct dcn20_opp_mask opp_mask = { 491 OPP_MASK_SH_LIST_DCN20(_MASK) 492 }; 493 494 #define aux_engine_regs(id)\ 495 [id] = {\ 496 AUX_COMMON_REG_LIST0(id), \ 497 .AUXN_IMPCAL = 0, \ 498 .AUXP_IMPCAL = 0, \ 499 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 500 } 501 502 static const struct dce110_aux_registers aux_engine_regs[] = { 503 aux_engine_regs(0), 504 aux_engine_regs(1), 505 aux_engine_regs(2), 506 aux_engine_regs(3), 507 aux_engine_regs(4) 508 }; 509 510 static const struct dce110_aux_registers_shift aux_shift = { 511 DCN_AUX_MASK_SH_LIST(__SHIFT) 512 }; 513 514 static const struct dce110_aux_registers_mask aux_mask = { 515 DCN_AUX_MASK_SH_LIST(_MASK) 516 }; 517 518 519 #define dwbc_regs_dcn3(id)\ 520 [id] = {\ 521 DWBC_COMMON_REG_LIST_DCN30(id),\ 522 } 523 524 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 525 dwbc_regs_dcn3(0), 526 }; 527 528 static const struct dcn30_dwbc_shift dwbc30_shift = { 529 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 530 }; 531 532 static const struct dcn30_dwbc_mask dwbc30_mask = { 533 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 534 }; 535 536 #define mcif_wb_regs_dcn3(id)\ 537 [id] = {\ 538 MCIF_WB_COMMON_REG_LIST_DCN32(id),\ 539 } 540 541 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 542 mcif_wb_regs_dcn3(0) 543 }; 544 545 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 546 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 547 }; 548 549 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 550 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 551 }; 552 553 #define dsc_regsDCN20(id)\ 554 [id] = {\ 555 DSC_REG_LIST_DCN20(id)\ 556 } 557 558 static const struct dcn20_dsc_registers dsc_regs[] = { 559 dsc_regsDCN20(0), 560 dsc_regsDCN20(1), 561 dsc_regsDCN20(2), 562 dsc_regsDCN20(3) 563 }; 564 565 static const struct dcn20_dsc_shift dsc_shift = { 566 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 567 }; 568 569 static const struct dcn20_dsc_mask dsc_mask = { 570 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 571 }; 572 573 static const struct dcn30_mpc_registers mpc_regs = { 574 MPC_REG_LIST_DCN3_2(0), 575 MPC_REG_LIST_DCN3_2(1), 576 MPC_REG_LIST_DCN3_2(2), 577 MPC_REG_LIST_DCN3_2(3), 578 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 579 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 580 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 581 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 582 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 583 }; 584 585 static const struct dcn30_mpc_shift mpc_shift = { 586 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 587 }; 588 589 static const struct dcn30_mpc_mask mpc_mask = { 590 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 591 }; 592 593 #define optc_regs(id)\ 594 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} 595 596 static const struct dcn_optc_registers optc_regs[] = { 597 optc_regs(0), 598 optc_regs(1), 599 optc_regs(2), 600 optc_regs(3) 601 }; 602 603 static const struct dcn_optc_shift optc_shift = { 604 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 605 }; 606 607 static const struct dcn_optc_mask optc_mask = { 608 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 609 }; 610 611 #define hubp_regs(id)\ 612 [id] = {\ 613 HUBP_REG_LIST_DCN32(id)\ 614 } 615 616 static const struct dcn_hubp2_registers hubp_regs[] = { 617 hubp_regs(0), 618 hubp_regs(1), 619 hubp_regs(2), 620 hubp_regs(3) 621 }; 622 623 624 static const struct dcn_hubp2_shift hubp_shift = { 625 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 626 }; 627 628 static const struct dcn_hubp2_mask hubp_mask = { 629 HUBP_MASK_SH_LIST_DCN32(_MASK) 630 }; 631 static const struct dcn_hubbub_registers hubbub_reg = { 632 HUBBUB_REG_LIST_DCN32(0) 633 }; 634 635 static const struct dcn_hubbub_shift hubbub_shift = { 636 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 637 }; 638 639 static const struct dcn_hubbub_mask hubbub_mask = { 640 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 641 }; 642 643 static const struct dccg_registers dccg_regs = { 644 DCCG_REG_LIST_DCN32() 645 }; 646 647 static const struct dccg_shift dccg_shift = { 648 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 649 }; 650 651 static const struct dccg_mask dccg_mask = { 652 DCCG_MASK_SH_LIST_DCN32(_MASK) 653 }; 654 655 656 #define SRII2(reg_name_pre, reg_name_post, id)\ 657 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 658 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 659 reg ## reg_name_pre ## id ## _ ## reg_name_post 660 661 662 #define HWSEQ_DCN32_REG_LIST()\ 663 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 664 SR(DIO_MEM_PWR_CTRL), \ 665 SR(ODM_MEM_PWR_CTRL3), \ 666 SR(MMHUBBUB_MEM_PWR_CNTL), \ 667 SR(DCCG_GATE_DISABLE_CNTL), \ 668 SR(DCCG_GATE_DISABLE_CNTL2), \ 669 SR(DCFCLK_CNTL),\ 670 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 671 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 672 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 673 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 674 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 675 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 676 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 677 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 678 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 679 SR(MICROSECOND_TIME_BASE_DIV), \ 680 SR(MILLISECOND_TIME_BASE_DIV), \ 681 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 682 SR(RBBMIF_TIMEOUT_DIS), \ 683 SR(RBBMIF_TIMEOUT_DIS_2), \ 684 SR(DCHUBBUB_CRC_CTRL), \ 685 SR(DPP_TOP0_DPP_CRC_CTRL), \ 686 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 687 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 688 SR(MPC_CRC_CTRL), \ 689 SR(MPC_CRC_RESULT_GB), \ 690 SR(MPC_CRC_RESULT_C), \ 691 SR(MPC_CRC_RESULT_AR), \ 692 SR(DOMAIN0_PG_CONFIG), \ 693 SR(DOMAIN1_PG_CONFIG), \ 694 SR(DOMAIN2_PG_CONFIG), \ 695 SR(DOMAIN3_PG_CONFIG), \ 696 SR(DOMAIN16_PG_CONFIG), \ 697 SR(DOMAIN17_PG_CONFIG), \ 698 SR(DOMAIN18_PG_CONFIG), \ 699 SR(DOMAIN19_PG_CONFIG), \ 700 SR(DOMAIN0_PG_STATUS), \ 701 SR(DOMAIN1_PG_STATUS), \ 702 SR(DOMAIN2_PG_STATUS), \ 703 SR(DOMAIN3_PG_STATUS), \ 704 SR(DOMAIN16_PG_STATUS), \ 705 SR(DOMAIN17_PG_STATUS), \ 706 SR(DOMAIN18_PG_STATUS), \ 707 SR(DOMAIN19_PG_STATUS), \ 708 SR(D1VGA_CONTROL), \ 709 SR(D2VGA_CONTROL), \ 710 SR(D3VGA_CONTROL), \ 711 SR(D4VGA_CONTROL), \ 712 SR(D5VGA_CONTROL), \ 713 SR(D6VGA_CONTROL), \ 714 SR(DC_IP_REQUEST_CNTL), \ 715 SR(AZALIA_AUDIO_DTO), \ 716 SR(AZALIA_CONTROLLER_CLOCK_GATING) 717 718 static const struct dce_hwseq_registers hwseq_reg = { 719 HWSEQ_DCN32_REG_LIST() 720 }; 721 722 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 723 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 724 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 725 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 726 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 727 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 728 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 729 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 730 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 731 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 732 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 733 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 734 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 735 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 736 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 737 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 738 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 739 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 740 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 741 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 742 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 745 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 746 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 747 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 748 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 749 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 750 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 751 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 752 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 753 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 754 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 755 756 static const struct dce_hwseq_shift hwseq_shift = { 757 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 758 }; 759 760 static const struct dce_hwseq_mask hwseq_mask = { 761 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 762 }; 763 #define vmid_regs(id)\ 764 [id] = {\ 765 DCN20_VMID_REG_LIST(id)\ 766 } 767 768 static const struct dcn_vmid_registers vmid_regs[] = { 769 vmid_regs(0), 770 vmid_regs(1), 771 vmid_regs(2), 772 vmid_regs(3), 773 vmid_regs(4), 774 vmid_regs(5), 775 vmid_regs(6), 776 vmid_regs(7), 777 vmid_regs(8), 778 vmid_regs(9), 779 vmid_regs(10), 780 vmid_regs(11), 781 vmid_regs(12), 782 vmid_regs(13), 783 vmid_regs(14), 784 vmid_regs(15) 785 }; 786 787 static const struct dcn20_vmid_shift vmid_shifts = { 788 DCN20_VMID_MASK_SH_LIST(__SHIFT) 789 }; 790 791 static const struct dcn20_vmid_mask vmid_masks = { 792 DCN20_VMID_MASK_SH_LIST(_MASK) 793 }; 794 795 static const struct resource_caps res_cap_dcn321 = { 796 .num_timing_generator = 4, 797 .num_opp = 4, 798 .num_video_plane = 4, 799 .num_audio = 5, 800 .num_stream_encoder = 5, 801 .num_hpo_dp_stream_encoder = 4, 802 .num_hpo_dp_link_encoder = 2, 803 .num_pll = 5, 804 .num_dwb = 1, 805 .num_ddc = 5, 806 .num_vmid = 16, 807 .num_mpc_3dlut = 4, 808 .num_dsc = 4, 809 }; 810 811 static const struct dc_plane_cap plane_cap = { 812 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 813 .blends_with_above = true, 814 .blends_with_below = true, 815 .per_pixel_alpha = true, 816 817 .pixel_format_support = { 818 .argb8888 = true, 819 .nv12 = true, 820 .fp16 = true, 821 .p010 = true, 822 .ayuv = false, 823 }, 824 825 .max_upscale_factor = { 826 .argb8888 = 16000, 827 .nv12 = 16000, 828 .fp16 = 16000 829 }, 830 831 // 6:1 downscaling ratio: 1000/6 = 166.666 832 .max_downscale_factor = { 833 .argb8888 = 167, 834 .nv12 = 167, 835 .fp16 = 167 836 }, 837 64, 838 64 839 }; 840 841 static const struct dc_debug_options debug_defaults_drv = { 842 .disable_dmcu = true, 843 .force_abm_enable = false, 844 .timing_trace = false, 845 .clock_trace = true, 846 .disable_pplib_clock_request = false, 847 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 848 .force_single_disp_pipe_split = false, 849 .disable_dcc = DCC_ENABLE, 850 .vsr_support = true, 851 .performance_trace = false, 852 .max_downscale_src_width = 7680,/*upto 8K*/ 853 .disable_pplib_wm_range = false, 854 .scl_reset_length10 = true, 855 .sanity_checks = false, 856 .underflow_assert_delay_us = 0xFFFFFFFF, 857 .dwb_fi_phase = -1, // -1 = disable, 858 .dmub_command_table = true, 859 .enable_mem_low_power = { 860 .bits = { 861 .vga = false, 862 .i2c = false, 863 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 864 .dscl = false, 865 .cm = false, 866 .mpc = false, 867 .optc = true, 868 } 869 }, 870 .use_max_lb = true, 871 .force_disable_subvp = true, 872 .enable_single_display_2to1_odm_policy = true, 873 .enable_dp_dig_pixel_rate_div_policy = 1, 874 }; 875 876 static const struct dc_debug_options debug_defaults_diags = { 877 .disable_dmcu = true, 878 .force_abm_enable = false, 879 .timing_trace = true, 880 .clock_trace = true, 881 .disable_dpp_power_gate = true, 882 .disable_hubp_power_gate = true, 883 .disable_dsc_power_gate = true, 884 .disable_clock_gate = true, 885 .disable_pplib_clock_request = true, 886 .disable_pplib_wm_range = true, 887 .disable_stutter = false, 888 .scl_reset_length10 = true, 889 .dwb_fi_phase = -1, // -1 = disable 890 .dmub_command_table = true, 891 .enable_tri_buf = true, 892 .use_max_lb = true, 893 .force_disable_subvp = true 894 }; 895 896 897 static struct dce_aux *dcn321_aux_engine_create( 898 struct dc_context *ctx, 899 uint32_t inst) 900 { 901 struct aux_engine_dce110 *aux_engine = 902 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 903 904 if (!aux_engine) 905 return NULL; 906 907 dce110_aux_engine_construct(aux_engine, ctx, inst, 908 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 909 &aux_engine_regs[inst], 910 &aux_mask, 911 &aux_shift, 912 ctx->dc->caps.extended_aux_timeout_support); 913 914 return &aux_engine->base; 915 } 916 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 917 918 static const struct dce_i2c_registers i2c_hw_regs[] = { 919 i2c_inst_regs(1), 920 i2c_inst_regs(2), 921 i2c_inst_regs(3), 922 i2c_inst_regs(4), 923 i2c_inst_regs(5), 924 }; 925 926 static const struct dce_i2c_shift i2c_shifts = { 927 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 928 }; 929 930 static const struct dce_i2c_mask i2c_masks = { 931 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 932 }; 933 934 static struct dce_i2c_hw *dcn321_i2c_hw_create( 935 struct dc_context *ctx, 936 uint32_t inst) 937 { 938 struct dce_i2c_hw *dce_i2c_hw = 939 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 940 941 if (!dce_i2c_hw) 942 return NULL; 943 944 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 945 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 946 947 return dce_i2c_hw; 948 } 949 950 static struct clock_source *dcn321_clock_source_create( 951 struct dc_context *ctx, 952 struct dc_bios *bios, 953 enum clock_source_id id, 954 const struct dce110_clk_src_regs *regs, 955 bool dp_clk_src) 956 { 957 struct dce110_clk_src *clk_src = 958 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 959 960 if (!clk_src) 961 return NULL; 962 963 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 964 regs, &cs_shift, &cs_mask)) { 965 clk_src->base.dp_clk_src = dp_clk_src; 966 return &clk_src->base; 967 } 968 969 BREAK_TO_DEBUGGER(); 970 return NULL; 971 } 972 973 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 974 { 975 int i; 976 977 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 978 GFP_KERNEL); 979 980 if (!hubbub2) 981 return NULL; 982 983 hubbub32_construct(hubbub2, ctx, 984 &hubbub_reg, 985 &hubbub_shift, 986 &hubbub_mask, 987 ctx->dc->dml.ip.det_buffer_size_kbytes, 988 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 989 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 990 991 992 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 993 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 994 995 vmid->ctx = ctx; 996 997 vmid->regs = &vmid_regs[i]; 998 vmid->shifts = &vmid_shifts; 999 vmid->masks = &vmid_masks; 1000 } 1001 1002 return &hubbub2->base; 1003 } 1004 1005 static struct hubp *dcn321_hubp_create( 1006 struct dc_context *ctx, 1007 uint32_t inst) 1008 { 1009 struct dcn20_hubp *hubp2 = 1010 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1011 1012 if (!hubp2) 1013 return NULL; 1014 1015 if (hubp32_construct(hubp2, ctx, inst, 1016 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1017 return &hubp2->base; 1018 1019 BREAK_TO_DEBUGGER(); 1020 kfree(hubp2); 1021 return NULL; 1022 } 1023 1024 static void dcn321_dpp_destroy(struct dpp **dpp) 1025 { 1026 kfree(TO_DCN30_DPP(*dpp)); 1027 *dpp = NULL; 1028 } 1029 1030 static struct dpp *dcn321_dpp_create( 1031 struct dc_context *ctx, 1032 uint32_t inst) 1033 { 1034 struct dcn3_dpp *dpp3 = 1035 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1036 1037 if (!dpp3) 1038 return NULL; 1039 1040 if (dpp32_construct(dpp3, ctx, inst, 1041 &dpp_regs[inst], &tf_shift, &tf_mask)) 1042 return &dpp3->base; 1043 1044 BREAK_TO_DEBUGGER(); 1045 kfree(dpp3); 1046 return NULL; 1047 } 1048 1049 static struct mpc *dcn321_mpc_create( 1050 struct dc_context *ctx, 1051 int num_mpcc, 1052 int num_rmu) 1053 { 1054 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1055 GFP_KERNEL); 1056 1057 if (!mpc30) 1058 return NULL; 1059 1060 dcn32_mpc_construct(mpc30, ctx, 1061 &mpc_regs, 1062 &mpc_shift, 1063 &mpc_mask, 1064 num_mpcc, 1065 num_rmu); 1066 1067 return &mpc30->base; 1068 } 1069 1070 static struct output_pixel_processor *dcn321_opp_create( 1071 struct dc_context *ctx, uint32_t inst) 1072 { 1073 struct dcn20_opp *opp2 = 1074 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1075 1076 if (!opp2) { 1077 BREAK_TO_DEBUGGER(); 1078 return NULL; 1079 } 1080 1081 dcn20_opp_construct(opp2, ctx, inst, 1082 &opp_regs[inst], &opp_shift, &opp_mask); 1083 return &opp2->base; 1084 } 1085 1086 1087 static struct timing_generator *dcn321_timing_generator_create( 1088 struct dc_context *ctx, 1089 uint32_t instance) 1090 { 1091 struct optc *tgn10 = 1092 kzalloc(sizeof(struct optc), GFP_KERNEL); 1093 1094 if (!tgn10) 1095 return NULL; 1096 1097 tgn10->base.inst = instance; 1098 tgn10->base.ctx = ctx; 1099 1100 tgn10->tg_regs = &optc_regs[instance]; 1101 tgn10->tg_shift = &optc_shift; 1102 tgn10->tg_mask = &optc_mask; 1103 1104 dcn32_timing_generator_init(tgn10); 1105 1106 return &tgn10->base; 1107 } 1108 1109 static const struct encoder_feature_support link_enc_feature = { 1110 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1111 .max_hdmi_pixel_clock = 600000, 1112 .hdmi_ycbcr420_supported = true, 1113 .dp_ycbcr420_supported = true, 1114 .fec_supported = true, 1115 .flags.bits.IS_HBR2_CAPABLE = true, 1116 .flags.bits.IS_HBR3_CAPABLE = true, 1117 .flags.bits.IS_TPS3_CAPABLE = true, 1118 .flags.bits.IS_TPS4_CAPABLE = true 1119 }; 1120 1121 static struct link_encoder *dcn321_link_encoder_create( 1122 const struct encoder_init_data *enc_init_data) 1123 { 1124 struct dcn20_link_encoder *enc20 = 1125 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1126 1127 if (!enc20) 1128 return NULL; 1129 1130 dcn321_link_encoder_construct(enc20, 1131 enc_init_data, 1132 &link_enc_feature, 1133 &link_enc_regs[enc_init_data->transmitter], 1134 &link_enc_aux_regs[enc_init_data->channel - 1], 1135 &link_enc_hpd_regs[enc_init_data->hpd_source], 1136 &le_shift, 1137 &le_mask); 1138 1139 return &enc20->enc10.base; 1140 } 1141 1142 static void read_dce_straps( 1143 struct dc_context *ctx, 1144 struct resource_straps *straps) 1145 { 1146 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1147 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1148 1149 } 1150 1151 static struct audio *dcn321_create_audio( 1152 struct dc_context *ctx, unsigned int inst) 1153 { 1154 return dce_audio_create(ctx, inst, 1155 &audio_regs[inst], &audio_shift, &audio_mask); 1156 } 1157 1158 static struct vpg *dcn321_vpg_create( 1159 struct dc_context *ctx, 1160 uint32_t inst) 1161 { 1162 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1163 1164 if (!vpg3) 1165 return NULL; 1166 1167 vpg3_construct(vpg3, ctx, inst, 1168 &vpg_regs[inst], 1169 &vpg_shift, 1170 &vpg_mask); 1171 1172 return &vpg3->base; 1173 } 1174 1175 static struct afmt *dcn321_afmt_create( 1176 struct dc_context *ctx, 1177 uint32_t inst) 1178 { 1179 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1180 1181 if (!afmt3) 1182 return NULL; 1183 1184 afmt3_construct(afmt3, ctx, inst, 1185 &afmt_regs[inst], 1186 &afmt_shift, 1187 &afmt_mask); 1188 1189 return &afmt3->base; 1190 } 1191 1192 static struct apg *dcn321_apg_create( 1193 struct dc_context *ctx, 1194 uint32_t inst) 1195 { 1196 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1197 1198 if (!apg31) 1199 return NULL; 1200 1201 apg31_construct(apg31, ctx, inst, 1202 &apg_regs[inst], 1203 &apg_shift, 1204 &apg_mask); 1205 1206 return &apg31->base; 1207 } 1208 1209 static struct stream_encoder *dcn321_stream_encoder_create( 1210 enum engine_id eng_id, 1211 struct dc_context *ctx) 1212 { 1213 struct dcn10_stream_encoder *enc1; 1214 struct vpg *vpg; 1215 struct afmt *afmt; 1216 int vpg_inst; 1217 int afmt_inst; 1218 1219 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1220 if (eng_id <= ENGINE_ID_DIGF) { 1221 vpg_inst = eng_id; 1222 afmt_inst = eng_id; 1223 } else 1224 return NULL; 1225 1226 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1227 vpg = dcn321_vpg_create(ctx, vpg_inst); 1228 afmt = dcn321_afmt_create(ctx, afmt_inst); 1229 1230 if (!enc1 || !vpg || !afmt) { 1231 kfree(enc1); 1232 kfree(vpg); 1233 kfree(afmt); 1234 return NULL; 1235 } 1236 1237 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1238 eng_id, vpg, afmt, 1239 &stream_enc_regs[eng_id], 1240 &se_shift, &se_mask); 1241 1242 return &enc1->base; 1243 } 1244 1245 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1246 enum engine_id eng_id, 1247 struct dc_context *ctx) 1248 { 1249 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1250 struct vpg *vpg; 1251 struct apg *apg; 1252 uint32_t hpo_dp_inst; 1253 uint32_t vpg_inst; 1254 uint32_t apg_inst; 1255 1256 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1257 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1258 1259 /* Mapping of VPG register blocks to HPO DP block instance: 1260 * VPG[6] -> HPO_DP[0] 1261 * VPG[7] -> HPO_DP[1] 1262 * VPG[8] -> HPO_DP[2] 1263 * VPG[9] -> HPO_DP[3] 1264 */ 1265 vpg_inst = hpo_dp_inst + 6; 1266 1267 /* Mapping of APG register blocks to HPO DP block instance: 1268 * APG[0] -> HPO_DP[0] 1269 * APG[1] -> HPO_DP[1] 1270 * APG[2] -> HPO_DP[2] 1271 * APG[3] -> HPO_DP[3] 1272 */ 1273 apg_inst = hpo_dp_inst; 1274 1275 /* allocate HPO stream encoder and create VPG sub-block */ 1276 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1277 vpg = dcn321_vpg_create(ctx, vpg_inst); 1278 apg = dcn321_apg_create(ctx, apg_inst); 1279 1280 if (!hpo_dp_enc31 || !vpg || !apg) { 1281 kfree(hpo_dp_enc31); 1282 kfree(vpg); 1283 kfree(apg); 1284 return NULL; 1285 } 1286 1287 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1288 hpo_dp_inst, eng_id, vpg, apg, 1289 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1290 &hpo_dp_se_shift, &hpo_dp_se_mask); 1291 1292 return &hpo_dp_enc31->base; 1293 } 1294 1295 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1296 uint8_t inst, 1297 struct dc_context *ctx) 1298 { 1299 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1300 1301 /* allocate HPO link encoder */ 1302 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1303 1304 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1305 &hpo_dp_link_enc_regs[inst], 1306 &hpo_dp_le_shift, &hpo_dp_le_mask); 1307 1308 return &hpo_dp_enc31->base; 1309 } 1310 1311 static struct dce_hwseq *dcn321_hwseq_create( 1312 struct dc_context *ctx) 1313 { 1314 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1315 1316 if (hws) { 1317 hws->ctx = ctx; 1318 hws->regs = &hwseq_reg; 1319 hws->shifts = &hwseq_shift; 1320 hws->masks = &hwseq_mask; 1321 } 1322 return hws; 1323 } 1324 static const struct resource_create_funcs res_create_funcs = { 1325 .read_dce_straps = read_dce_straps, 1326 .create_audio = dcn321_create_audio, 1327 .create_stream_encoder = dcn321_stream_encoder_create, 1328 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1329 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1330 .create_hwseq = dcn321_hwseq_create, 1331 }; 1332 1333 static const struct resource_create_funcs res_create_maximus_funcs = { 1334 .read_dce_straps = NULL, 1335 .create_audio = NULL, 1336 .create_stream_encoder = NULL, 1337 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1338 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1339 .create_hwseq = dcn321_hwseq_create, 1340 }; 1341 1342 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1343 { 1344 unsigned int i; 1345 1346 for (i = 0; i < pool->base.stream_enc_count; i++) { 1347 if (pool->base.stream_enc[i] != NULL) { 1348 if (pool->base.stream_enc[i]->vpg != NULL) { 1349 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1350 pool->base.stream_enc[i]->vpg = NULL; 1351 } 1352 if (pool->base.stream_enc[i]->afmt != NULL) { 1353 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1354 pool->base.stream_enc[i]->afmt = NULL; 1355 } 1356 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1357 pool->base.stream_enc[i] = NULL; 1358 } 1359 } 1360 1361 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1362 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1363 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1364 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1365 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1366 } 1367 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1368 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1369 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1370 } 1371 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1372 pool->base.hpo_dp_stream_enc[i] = NULL; 1373 } 1374 } 1375 1376 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1377 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1378 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1379 pool->base.hpo_dp_link_enc[i] = NULL; 1380 } 1381 } 1382 1383 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1384 if (pool->base.dscs[i] != NULL) 1385 dcn20_dsc_destroy(&pool->base.dscs[i]); 1386 } 1387 1388 if (pool->base.mpc != NULL) { 1389 kfree(TO_DCN20_MPC(pool->base.mpc)); 1390 pool->base.mpc = NULL; 1391 } 1392 if (pool->base.hubbub != NULL) { 1393 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1394 pool->base.hubbub = NULL; 1395 } 1396 for (i = 0; i < pool->base.pipe_count; i++) { 1397 if (pool->base.dpps[i] != NULL) 1398 dcn321_dpp_destroy(&pool->base.dpps[i]); 1399 1400 if (pool->base.ipps[i] != NULL) 1401 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1402 1403 if (pool->base.hubps[i] != NULL) { 1404 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1405 pool->base.hubps[i] = NULL; 1406 } 1407 1408 if (pool->base.irqs != NULL) 1409 dal_irq_service_destroy(&pool->base.irqs); 1410 } 1411 1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1413 if (pool->base.engines[i] != NULL) 1414 dce110_engine_destroy(&pool->base.engines[i]); 1415 if (pool->base.hw_i2cs[i] != NULL) { 1416 kfree(pool->base.hw_i2cs[i]); 1417 pool->base.hw_i2cs[i] = NULL; 1418 } 1419 if (pool->base.sw_i2cs[i] != NULL) { 1420 kfree(pool->base.sw_i2cs[i]); 1421 pool->base.sw_i2cs[i] = NULL; 1422 } 1423 } 1424 1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1426 if (pool->base.opps[i] != NULL) 1427 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1428 } 1429 1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1431 if (pool->base.timing_generators[i] != NULL) { 1432 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1433 pool->base.timing_generators[i] = NULL; 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1438 if (pool->base.dwbc[i] != NULL) { 1439 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1440 pool->base.dwbc[i] = NULL; 1441 } 1442 if (pool->base.mcif_wb[i] != NULL) { 1443 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1444 pool->base.mcif_wb[i] = NULL; 1445 } 1446 } 1447 1448 for (i = 0; i < pool->base.audio_count; i++) { 1449 if (pool->base.audios[i]) 1450 dce_aud_destroy(&pool->base.audios[i]); 1451 } 1452 1453 for (i = 0; i < pool->base.clk_src_count; i++) { 1454 if (pool->base.clock_sources[i] != NULL) { 1455 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1456 pool->base.clock_sources[i] = NULL; 1457 } 1458 } 1459 1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1461 if (pool->base.mpc_lut[i] != NULL) { 1462 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1463 pool->base.mpc_lut[i] = NULL; 1464 } 1465 if (pool->base.mpc_shaper[i] != NULL) { 1466 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1467 pool->base.mpc_shaper[i] = NULL; 1468 } 1469 } 1470 1471 if (pool->base.dp_clock_source != NULL) { 1472 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1473 pool->base.dp_clock_source = NULL; 1474 } 1475 1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1477 if (pool->base.multiple_abms[i] != NULL) 1478 dce_abm_destroy(&pool->base.multiple_abms[i]); 1479 } 1480 1481 if (pool->base.psr != NULL) 1482 dmub_psr_destroy(&pool->base.psr); 1483 1484 if (pool->base.dccg != NULL) 1485 dcn_dccg_destroy(&pool->base.dccg); 1486 1487 if (pool->base.oem_device != NULL) 1488 dal_ddc_service_destroy(&pool->base.oem_device); 1489 } 1490 1491 1492 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1493 { 1494 int i; 1495 uint32_t dwb_count = pool->res_cap->num_dwb; 1496 1497 for (i = 0; i < dwb_count; i++) { 1498 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1499 GFP_KERNEL); 1500 1501 if (!dwbc30) { 1502 dm_error("DC: failed to create dwbc30!\n"); 1503 return false; 1504 } 1505 1506 dcn30_dwbc_construct(dwbc30, ctx, 1507 &dwbc30_regs[i], 1508 &dwbc30_shift, 1509 &dwbc30_mask, 1510 i); 1511 1512 pool->dwbc[i] = &dwbc30->base; 1513 } 1514 return true; 1515 } 1516 1517 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1518 { 1519 int i; 1520 uint32_t dwb_count = pool->res_cap->num_dwb; 1521 1522 for (i = 0; i < dwb_count; i++) { 1523 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1524 GFP_KERNEL); 1525 1526 if (!mcif_wb30) { 1527 dm_error("DC: failed to create mcif_wb30!\n"); 1528 return false; 1529 } 1530 1531 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1532 &mcif_wb30_regs[i], 1533 &mcif_wb30_shift, 1534 &mcif_wb30_mask, 1535 i); 1536 1537 pool->mcif_wb[i] = &mcif_wb30->base; 1538 } 1539 return true; 1540 } 1541 1542 static struct display_stream_compressor *dcn321_dsc_create( 1543 struct dc_context *ctx, uint32_t inst) 1544 { 1545 struct dcn20_dsc *dsc = 1546 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1547 1548 if (!dsc) { 1549 BREAK_TO_DEBUGGER(); 1550 return NULL; 1551 } 1552 1553 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1554 1555 dsc->max_image_width = 6016; 1556 1557 return &dsc->base; 1558 } 1559 1560 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1561 { 1562 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1563 1564 dcn321_resource_destruct(dcn321_pool); 1565 kfree(dcn321_pool); 1566 *pool = NULL; 1567 } 1568 1569 static struct dc_cap_funcs cap_funcs = { 1570 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1571 }; 1572 1573 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1574 { 1575 DC_FP_START(); 1576 dcn321_update_bw_bounding_box_fpu(dc, bw_params); 1577 DC_FP_END(); 1578 } 1579 1580 static struct resource_funcs dcn321_res_pool_funcs = { 1581 .destroy = dcn321_destroy_resource_pool, 1582 .link_enc_create = dcn321_link_encoder_create, 1583 .link_enc_create_minimal = NULL, 1584 .panel_cntl_create = dcn32_panel_cntl_create, 1585 .validate_bandwidth = dcn32_validate_bandwidth, 1586 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1587 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1588 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1589 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1590 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1591 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1592 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1593 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1594 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1595 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1596 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1597 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 1598 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1599 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1600 .add_phantom_pipes = dcn32_add_phantom_pipes, 1601 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1602 }; 1603 1604 1605 static bool dcn321_resource_construct( 1606 uint8_t num_virtual_links, 1607 struct dc *dc, 1608 struct dcn321_resource_pool *pool) 1609 { 1610 int i, j; 1611 struct dc_context *ctx = dc->ctx; 1612 struct irq_service_init_data init_data; 1613 struct ddc_service_init_data ddc_init_data = {0}; 1614 uint32_t pipe_fuses = 0; 1615 uint32_t num_pipes = 4; 1616 1617 ctx->dc_bios->regs = &bios_regs; 1618 1619 pool->base.res_cap = &res_cap_dcn321; 1620 /* max number of pipes for ASIC before checking for pipe fuses */ 1621 num_pipes = pool->base.res_cap->num_timing_generator; 1622 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1623 1624 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1625 if (pipe_fuses & 1 << i) 1626 num_pipes--; 1627 1628 if (pipe_fuses & 1) 1629 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1630 1631 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1632 ASSERT(0); //Entire DCN is harvested! 1633 1634 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1635 * value will be changed, update max_num_dpp and max_num_otg for dml. 1636 */ 1637 dcn3_21_ip.max_num_dpp = num_pipes; 1638 dcn3_21_ip.max_num_otg = num_pipes; 1639 1640 pool->base.funcs = &dcn321_res_pool_funcs; 1641 1642 /************************************************* 1643 * Resource + asic cap harcoding * 1644 *************************************************/ 1645 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1646 pool->base.timing_generator_count = num_pipes; 1647 pool->base.pipe_count = num_pipes; 1648 pool->base.mpcc_count = num_pipes; 1649 dc->caps.max_downscale_ratio = 600; 1650 dc->caps.i2c_speed_in_khz = 100; 1651 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1652 dc->caps.max_cursor_size = 256; 1653 dc->caps.min_horizontal_blanking_period = 80; 1654 dc->caps.dmdata_alloc_size = 2048; 1655 dc->caps.mall_size_per_mem_channel = 0; 1656 dc->caps.mall_size_total = 0; 1657 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1658 dc->caps.cache_line_size = 64; 1659 dc->caps.cache_num_ways = 16; 1660 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 1661 dc->caps.subvp_fw_processing_delay_us = 15; 1662 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1663 dc->caps.subvp_pstate_allow_width_us = 20; 1664 1665 dc->caps.max_slave_planes = 1; 1666 dc->caps.max_slave_yuv_planes = 1; 1667 dc->caps.max_slave_rgb_planes = 1; 1668 dc->caps.post_blend_color_processing = true; 1669 dc->caps.force_dp_tps4_for_cp2520 = true; 1670 dc->caps.dp_hpo = true; 1671 dc->caps.dp_hdmi21_pcon_support = true; 1672 dc->caps.edp_dsc_support = true; 1673 dc->caps.extended_aux_timeout_support = true; 1674 dc->caps.dmcub_support = true; 1675 1676 /* Color pipeline capabilities */ 1677 dc->caps.color.dpp.dcn_arch = 1; 1678 dc->caps.color.dpp.input_lut_shared = 0; 1679 dc->caps.color.dpp.icsc = 1; 1680 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1681 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1682 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1683 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1684 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1685 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1686 dc->caps.color.dpp.post_csc = 1; 1687 dc->caps.color.dpp.gamma_corr = 1; 1688 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1689 1690 dc->caps.color.dpp.hw_3d_lut = 1; 1691 dc->caps.color.dpp.ogam_ram = 1; 1692 // no OGAM ROM on DCN2 and later ASICs 1693 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1694 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1695 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1696 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1697 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1698 dc->caps.color.dpp.ocsc = 0; 1699 1700 dc->caps.color.mpc.gamut_remap = 1; 1701 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 1702 dc->caps.color.mpc.ogam_ram = 1; 1703 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1704 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1705 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1706 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1707 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1708 dc->caps.color.mpc.ocsc = 1; 1709 1710 /* read VBIOS LTTPR caps */ 1711 { 1712 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1713 enum bp_result bp_query_result; 1714 uint8_t is_vbios_lttpr_enable = 0; 1715 1716 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1717 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1718 } 1719 1720 /* interop bit is implicit */ 1721 { 1722 dc->caps.vbios_lttpr_aware = true; 1723 } 1724 } 1725 1726 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1727 dc->debug = debug_defaults_drv; 1728 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1729 dc->debug = debug_defaults_diags; 1730 } else 1731 dc->debug = debug_defaults_diags; 1732 // Init the vm_helper 1733 if (dc->vm_helper) 1734 vm_helper_init(dc->vm_helper, 16); 1735 1736 /************************************************* 1737 * Create resources * 1738 *************************************************/ 1739 1740 /* Clock Sources for Pixel Clock*/ 1741 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 1742 dcn321_clock_source_create(ctx, ctx->dc_bios, 1743 CLOCK_SOURCE_COMBO_PHY_PLL0, 1744 &clk_src_regs[0], false); 1745 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 1746 dcn321_clock_source_create(ctx, ctx->dc_bios, 1747 CLOCK_SOURCE_COMBO_PHY_PLL1, 1748 &clk_src_regs[1], false); 1749 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 1750 dcn321_clock_source_create(ctx, ctx->dc_bios, 1751 CLOCK_SOURCE_COMBO_PHY_PLL2, 1752 &clk_src_regs[2], false); 1753 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 1754 dcn321_clock_source_create(ctx, ctx->dc_bios, 1755 CLOCK_SOURCE_COMBO_PHY_PLL3, 1756 &clk_src_regs[3], false); 1757 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 1758 dcn321_clock_source_create(ctx, ctx->dc_bios, 1759 CLOCK_SOURCE_COMBO_PHY_PLL4, 1760 &clk_src_regs[4], false); 1761 1762 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 1763 1764 /* todo: not reuse phy_pll registers */ 1765 pool->base.dp_clock_source = 1766 dcn321_clock_source_create(ctx, ctx->dc_bios, 1767 CLOCK_SOURCE_ID_DP_DTO, 1768 &clk_src_regs[0], true); 1769 1770 for (i = 0; i < pool->base.clk_src_count; i++) { 1771 if (pool->base.clock_sources[i] == NULL) { 1772 dm_error("DC: failed to create clock sources!\n"); 1773 BREAK_TO_DEBUGGER(); 1774 goto create_fail; 1775 } 1776 } 1777 1778 /* DCCG */ 1779 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1780 if (pool->base.dccg == NULL) { 1781 dm_error("DC: failed to create dccg!\n"); 1782 BREAK_TO_DEBUGGER(); 1783 goto create_fail; 1784 } 1785 1786 /* DML */ 1787 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1788 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 1789 1790 /* IRQ Service */ 1791 init_data.ctx = dc->ctx; 1792 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 1793 if (!pool->base.irqs) 1794 goto create_fail; 1795 1796 /* HUBBUB */ 1797 pool->base.hubbub = dcn321_hubbub_create(ctx); 1798 if (pool->base.hubbub == NULL) { 1799 BREAK_TO_DEBUGGER(); 1800 dm_error("DC: failed to create hubbub!\n"); 1801 goto create_fail; 1802 } 1803 1804 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 1805 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1806 1807 /* if pipe is disabled, skip instance of HW pipe, 1808 * i.e, skip ASIC register instance 1809 */ 1810 if (pipe_fuses & 1 << i) 1811 continue; 1812 1813 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 1814 if (pool->base.hubps[j] == NULL) { 1815 BREAK_TO_DEBUGGER(); 1816 dm_error( 1817 "DC: failed to create hubps!\n"); 1818 goto create_fail; 1819 } 1820 1821 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 1822 if (pool->base.dpps[j] == NULL) { 1823 BREAK_TO_DEBUGGER(); 1824 dm_error( 1825 "DC: failed to create dpps!\n"); 1826 goto create_fail; 1827 } 1828 1829 pool->base.opps[j] = dcn321_opp_create(ctx, i); 1830 if (pool->base.opps[j] == NULL) { 1831 BREAK_TO_DEBUGGER(); 1832 dm_error( 1833 "DC: failed to create output pixel processor!\n"); 1834 goto create_fail; 1835 } 1836 1837 pool->base.timing_generators[j] = dcn321_timing_generator_create( 1838 ctx, i); 1839 if (pool->base.timing_generators[j] == NULL) { 1840 BREAK_TO_DEBUGGER(); 1841 dm_error("DC: failed to create tg!\n"); 1842 goto create_fail; 1843 } 1844 1845 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 1846 &abm_regs[i], 1847 &abm_shift, 1848 &abm_mask); 1849 if (pool->base.multiple_abms[j] == NULL) { 1850 dm_error("DC: failed to create abm for pipe %d!\n", i); 1851 BREAK_TO_DEBUGGER(); 1852 goto create_fail; 1853 } 1854 1855 /* index for resource pool arrays for next valid pipe */ 1856 j++; 1857 } 1858 1859 /* PSR */ 1860 pool->base.psr = dmub_psr_create(ctx); 1861 if (pool->base.psr == NULL) { 1862 dm_error("DC: failed to create psr obj!\n"); 1863 BREAK_TO_DEBUGGER(); 1864 goto create_fail; 1865 } 1866 1867 /* MPCCs */ 1868 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 1869 if (pool->base.mpc == NULL) { 1870 BREAK_TO_DEBUGGER(); 1871 dm_error("DC: failed to create mpc!\n"); 1872 goto create_fail; 1873 } 1874 1875 /* DSCs */ 1876 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1877 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 1878 if (pool->base.dscs[i] == NULL) { 1879 BREAK_TO_DEBUGGER(); 1880 dm_error("DC: failed to create display stream compressor %d!\n", i); 1881 goto create_fail; 1882 } 1883 } 1884 1885 /* DWB */ 1886 if (!dcn321_dwbc_create(ctx, &pool->base)) { 1887 BREAK_TO_DEBUGGER(); 1888 dm_error("DC: failed to create dwbc!\n"); 1889 goto create_fail; 1890 } 1891 1892 /* MMHUBBUB */ 1893 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 1894 BREAK_TO_DEBUGGER(); 1895 dm_error("DC: failed to create mcif_wb!\n"); 1896 goto create_fail; 1897 } 1898 1899 /* AUX and I2C */ 1900 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1901 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 1902 if (pool->base.engines[i] == NULL) { 1903 BREAK_TO_DEBUGGER(); 1904 dm_error( 1905 "DC:failed to create aux engine!!\n"); 1906 goto create_fail; 1907 } 1908 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 1909 if (pool->base.hw_i2cs[i] == NULL) { 1910 BREAK_TO_DEBUGGER(); 1911 dm_error( 1912 "DC:failed to create hw i2c!!\n"); 1913 goto create_fail; 1914 } 1915 pool->base.sw_i2cs[i] = NULL; 1916 } 1917 1918 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1919 if (!resource_construct(num_virtual_links, dc, &pool->base, 1920 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1921 &res_create_funcs : &res_create_maximus_funcs))) 1922 goto create_fail; 1923 1924 /* HW Sequencer init functions and Plane caps */ 1925 dcn32_hw_sequencer_init_functions(dc); 1926 1927 dc->caps.max_planes = pool->base.pipe_count; 1928 1929 for (i = 0; i < dc->caps.max_planes; ++i) 1930 dc->caps.planes[i] = plane_cap; 1931 1932 dc->cap_funcs = cap_funcs; 1933 1934 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1935 ddc_init_data.ctx = dc->ctx; 1936 ddc_init_data.link = NULL; 1937 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1938 ddc_init_data.id.enum_id = 0; 1939 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1940 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 1941 } else { 1942 pool->base.oem_device = NULL; 1943 } 1944 1945 return true; 1946 1947 create_fail: 1948 1949 dcn321_resource_destruct(pool); 1950 1951 return false; 1952 } 1953 1954 struct resource_pool *dcn321_create_resource_pool( 1955 const struct dc_init_data *init_data, 1956 struct dc *dc) 1957 { 1958 struct dcn321_resource_pool *pool = 1959 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 1960 1961 if (!pool) 1962 return NULL; 1963 1964 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 1965 return &pool->base; 1966 1967 BREAK_TO_DEBUGGER(); 1968 kfree(pool); 1969 return NULL; 1970 } 1971