1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32/dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32/dcn32_resource.h" 35 #include "dcn321_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn32/dcn32_hubbub.h" 44 #include "dcn32/dcn32_mpc.h" 45 #include "dcn32/dcn32_hubp.h" 46 #include "irq/dcn32/irq_service_dcn32.h" 47 #include "dcn32/dcn32_dpp.h" 48 #include "dcn32/dcn32_optc.h" 49 #include "dcn20/dcn20_hwseq.h" 50 #include "dcn30/dcn30_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dcn30/dcn30_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dcn30/dcn30_afmt.h" 56 #include "dcn30/dcn30_dio_stream_encoder.h" 57 #include "dcn32/dcn32_dio_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 59 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 60 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 61 #include "dc_link_dp.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_dio_link_encoder.h" 64 #include "dcn32/dcn32_dio_link_encoder.h" 65 #include "dcn321_dio_link_encoder.h" 66 #include "dce/dce_clock_source.h" 67 #include "dce/dce_audio.h" 68 #include "dce/dce_hwseq.h" 69 #include "clk_mgr.h" 70 #include "virtual/virtual_stream_encoder.h" 71 #include "dml/display_mode_vba.h" 72 #include "dcn32/dcn32_dccg.h" 73 #include "dcn10/dcn10_resource.h" 74 #include "dc_link_ddc.h" 75 #include "dcn31/dcn31_panel_cntl.h" 76 77 #include "dcn30/dcn30_dwb.h" 78 #include "dcn32/dcn32_mmhubbub.h" 79 80 #include "dcn/dcn_3_2_1_offset.h" 81 #include "dcn/dcn_3_2_1_sh_mask.h" 82 #include "nbio/nbio_4_3_0_offset.h" 83 84 #include "reg_helper.h" 85 #include "dce/dmub_abm.h" 86 #include "dce/dmub_psr.h" 87 #include "dce/dce_aux.h" 88 #include "dce/dce_i2c.h" 89 90 #include "dml/dcn30/display_mode_vba_30.h" 91 #include "vm_helper.h" 92 #include "dcn20/dcn20_vmid.h" 93 94 #define DCN_BASE__INST0_SEG1 0x000000C0 95 #define DCN_BASE__INST0_SEG2 0x000034C0 96 #define DCN_BASE__INST0_SEG3 0x00009000 97 #define NBIO_BASE__INST0_SEG1 0x00000014 98 99 #define MAX_INSTANCE 8 100 #define MAX_SEGMENT 6 101 102 struct IP_BASE_INSTANCE { 103 unsigned int segment[MAX_SEGMENT]; 104 }; 105 106 struct IP_BASE { 107 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 108 }; 109 110 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } } } }; 118 119 #define DC_LOGGER_INIT(logger) 120 #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) 121 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 122 123 #define DCN3_2_DEFAULT_DET_SIZE 256 124 125 struct _vcs_dpi_ip_params_st dcn3_21_ip = { 126 .gpuvm_enable = 1, 127 .gpuvm_max_page_table_levels = 4, 128 .hostvm_enable = 0, 129 .rob_buffer_size_kbytes = 128, 130 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 131 .config_return_buffer_size_in_kbytes = 1280, 132 .compressed_buffer_segment_size_in_kbytes = 64, 133 .meta_fifo_size_in_kentries = 22, 134 .zero_size_buffer_entries = 512, 135 .compbuf_reserved_space_64b = 256, 136 .compbuf_reserved_space_zs = 64, 137 .dpp_output_buffer_pixels = 2560, 138 .opp_output_buffer_lines = 1, 139 .pixel_chunk_size_kbytes = 8, 140 .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team 141 .min_pixel_chunk_size_bytes = 1024, 142 .dcc_meta_buffer_size_bytes = 6272, 143 .meta_chunk_size_kbytes = 2, 144 .min_meta_chunk_size_bytes = 256, 145 .writeback_chunk_size_kbytes = 8, 146 .ptoi_supported = false, 147 .num_dsc = 4, 148 .maximum_dsc_bits_per_component = 12, 149 .maximum_pixels_per_line_per_dsc_unit = 6016, 150 .dsc422_native_support = true, 151 .is_line_buffer_bpp_fixed = true, 152 .line_buffer_fixed_bpp = 57, 153 .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp 154 .max_line_buffer_lines = 32, 155 .writeback_interface_buffer_size_kbytes = 90, 156 .max_num_dpp = 4, 157 .max_num_otg = 4, 158 .max_num_hdmi_frl_outputs = 1, 159 .max_num_wb = 1, 160 .max_dchub_pscl_bw_pix_per_clk = 4, 161 .max_pscl_lb_bw_pix_per_clk = 2, 162 .max_lb_vscl_bw_pix_per_clk = 4, 163 .max_vscl_hscl_bw_pix_per_clk = 4, 164 .max_hscl_ratio = 6, 165 .max_vscl_ratio = 6, 166 .max_hscl_taps = 8, 167 .max_vscl_taps = 8, 168 .dpte_buffer_size_in_pte_reqs_luma = 64, 169 .dpte_buffer_size_in_pte_reqs_chroma = 34, 170 .dispclk_ramp_margin_percent = 1, 171 .max_inter_dcn_tile_repeaters = 8, 172 .cursor_buffer_size = 16, 173 .cursor_chunk_size = 2, 174 .writeback_line_buffer_buffer_size = 0, 175 .writeback_min_hscl_ratio = 1, 176 .writeback_min_vscl_ratio = 1, 177 .writeback_max_hscl_ratio = 1, 178 .writeback_max_vscl_ratio = 1, 179 .writeback_max_hscl_taps = 1, 180 .writeback_max_vscl_taps = 1, 181 .dppclk_delay_subtotal = 47, 182 .dppclk_delay_scl = 50, 183 .dppclk_delay_scl_lb_only = 16, 184 .dppclk_delay_cnvc_formatter = 28, 185 .dppclk_delay_cnvc_cursor = 6, 186 .dispclk_delay_subtotal = 125, 187 .dynamic_metadata_vm_enabled = false, 188 .odm_combine_4to1_supported = false, 189 .dcc_supported = true, 190 .max_num_dp2p0_outputs = 2, 191 .max_num_dp2p0_streams = 4, 192 }; 193 194 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 195 .clock_limits = { 196 { 197 .state = 0, 198 .dcfclk_mhz = 1564.0, 199 .fabricclk_mhz = 400.0, 200 .dispclk_mhz = 2150.0, 201 .dppclk_mhz = 2150.0, 202 .phyclk_mhz = 810.0, 203 .phyclk_d18_mhz = 667.0, 204 .phyclk_d32_mhz = 625.0, 205 .socclk_mhz = 1200.0, 206 .dscclk_mhz = 716.667, 207 .dram_speed_mts = 1600.0, 208 .dtbclk_mhz = 1564.0, 209 }, 210 }, 211 .num_states = 1, 212 .sr_exit_time_us = 5.20, 213 .sr_enter_plus_exit_time_us = 9.60, 214 .sr_exit_z8_time_us = 285.0, 215 .sr_enter_plus_exit_z8_time_us = 320, 216 .writeback_latency_us = 12.0, 217 .round_trip_ping_latency_dcfclk_cycles = 263, 218 .urgent_latency_pixel_data_only_us = 4.0, 219 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 220 .urgent_latency_vm_data_only_us = 4.0, 221 .fclk_change_latency_us = 20, 222 .usr_retraining_latency_us = 2, 223 .smn_latency_us = 2, 224 .mall_allocated_for_dcn_mbytes = 64, 225 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 226 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 227 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 228 .pct_ideal_sdp_bw_after_urgent = 100.0, 229 .pct_ideal_fabric_bw_after_urgent = 67.0, 230 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 231 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 232 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 233 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 234 .max_avg_sdp_bw_use_normal_percent = 80.0, 235 .max_avg_fabric_bw_use_normal_percent = 60.0, 236 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 237 .max_avg_dram_bw_use_normal_percent = 15.0, 238 .num_chans = 8, 239 .dram_channel_width_bytes = 2, 240 .fabric_datapath_to_dcn_data_return_bytes = 64, 241 .return_bus_width_bytes = 64, 242 .downspread_percent = 0.38, 243 .dcn_downspread_percent = 0.5, 244 .dram_clock_change_latency_us = 400, 245 .dispclk_dppclk_vco_speed_mhz = 4300.0, 246 .do_urgent_latency_adjustment = true, 247 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 248 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 249 }; 250 251 enum dcn321_clk_src_array_id { 252 DCN321_CLK_SRC_PLL0, 253 DCN321_CLK_SRC_PLL1, 254 DCN321_CLK_SRC_PLL2, 255 DCN321_CLK_SRC_PLL3, 256 DCN321_CLK_SRC_PLL4, 257 DCN321_CLK_SRC_TOTAL 258 }; 259 260 /* begin ********************* 261 * macros to expend register list macro defined in HW object header file 262 */ 263 264 /* DCN */ 265 /* TODO awful hack. fixup dcn20_dwb.h */ 266 #undef BASE_INNER 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 268 269 #define BASE(seg) BASE_INNER(seg) 270 271 #define SR(reg_name)\ 272 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 273 reg ## reg_name 274 275 #define SRI(reg_name, block, id)\ 276 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 277 reg ## block ## id ## _ ## reg_name 278 279 #define SRI2(reg_name, block, id)\ 280 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 281 reg ## reg_name 282 283 #define SRIR(var_name, reg_name, block, id)\ 284 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 285 reg ## block ## id ## _ ## reg_name 286 287 #define SRII(reg_name, block, id)\ 288 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 reg ## block ## id ## _ ## reg_name 290 291 #define SRII_MPC_RMU(reg_name, block, id)\ 292 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 293 reg ## block ## id ## _ ## reg_name 294 295 #define SRII_DWB(reg_name, temp_name, block, id)\ 296 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 297 reg ## block ## id ## _ ## temp_name 298 299 #define DCCG_SRII(reg_name, block, id)\ 300 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 301 reg ## block ## id ## _ ## reg_name 302 303 #define VUPDATE_SRII(reg_name, block, id)\ 304 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 305 reg ## reg_name ## _ ## block ## id 306 307 /* NBIO */ 308 #define NBIO_BASE_INNER(seg) \ 309 NBIO_BASE__INST0_SEG ## seg 310 311 #define NBIO_BASE(seg) \ 312 NBIO_BASE_INNER(seg) 313 314 #define NBIO_SR(reg_name)\ 315 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 316 regBIF_BX0_ ## reg_name 317 318 #define CTX ctx 319 #define REG(reg_name) \ 320 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 321 322 static const struct bios_registers bios_regs = { 323 NBIO_SR(BIOS_SCRATCH_3), 324 NBIO_SR(BIOS_SCRATCH_6) 325 }; 326 327 #define clk_src_regs(index, pllid)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E) 338 }; 339 340 static const struct dce110_clk_src_shift cs_shift = { 341 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 342 }; 343 344 static const struct dce110_clk_src_mask cs_mask = { 345 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 346 }; 347 348 #define abm_regs(id)\ 349 [id] = {\ 350 ABM_DCN32_REG_LIST(id)\ 351 } 352 353 static const struct dce_abm_registers abm_regs[] = { 354 abm_regs(0), 355 abm_regs(1), 356 abm_regs(2), 357 abm_regs(3), 358 }; 359 360 static const struct dce_abm_shift abm_shift = { 361 ABM_MASK_SH_LIST_DCN32(__SHIFT) 362 }; 363 364 static const struct dce_abm_mask abm_mask = { 365 ABM_MASK_SH_LIST_DCN32(_MASK) 366 }; 367 368 #define audio_regs(id)\ 369 [id] = {\ 370 AUD_COMMON_REG_LIST(id)\ 371 } 372 373 static const struct dce_audio_registers audio_regs[] = { 374 audio_regs(0), 375 audio_regs(1), 376 audio_regs(2), 377 audio_regs(3), 378 audio_regs(4) 379 }; 380 381 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 382 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 384 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 385 386 static const struct dce_audio_shift audio_shift = { 387 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 388 }; 389 390 static const struct dce_audio_mask audio_mask = { 391 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 392 }; 393 394 #define vpg_regs(id)\ 395 [id] = {\ 396 VPG_DCN3_REG_LIST(id)\ 397 } 398 399 static const struct dcn30_vpg_registers vpg_regs[] = { 400 vpg_regs(0), 401 vpg_regs(1), 402 vpg_regs(2), 403 vpg_regs(3), 404 vpg_regs(4), 405 vpg_regs(5), 406 vpg_regs(6), 407 vpg_regs(7), 408 vpg_regs(8), 409 vpg_regs(9), 410 }; 411 412 static const struct dcn30_vpg_shift vpg_shift = { 413 DCN3_VPG_MASK_SH_LIST(__SHIFT) 414 }; 415 416 static const struct dcn30_vpg_mask vpg_mask = { 417 DCN3_VPG_MASK_SH_LIST(_MASK) 418 }; 419 420 #define afmt_regs(id)\ 421 [id] = {\ 422 AFMT_DCN3_REG_LIST(id)\ 423 } 424 425 static const struct dcn30_afmt_registers afmt_regs[] = { 426 afmt_regs(0), 427 afmt_regs(1), 428 afmt_regs(2), 429 afmt_regs(3), 430 afmt_regs(4), 431 afmt_regs(5) 432 }; 433 434 static const struct dcn30_afmt_shift afmt_shift = { 435 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 436 }; 437 438 static const struct dcn30_afmt_mask afmt_mask = { 439 DCN3_AFMT_MASK_SH_LIST(_MASK) 440 }; 441 442 #define apg_regs(id)\ 443 [id] = {\ 444 APG_DCN31_REG_LIST(id)\ 445 } 446 447 static const struct dcn31_apg_registers apg_regs[] = { 448 apg_regs(0), 449 apg_regs(1), 450 apg_regs(2), 451 apg_regs(3) 452 }; 453 454 static const struct dcn31_apg_shift apg_shift = { 455 DCN31_APG_MASK_SH_LIST(__SHIFT) 456 }; 457 458 static const struct dcn31_apg_mask apg_mask = { 459 DCN31_APG_MASK_SH_LIST(_MASK) 460 }; 461 462 #define stream_enc_regs(id)\ 463 [id] = {\ 464 SE_DCN32_REG_LIST(id)\ 465 } 466 467 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 468 stream_enc_regs(0), 469 stream_enc_regs(1), 470 stream_enc_regs(2), 471 stream_enc_regs(3), 472 stream_enc_regs(4) 473 }; 474 475 static const struct dcn10_stream_encoder_shift se_shift = { 476 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 477 }; 478 479 static const struct dcn10_stream_encoder_mask se_mask = { 480 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 481 }; 482 483 484 #define aux_regs(id)\ 485 [id] = {\ 486 DCN2_AUX_REG_LIST(id)\ 487 } 488 489 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 490 aux_regs(0), 491 aux_regs(1), 492 aux_regs(2), 493 aux_regs(3), 494 aux_regs(4) 495 }; 496 497 #define hpd_regs(id)\ 498 [id] = {\ 499 HPD_REG_LIST(id)\ 500 } 501 502 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 503 hpd_regs(0), 504 hpd_regs(1), 505 hpd_regs(2), 506 hpd_regs(3), 507 hpd_regs(4) 508 }; 509 510 #define link_regs(id, phyid)\ 511 [id] = {\ 512 LE_DCN31_REG_LIST(id), \ 513 UNIPHY_DCN2_REG_LIST(phyid), \ 514 /*DPCS_DCN31_REG_LIST(id),*/ \ 515 } 516 517 static const struct dcn10_link_enc_registers link_enc_regs[] = { 518 link_regs(0, A), 519 link_regs(1, B), 520 link_regs(2, C), 521 link_regs(3, D), 522 link_regs(4, E) 523 }; 524 525 static const struct dcn10_link_enc_shift le_shift = { 526 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 527 // DPCS_DCN31_MASK_SH_LIST(__SHIFT) 528 }; 529 530 static const struct dcn10_link_enc_mask le_mask = { 531 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 532 // DPCS_DCN31_MASK_SH_LIST(_MASK) 533 }; 534 535 #define hpo_dp_stream_encoder_reg_list(id)\ 536 [id] = {\ 537 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 538 } 539 540 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 541 hpo_dp_stream_encoder_reg_list(0), 542 hpo_dp_stream_encoder_reg_list(1), 543 hpo_dp_stream_encoder_reg_list(2), 544 hpo_dp_stream_encoder_reg_list(3), 545 }; 546 547 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 548 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 549 }; 550 551 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 552 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 553 }; 554 555 556 #define hpo_dp_link_encoder_reg_list(id)\ 557 [id] = {\ 558 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 559 /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ 560 /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ 561 /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ 562 /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ 563 /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ 564 } 565 566 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 567 hpo_dp_link_encoder_reg_list(0), 568 hpo_dp_link_encoder_reg_list(1), 569 }; 570 571 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 572 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 573 }; 574 575 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 576 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 577 }; 578 579 #define dpp_regs(id)\ 580 [id] = {\ 581 DPP_REG_LIST_DCN30_COMMON(id),\ 582 } 583 584 static const struct dcn3_dpp_registers dpp_regs[] = { 585 dpp_regs(0), 586 dpp_regs(1), 587 dpp_regs(2), 588 dpp_regs(3) 589 }; 590 591 static const struct dcn3_dpp_shift tf_shift = { 592 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 593 }; 594 595 static const struct dcn3_dpp_mask tf_mask = { 596 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 597 }; 598 599 600 #define opp_regs(id)\ 601 [id] = {\ 602 OPP_REG_LIST_DCN30(id),\ 603 } 604 605 static const struct dcn20_opp_registers opp_regs[] = { 606 opp_regs(0), 607 opp_regs(1), 608 opp_regs(2), 609 opp_regs(3) 610 }; 611 612 static const struct dcn20_opp_shift opp_shift = { 613 OPP_MASK_SH_LIST_DCN20(__SHIFT) 614 }; 615 616 static const struct dcn20_opp_mask opp_mask = { 617 OPP_MASK_SH_LIST_DCN20(_MASK) 618 }; 619 620 #define aux_engine_regs(id)\ 621 [id] = {\ 622 AUX_COMMON_REG_LIST0(id), \ 623 .AUXN_IMPCAL = 0, \ 624 .AUXP_IMPCAL = 0, \ 625 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 626 } 627 628 static const struct dce110_aux_registers aux_engine_regs[] = { 629 aux_engine_regs(0), 630 aux_engine_regs(1), 631 aux_engine_regs(2), 632 aux_engine_regs(3), 633 aux_engine_regs(4) 634 }; 635 636 static const struct dce110_aux_registers_shift aux_shift = { 637 DCN_AUX_MASK_SH_LIST(__SHIFT) 638 }; 639 640 static const struct dce110_aux_registers_mask aux_mask = { 641 DCN_AUX_MASK_SH_LIST(_MASK) 642 }; 643 644 645 #define dwbc_regs_dcn3(id)\ 646 [id] = {\ 647 DWBC_COMMON_REG_LIST_DCN30(id),\ 648 } 649 650 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 651 dwbc_regs_dcn3(0), 652 }; 653 654 static const struct dcn30_dwbc_shift dwbc30_shift = { 655 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 656 }; 657 658 static const struct dcn30_dwbc_mask dwbc30_mask = { 659 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 660 }; 661 662 #define mcif_wb_regs_dcn3(id)\ 663 [id] = {\ 664 MCIF_WB_COMMON_REG_LIST_DCN32(id),\ 665 } 666 667 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 668 mcif_wb_regs_dcn3(0) 669 }; 670 671 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 672 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 673 }; 674 675 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 676 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 677 }; 678 679 #define dsc_regsDCN20(id)\ 680 [id] = {\ 681 DSC_REG_LIST_DCN20(id)\ 682 } 683 684 static const struct dcn20_dsc_registers dsc_regs[] = { 685 dsc_regsDCN20(0), 686 dsc_regsDCN20(1), 687 dsc_regsDCN20(2), 688 dsc_regsDCN20(3) 689 }; 690 691 static const struct dcn20_dsc_shift dsc_shift = { 692 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 693 }; 694 695 static const struct dcn20_dsc_mask dsc_mask = { 696 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 697 }; 698 699 static const struct dcn30_mpc_registers mpc_regs = { 700 MPC_REG_LIST_DCN3_2(0), 701 MPC_REG_LIST_DCN3_2(1), 702 MPC_REG_LIST_DCN3_2(2), 703 MPC_REG_LIST_DCN3_2(3), 704 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 705 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 706 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 707 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 708 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 709 }; 710 711 static const struct dcn30_mpc_shift mpc_shift = { 712 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 713 }; 714 715 static const struct dcn30_mpc_mask mpc_mask = { 716 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 717 }; 718 719 #define optc_regs(id)\ 720 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} 721 722 static const struct dcn_optc_registers optc_regs[] = { 723 optc_regs(0), 724 optc_regs(1), 725 optc_regs(2), 726 optc_regs(3) 727 }; 728 729 static const struct dcn_optc_shift optc_shift = { 730 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 731 }; 732 733 static const struct dcn_optc_mask optc_mask = { 734 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 735 }; 736 737 #define hubp_regs(id)\ 738 [id] = {\ 739 HUBP_REG_LIST_DCN32(id)\ 740 } 741 742 static const struct dcn_hubp2_registers hubp_regs[] = { 743 hubp_regs(0), 744 hubp_regs(1), 745 hubp_regs(2), 746 hubp_regs(3) 747 }; 748 749 750 static const struct dcn_hubp2_shift hubp_shift = { 751 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 752 }; 753 754 static const struct dcn_hubp2_mask hubp_mask = { 755 HUBP_MASK_SH_LIST_DCN32(_MASK) 756 }; 757 static const struct dcn_hubbub_registers hubbub_reg = { 758 HUBBUB_REG_LIST_DCN32(0) 759 }; 760 761 static const struct dcn_hubbub_shift hubbub_shift = { 762 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 763 }; 764 765 static const struct dcn_hubbub_mask hubbub_mask = { 766 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 767 }; 768 769 static const struct dccg_registers dccg_regs = { 770 DCCG_REG_LIST_DCN32() 771 }; 772 773 static const struct dccg_shift dccg_shift = { 774 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 775 }; 776 777 static const struct dccg_mask dccg_mask = { 778 DCCG_MASK_SH_LIST_DCN32(_MASK) 779 }; 780 781 782 #define SRII2(reg_name_pre, reg_name_post, id)\ 783 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 784 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 785 reg ## reg_name_pre ## id ## _ ## reg_name_post 786 787 788 #define HWSEQ_DCN32_REG_LIST()\ 789 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 790 SR(DIO_MEM_PWR_CTRL), \ 791 SR(ODM_MEM_PWR_CTRL3), \ 792 SR(MMHUBBUB_MEM_PWR_CNTL), \ 793 SR(DCCG_GATE_DISABLE_CNTL), \ 794 SR(DCCG_GATE_DISABLE_CNTL2), \ 795 SR(DCFCLK_CNTL),\ 796 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 797 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 798 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 799 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 800 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 801 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 802 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 803 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 804 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 805 SR(MICROSECOND_TIME_BASE_DIV), \ 806 SR(MILLISECOND_TIME_BASE_DIV), \ 807 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 808 SR(RBBMIF_TIMEOUT_DIS), \ 809 SR(RBBMIF_TIMEOUT_DIS_2), \ 810 SR(DCHUBBUB_CRC_CTRL), \ 811 SR(DPP_TOP0_DPP_CRC_CTRL), \ 812 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 813 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 814 SR(MPC_CRC_CTRL), \ 815 SR(MPC_CRC_RESULT_GB), \ 816 SR(MPC_CRC_RESULT_C), \ 817 SR(MPC_CRC_RESULT_AR), \ 818 SR(DOMAIN0_PG_CONFIG), \ 819 SR(DOMAIN1_PG_CONFIG), \ 820 SR(DOMAIN2_PG_CONFIG), \ 821 SR(DOMAIN3_PG_CONFIG), \ 822 SR(DOMAIN16_PG_CONFIG), \ 823 SR(DOMAIN17_PG_CONFIG), \ 824 SR(DOMAIN18_PG_CONFIG), \ 825 SR(DOMAIN19_PG_CONFIG), \ 826 SR(DOMAIN0_PG_STATUS), \ 827 SR(DOMAIN1_PG_STATUS), \ 828 SR(DOMAIN2_PG_STATUS), \ 829 SR(DOMAIN3_PG_STATUS), \ 830 SR(DOMAIN16_PG_STATUS), \ 831 SR(DOMAIN17_PG_STATUS), \ 832 SR(DOMAIN18_PG_STATUS), \ 833 SR(DOMAIN19_PG_STATUS), \ 834 SR(D1VGA_CONTROL), \ 835 SR(D2VGA_CONTROL), \ 836 SR(D3VGA_CONTROL), \ 837 SR(D4VGA_CONTROL), \ 838 SR(D5VGA_CONTROL), \ 839 SR(D6VGA_CONTROL), \ 840 SR(DC_IP_REQUEST_CNTL), \ 841 SR(AZALIA_AUDIO_DTO), \ 842 SR(AZALIA_CONTROLLER_CLOCK_GATING) 843 844 static const struct dce_hwseq_registers hwseq_reg = { 845 HWSEQ_DCN32_REG_LIST() 846 }; 847 848 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 849 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 850 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 851 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 852 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 853 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 854 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 855 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 856 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 857 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 858 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 859 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 860 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 861 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 862 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 863 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 864 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 865 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 866 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 867 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 868 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 869 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 870 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 871 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 872 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 873 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 874 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 875 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 876 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 877 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 878 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 879 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 880 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 881 882 static const struct dce_hwseq_shift hwseq_shift = { 883 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 884 }; 885 886 static const struct dce_hwseq_mask hwseq_mask = { 887 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 888 }; 889 #define vmid_regs(id)\ 890 [id] = {\ 891 DCN20_VMID_REG_LIST(id)\ 892 } 893 894 static const struct dcn_vmid_registers vmid_regs[] = { 895 vmid_regs(0), 896 vmid_regs(1), 897 vmid_regs(2), 898 vmid_regs(3), 899 vmid_regs(4), 900 vmid_regs(5), 901 vmid_regs(6), 902 vmid_regs(7), 903 vmid_regs(8), 904 vmid_regs(9), 905 vmid_regs(10), 906 vmid_regs(11), 907 vmid_regs(12), 908 vmid_regs(13), 909 vmid_regs(14), 910 vmid_regs(15) 911 }; 912 913 static const struct dcn20_vmid_shift vmid_shifts = { 914 DCN20_VMID_MASK_SH_LIST(__SHIFT) 915 }; 916 917 static const struct dcn20_vmid_mask vmid_masks = { 918 DCN20_VMID_MASK_SH_LIST(_MASK) 919 }; 920 921 static const struct resource_caps res_cap_dcn321 = { 922 .num_timing_generator = 4, 923 .num_opp = 4, 924 .num_video_plane = 4, 925 .num_audio = 5, 926 .num_stream_encoder = 5, 927 .num_hpo_dp_stream_encoder = 4, 928 .num_hpo_dp_link_encoder = 2, 929 .num_pll = 5, 930 .num_dwb = 1, 931 .num_ddc = 5, 932 .num_vmid = 16, 933 .num_mpc_3dlut = 4, 934 .num_dsc = 4, 935 }; 936 937 static const struct dc_plane_cap plane_cap = { 938 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 939 .blends_with_above = true, 940 .blends_with_below = true, 941 .per_pixel_alpha = true, 942 943 .pixel_format_support = { 944 .argb8888 = true, 945 .nv12 = true, 946 .fp16 = true, 947 .p010 = true, 948 .ayuv = false, 949 }, 950 951 .max_upscale_factor = { 952 .argb8888 = 16000, 953 .nv12 = 16000, 954 .fp16 = 16000 955 }, 956 957 // 6:1 downscaling ratio: 1000/6 = 166.666 958 .max_downscale_factor = { 959 .argb8888 = 167, 960 .nv12 = 167, 961 .fp16 = 167 962 }, 963 64, 964 64 965 }; 966 967 static const struct dc_debug_options debug_defaults_drv = { 968 .disable_dmcu = true, 969 .force_abm_enable = false, 970 .timing_trace = false, 971 .clock_trace = true, 972 .disable_pplib_clock_request = false, 973 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 974 .force_single_disp_pipe_split = false, 975 .disable_dcc = DCC_ENABLE, 976 .vsr_support = true, 977 .performance_trace = false, 978 .max_downscale_src_width = 7680,/*upto 8K*/ 979 .disable_pplib_wm_range = false, 980 .scl_reset_length10 = true, 981 .sanity_checks = false, 982 .underflow_assert_delay_us = 0xFFFFFFFF, 983 .dwb_fi_phase = -1, // -1 = disable, 984 .dmub_command_table = true, 985 .enable_mem_low_power = { 986 .bits = { 987 .vga = false, 988 .i2c = false, 989 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 990 .dscl = false, 991 .cm = false, 992 .mpc = false, 993 .optc = true, 994 } 995 }, 996 .use_max_lb = true, 997 .force_disable_subvp = true, 998 .enable_single_display_2to1_odm_policy = true, 999 .enable_dp_dig_pixel_rate_div_policy = 1, 1000 }; 1001 1002 static const struct dc_debug_options debug_defaults_diags = { 1003 .disable_dmcu = true, 1004 .force_abm_enable = false, 1005 .timing_trace = true, 1006 .clock_trace = true, 1007 .disable_dpp_power_gate = true, 1008 .disable_hubp_power_gate = true, 1009 .disable_dsc_power_gate = true, 1010 .disable_clock_gate = true, 1011 .disable_pplib_clock_request = true, 1012 .disable_pplib_wm_range = true, 1013 .disable_stutter = false, 1014 .scl_reset_length10 = true, 1015 .dwb_fi_phase = -1, // -1 = disable 1016 .dmub_command_table = true, 1017 .enable_tri_buf = true, 1018 .use_max_lb = true, 1019 .force_disable_subvp = true 1020 }; 1021 1022 1023 static struct dce_aux *dcn321_aux_engine_create( 1024 struct dc_context *ctx, 1025 uint32_t inst) 1026 { 1027 struct aux_engine_dce110 *aux_engine = 1028 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1029 1030 if (!aux_engine) 1031 return NULL; 1032 1033 dce110_aux_engine_construct(aux_engine, ctx, inst, 1034 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1035 &aux_engine_regs[inst], 1036 &aux_mask, 1037 &aux_shift, 1038 ctx->dc->caps.extended_aux_timeout_support); 1039 1040 return &aux_engine->base; 1041 } 1042 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1043 1044 static const struct dce_i2c_registers i2c_hw_regs[] = { 1045 i2c_inst_regs(1), 1046 i2c_inst_regs(2), 1047 i2c_inst_regs(3), 1048 i2c_inst_regs(4), 1049 i2c_inst_regs(5), 1050 }; 1051 1052 static const struct dce_i2c_shift i2c_shifts = { 1053 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1054 }; 1055 1056 static const struct dce_i2c_mask i2c_masks = { 1057 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1058 }; 1059 1060 static struct dce_i2c_hw *dcn321_i2c_hw_create( 1061 struct dc_context *ctx, 1062 uint32_t inst) 1063 { 1064 struct dce_i2c_hw *dce_i2c_hw = 1065 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1066 1067 if (!dce_i2c_hw) 1068 return NULL; 1069 1070 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1071 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1072 1073 return dce_i2c_hw; 1074 } 1075 1076 static struct clock_source *dcn321_clock_source_create( 1077 struct dc_context *ctx, 1078 struct dc_bios *bios, 1079 enum clock_source_id id, 1080 const struct dce110_clk_src_regs *regs, 1081 bool dp_clk_src) 1082 { 1083 struct dce110_clk_src *clk_src = 1084 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1085 1086 if (!clk_src) 1087 return NULL; 1088 1089 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1090 regs, &cs_shift, &cs_mask)) { 1091 clk_src->base.dp_clk_src = dp_clk_src; 1092 return &clk_src->base; 1093 } 1094 1095 BREAK_TO_DEBUGGER(); 1096 return NULL; 1097 } 1098 1099 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) 1100 { 1101 int i; 1102 1103 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 1104 GFP_KERNEL); 1105 1106 if (!hubbub2) 1107 return NULL; 1108 1109 hubbub32_construct(hubbub2, ctx, 1110 &hubbub_reg, 1111 &hubbub_shift, 1112 &hubbub_mask, 1113 ctx->dc->dml.ip.det_buffer_size_kbytes, 1114 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 1115 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 1116 1117 1118 for (i = 0; i < res_cap_dcn321.num_vmid; i++) { 1119 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 1120 1121 vmid->ctx = ctx; 1122 1123 vmid->regs = &vmid_regs[i]; 1124 vmid->shifts = &vmid_shifts; 1125 vmid->masks = &vmid_masks; 1126 } 1127 1128 return &hubbub2->base; 1129 } 1130 1131 static struct hubp *dcn321_hubp_create( 1132 struct dc_context *ctx, 1133 uint32_t inst) 1134 { 1135 struct dcn20_hubp *hubp2 = 1136 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1137 1138 if (!hubp2) 1139 return NULL; 1140 1141 if (hubp32_construct(hubp2, ctx, inst, 1142 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1143 return &hubp2->base; 1144 1145 BREAK_TO_DEBUGGER(); 1146 kfree(hubp2); 1147 return NULL; 1148 } 1149 1150 static void dcn321_dpp_destroy(struct dpp **dpp) 1151 { 1152 kfree(TO_DCN30_DPP(*dpp)); 1153 *dpp = NULL; 1154 } 1155 1156 static struct dpp *dcn321_dpp_create( 1157 struct dc_context *ctx, 1158 uint32_t inst) 1159 { 1160 struct dcn3_dpp *dpp3 = 1161 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1162 1163 if (!dpp3) 1164 return NULL; 1165 1166 if (dpp32_construct(dpp3, ctx, inst, 1167 &dpp_regs[inst], &tf_shift, &tf_mask)) 1168 return &dpp3->base; 1169 1170 BREAK_TO_DEBUGGER(); 1171 kfree(dpp3); 1172 return NULL; 1173 } 1174 1175 static struct mpc *dcn321_mpc_create( 1176 struct dc_context *ctx, 1177 int num_mpcc, 1178 int num_rmu) 1179 { 1180 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1181 GFP_KERNEL); 1182 1183 if (!mpc30) 1184 return NULL; 1185 1186 dcn32_mpc_construct(mpc30, ctx, 1187 &mpc_regs, 1188 &mpc_shift, 1189 &mpc_mask, 1190 num_mpcc, 1191 num_rmu); 1192 1193 return &mpc30->base; 1194 } 1195 1196 static struct output_pixel_processor *dcn321_opp_create( 1197 struct dc_context *ctx, uint32_t inst) 1198 { 1199 struct dcn20_opp *opp2 = 1200 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1201 1202 if (!opp2) { 1203 BREAK_TO_DEBUGGER(); 1204 return NULL; 1205 } 1206 1207 dcn20_opp_construct(opp2, ctx, inst, 1208 &opp_regs[inst], &opp_shift, &opp_mask); 1209 return &opp2->base; 1210 } 1211 1212 1213 static struct timing_generator *dcn321_timing_generator_create( 1214 struct dc_context *ctx, 1215 uint32_t instance) 1216 { 1217 struct optc *tgn10 = 1218 kzalloc(sizeof(struct optc), GFP_KERNEL); 1219 1220 if (!tgn10) 1221 return NULL; 1222 1223 tgn10->base.inst = instance; 1224 tgn10->base.ctx = ctx; 1225 1226 tgn10->tg_regs = &optc_regs[instance]; 1227 tgn10->tg_shift = &optc_shift; 1228 tgn10->tg_mask = &optc_mask; 1229 1230 dcn32_timing_generator_init(tgn10); 1231 1232 return &tgn10->base; 1233 } 1234 1235 static const struct encoder_feature_support link_enc_feature = { 1236 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1237 .max_hdmi_pixel_clock = 600000, 1238 .hdmi_ycbcr420_supported = true, 1239 .dp_ycbcr420_supported = true, 1240 .fec_supported = true, 1241 .flags.bits.IS_HBR2_CAPABLE = true, 1242 .flags.bits.IS_HBR3_CAPABLE = true, 1243 .flags.bits.IS_TPS3_CAPABLE = true, 1244 .flags.bits.IS_TPS4_CAPABLE = true 1245 }; 1246 1247 static struct link_encoder *dcn321_link_encoder_create( 1248 const struct encoder_init_data *enc_init_data) 1249 { 1250 struct dcn20_link_encoder *enc20 = 1251 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1252 1253 if (!enc20) 1254 return NULL; 1255 1256 dcn321_link_encoder_construct(enc20, 1257 enc_init_data, 1258 &link_enc_feature, 1259 &link_enc_regs[enc_init_data->transmitter], 1260 &link_enc_aux_regs[enc_init_data->channel - 1], 1261 &link_enc_hpd_regs[enc_init_data->hpd_source], 1262 &le_shift, 1263 &le_mask); 1264 1265 return &enc20->enc10.base; 1266 } 1267 1268 static void read_dce_straps( 1269 struct dc_context *ctx, 1270 struct resource_straps *straps) 1271 { 1272 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1273 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1274 1275 } 1276 1277 static struct audio *dcn321_create_audio( 1278 struct dc_context *ctx, unsigned int inst) 1279 { 1280 return dce_audio_create(ctx, inst, 1281 &audio_regs[inst], &audio_shift, &audio_mask); 1282 } 1283 1284 static struct vpg *dcn321_vpg_create( 1285 struct dc_context *ctx, 1286 uint32_t inst) 1287 { 1288 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1289 1290 if (!vpg3) 1291 return NULL; 1292 1293 vpg3_construct(vpg3, ctx, inst, 1294 &vpg_regs[inst], 1295 &vpg_shift, 1296 &vpg_mask); 1297 1298 return &vpg3->base; 1299 } 1300 1301 static struct afmt *dcn321_afmt_create( 1302 struct dc_context *ctx, 1303 uint32_t inst) 1304 { 1305 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1306 1307 if (!afmt3) 1308 return NULL; 1309 1310 afmt3_construct(afmt3, ctx, inst, 1311 &afmt_regs[inst], 1312 &afmt_shift, 1313 &afmt_mask); 1314 1315 return &afmt3->base; 1316 } 1317 1318 static struct apg *dcn321_apg_create( 1319 struct dc_context *ctx, 1320 uint32_t inst) 1321 { 1322 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1323 1324 if (!apg31) 1325 return NULL; 1326 1327 apg31_construct(apg31, ctx, inst, 1328 &apg_regs[inst], 1329 &apg_shift, 1330 &apg_mask); 1331 1332 return &apg31->base; 1333 } 1334 1335 static struct stream_encoder *dcn321_stream_encoder_create( 1336 enum engine_id eng_id, 1337 struct dc_context *ctx) 1338 { 1339 struct dcn10_stream_encoder *enc1; 1340 struct vpg *vpg; 1341 struct afmt *afmt; 1342 int vpg_inst; 1343 int afmt_inst; 1344 1345 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1346 if (eng_id <= ENGINE_ID_DIGF) { 1347 vpg_inst = eng_id; 1348 afmt_inst = eng_id; 1349 } else 1350 return NULL; 1351 1352 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1353 vpg = dcn321_vpg_create(ctx, vpg_inst); 1354 afmt = dcn321_afmt_create(ctx, afmt_inst); 1355 1356 if (!enc1 || !vpg || !afmt) { 1357 kfree(enc1); 1358 kfree(vpg); 1359 kfree(afmt); 1360 return NULL; 1361 } 1362 1363 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1364 eng_id, vpg, afmt, 1365 &stream_enc_regs[eng_id], 1366 &se_shift, &se_mask); 1367 1368 return &enc1->base; 1369 } 1370 1371 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( 1372 enum engine_id eng_id, 1373 struct dc_context *ctx) 1374 { 1375 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1376 struct vpg *vpg; 1377 struct apg *apg; 1378 uint32_t hpo_dp_inst; 1379 uint32_t vpg_inst; 1380 uint32_t apg_inst; 1381 1382 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1383 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1384 1385 /* Mapping of VPG register blocks to HPO DP block instance: 1386 * VPG[6] -> HPO_DP[0] 1387 * VPG[7] -> HPO_DP[1] 1388 * VPG[8] -> HPO_DP[2] 1389 * VPG[9] -> HPO_DP[3] 1390 */ 1391 vpg_inst = hpo_dp_inst + 6; 1392 1393 /* Mapping of APG register blocks to HPO DP block instance: 1394 * APG[0] -> HPO_DP[0] 1395 * APG[1] -> HPO_DP[1] 1396 * APG[2] -> HPO_DP[2] 1397 * APG[3] -> HPO_DP[3] 1398 */ 1399 apg_inst = hpo_dp_inst; 1400 1401 /* allocate HPO stream encoder and create VPG sub-block */ 1402 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1403 vpg = dcn321_vpg_create(ctx, vpg_inst); 1404 apg = dcn321_apg_create(ctx, apg_inst); 1405 1406 if (!hpo_dp_enc31 || !vpg || !apg) { 1407 kfree(hpo_dp_enc31); 1408 kfree(vpg); 1409 kfree(apg); 1410 return NULL; 1411 } 1412 1413 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1414 hpo_dp_inst, eng_id, vpg, apg, 1415 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1416 &hpo_dp_se_shift, &hpo_dp_se_mask); 1417 1418 return &hpo_dp_enc31->base; 1419 } 1420 1421 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( 1422 uint8_t inst, 1423 struct dc_context *ctx) 1424 { 1425 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1426 1427 /* allocate HPO link encoder */ 1428 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1429 1430 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1431 &hpo_dp_link_enc_regs[inst], 1432 &hpo_dp_le_shift, &hpo_dp_le_mask); 1433 1434 return &hpo_dp_enc31->base; 1435 } 1436 1437 static struct dce_hwseq *dcn321_hwseq_create( 1438 struct dc_context *ctx) 1439 { 1440 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1441 1442 if (hws) { 1443 hws->ctx = ctx; 1444 hws->regs = &hwseq_reg; 1445 hws->shifts = &hwseq_shift; 1446 hws->masks = &hwseq_mask; 1447 } 1448 return hws; 1449 } 1450 static const struct resource_create_funcs res_create_funcs = { 1451 .read_dce_straps = read_dce_straps, 1452 .create_audio = dcn321_create_audio, 1453 .create_stream_encoder = dcn321_stream_encoder_create, 1454 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1455 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1456 .create_hwseq = dcn321_hwseq_create, 1457 }; 1458 1459 static const struct resource_create_funcs res_create_maximus_funcs = { 1460 .read_dce_straps = NULL, 1461 .create_audio = NULL, 1462 .create_stream_encoder = NULL, 1463 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, 1464 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, 1465 .create_hwseq = dcn321_hwseq_create, 1466 }; 1467 1468 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) 1469 { 1470 unsigned int i; 1471 1472 for (i = 0; i < pool->base.stream_enc_count; i++) { 1473 if (pool->base.stream_enc[i] != NULL) { 1474 if (pool->base.stream_enc[i]->vpg != NULL) { 1475 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1476 pool->base.stream_enc[i]->vpg = NULL; 1477 } 1478 if (pool->base.stream_enc[i]->afmt != NULL) { 1479 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1480 pool->base.stream_enc[i]->afmt = NULL; 1481 } 1482 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1483 pool->base.stream_enc[i] = NULL; 1484 } 1485 } 1486 1487 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1488 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1489 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1490 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1491 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1492 } 1493 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1494 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1495 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1496 } 1497 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1498 pool->base.hpo_dp_stream_enc[i] = NULL; 1499 } 1500 } 1501 1502 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1503 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1504 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1505 pool->base.hpo_dp_link_enc[i] = NULL; 1506 } 1507 } 1508 1509 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1510 if (pool->base.dscs[i] != NULL) 1511 dcn20_dsc_destroy(&pool->base.dscs[i]); 1512 } 1513 1514 if (pool->base.mpc != NULL) { 1515 kfree(TO_DCN20_MPC(pool->base.mpc)); 1516 pool->base.mpc = NULL; 1517 } 1518 if (pool->base.hubbub != NULL) { 1519 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1520 pool->base.hubbub = NULL; 1521 } 1522 for (i = 0; i < pool->base.pipe_count; i++) { 1523 if (pool->base.dpps[i] != NULL) 1524 dcn321_dpp_destroy(&pool->base.dpps[i]); 1525 1526 if (pool->base.ipps[i] != NULL) 1527 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1528 1529 if (pool->base.hubps[i] != NULL) { 1530 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1531 pool->base.hubps[i] = NULL; 1532 } 1533 1534 if (pool->base.irqs != NULL) 1535 dal_irq_service_destroy(&pool->base.irqs); 1536 } 1537 1538 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1539 if (pool->base.engines[i] != NULL) 1540 dce110_engine_destroy(&pool->base.engines[i]); 1541 if (pool->base.hw_i2cs[i] != NULL) { 1542 kfree(pool->base.hw_i2cs[i]); 1543 pool->base.hw_i2cs[i] = NULL; 1544 } 1545 if (pool->base.sw_i2cs[i] != NULL) { 1546 kfree(pool->base.sw_i2cs[i]); 1547 pool->base.sw_i2cs[i] = NULL; 1548 } 1549 } 1550 1551 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1552 if (pool->base.opps[i] != NULL) 1553 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1554 } 1555 1556 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1557 if (pool->base.timing_generators[i] != NULL) { 1558 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1559 pool->base.timing_generators[i] = NULL; 1560 } 1561 } 1562 1563 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1564 if (pool->base.dwbc[i] != NULL) { 1565 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1566 pool->base.dwbc[i] = NULL; 1567 } 1568 if (pool->base.mcif_wb[i] != NULL) { 1569 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1570 pool->base.mcif_wb[i] = NULL; 1571 } 1572 } 1573 1574 for (i = 0; i < pool->base.audio_count; i++) { 1575 if (pool->base.audios[i]) 1576 dce_aud_destroy(&pool->base.audios[i]); 1577 } 1578 1579 for (i = 0; i < pool->base.clk_src_count; i++) { 1580 if (pool->base.clock_sources[i] != NULL) { 1581 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1582 pool->base.clock_sources[i] = NULL; 1583 } 1584 } 1585 1586 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1587 if (pool->base.mpc_lut[i] != NULL) { 1588 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1589 pool->base.mpc_lut[i] = NULL; 1590 } 1591 if (pool->base.mpc_shaper[i] != NULL) { 1592 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1593 pool->base.mpc_shaper[i] = NULL; 1594 } 1595 } 1596 1597 if (pool->base.dp_clock_source != NULL) { 1598 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1599 pool->base.dp_clock_source = NULL; 1600 } 1601 1602 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1603 if (pool->base.multiple_abms[i] != NULL) 1604 dce_abm_destroy(&pool->base.multiple_abms[i]); 1605 } 1606 1607 if (pool->base.psr != NULL) 1608 dmub_psr_destroy(&pool->base.psr); 1609 1610 if (pool->base.dccg != NULL) 1611 dcn_dccg_destroy(&pool->base.dccg); 1612 1613 if (pool->base.oem_device != NULL) 1614 dal_ddc_service_destroy(&pool->base.oem_device); 1615 } 1616 1617 1618 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1619 { 1620 int i; 1621 uint32_t dwb_count = pool->res_cap->num_dwb; 1622 1623 for (i = 0; i < dwb_count; i++) { 1624 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1625 GFP_KERNEL); 1626 1627 if (!dwbc30) { 1628 dm_error("DC: failed to create dwbc30!\n"); 1629 return false; 1630 } 1631 1632 dcn30_dwbc_construct(dwbc30, ctx, 1633 &dwbc30_regs[i], 1634 &dwbc30_shift, 1635 &dwbc30_mask, 1636 i); 1637 1638 pool->dwbc[i] = &dwbc30->base; 1639 } 1640 return true; 1641 } 1642 1643 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1644 { 1645 int i; 1646 uint32_t dwb_count = pool->res_cap->num_dwb; 1647 1648 for (i = 0; i < dwb_count; i++) { 1649 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1650 GFP_KERNEL); 1651 1652 if (!mcif_wb30) { 1653 dm_error("DC: failed to create mcif_wb30!\n"); 1654 return false; 1655 } 1656 1657 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1658 &mcif_wb30_regs[i], 1659 &mcif_wb30_shift, 1660 &mcif_wb30_mask, 1661 i); 1662 1663 pool->mcif_wb[i] = &mcif_wb30->base; 1664 } 1665 return true; 1666 } 1667 1668 static struct display_stream_compressor *dcn321_dsc_create( 1669 struct dc_context *ctx, uint32_t inst) 1670 { 1671 struct dcn20_dsc *dsc = 1672 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1673 1674 if (!dsc) { 1675 BREAK_TO_DEBUGGER(); 1676 return NULL; 1677 } 1678 1679 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1680 1681 dsc->max_image_width = 6016; 1682 1683 return &dsc->base; 1684 } 1685 1686 static void dcn321_destroy_resource_pool(struct resource_pool **pool) 1687 { 1688 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); 1689 1690 dcn321_resource_destruct(dcn321_pool); 1691 kfree(dcn321_pool); 1692 *pool = NULL; 1693 } 1694 1695 static struct dc_cap_funcs cap_funcs = { 1696 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1697 }; 1698 1699 1700 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1701 unsigned int *optimal_dcfclk, 1702 unsigned int *optimal_fclk) 1703 { 1704 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1705 1706 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * 1707 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); 1708 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * 1709 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); 1710 1711 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1712 1713 if (optimal_fclk) 1714 *optimal_fclk = bw_from_dram / 1715 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1716 1717 if (optimal_dcfclk) 1718 *optimal_dcfclk = bw_from_dram / 1719 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1720 } 1721 1722 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 1723 { 1724 if (entry->dcfclk_mhz > 0) { 1725 float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 1726 1727 entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 1728 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * 1729 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 1730 } else if (entry->fabricclk_mhz > 0) { 1731 float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 1732 1733 entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 1734 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * 1735 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 1736 } else if (entry->dram_speed_mts > 0) { 1737 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * 1738 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 1739 1740 entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 1741 entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 1742 } 1743 } 1744 1745 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 1746 { 1747 float memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * 1748 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 1749 1750 float fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 1751 1752 float sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 1753 1754 float limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 1755 1756 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 1757 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 1758 1759 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 1760 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 1761 1762 return limiting_bw_kbytes_sec; 1763 } 1764 1765 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 1766 struct _vcs_dpi_voltage_scaling_st *entry) 1767 { 1768 int index = 0; 1769 int i = 0; 1770 float net_bw_of_new_state = 0; 1771 1772 if (*num_entries == 0) { 1773 table[0] = *entry; 1774 (*num_entries)++; 1775 } else { 1776 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 1777 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 1778 index++; 1779 if (index >= *num_entries) 1780 break; 1781 } 1782 1783 for (i = *num_entries; i > index; i--) { 1784 table[i] = table[i - 1]; 1785 } 1786 1787 table[index] = *entry; 1788 (*num_entries)++; 1789 } 1790 } 1791 1792 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 1793 unsigned int index) 1794 { 1795 int i; 1796 1797 if (*num_entries == 0) 1798 return; 1799 1800 for (i = index; i < *num_entries - 1; i++) { 1801 table[i] = table[i + 1]; 1802 } 1803 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 1804 } 1805 1806 static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 1807 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 1808 { 1809 int i, j; 1810 struct _vcs_dpi_voltage_scaling_st entry = {0}; 1811 1812 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 1813 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 1814 1815 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 1816 1817 static const unsigned int num_dcfclk_stas = 5; 1818 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 1819 1820 unsigned int num_uclk_dpms = 0; 1821 unsigned int num_fclk_dpms = 0; 1822 unsigned int num_dcfclk_dpms = 0; 1823 1824 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1825 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1826 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1827 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 1828 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 1829 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 1830 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 1831 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1832 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1833 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1834 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1835 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1836 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1837 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 1838 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 1839 1840 if (bw_params->clk_table.entries[i].memclk_mhz > 0) 1841 num_uclk_dpms++; 1842 if (bw_params->clk_table.entries[i].fclk_mhz > 0) 1843 num_fclk_dpms++; 1844 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 1845 num_dcfclk_dpms++; 1846 } 1847 1848 if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 1849 return -1; 1850 1851 if (max_dppclk_mhz == 0) 1852 max_dppclk_mhz = max_dispclk_mhz; 1853 1854 if (max_fclk_mhz == 0) 1855 max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; 1856 1857 if (max_phyclk_mhz == 0) 1858 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 1859 1860 *num_entries = 0; 1861 entry.dispclk_mhz = max_dispclk_mhz; 1862 entry.dscclk_mhz = max_dispclk_mhz / 3; 1863 entry.dppclk_mhz = max_dppclk_mhz; 1864 entry.dtbclk_mhz = max_dtbclk_mhz; 1865 entry.phyclk_mhz = max_phyclk_mhz; 1866 entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 1867 entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 1868 1869 // Insert all the DCFCLK STAs 1870 for (i = 0; i < num_dcfclk_stas; i++) { 1871 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 1872 entry.fabricclk_mhz = 0; 1873 entry.dram_speed_mts = 0; 1874 1875 get_optimal_ntuple(&entry); 1876 insert_entry_into_table_sorted(table, num_entries, &entry); 1877 } 1878 1879 // Insert the max DCFCLK 1880 entry.dcfclk_mhz = max_dcfclk_mhz; 1881 entry.fabricclk_mhz = 0; 1882 entry.dram_speed_mts = 0; 1883 1884 get_optimal_ntuple(&entry); 1885 insert_entry_into_table_sorted(table, num_entries, &entry); 1886 1887 // Insert the UCLK DPMS 1888 for (i = 0; i < num_uclk_dpms; i++) { 1889 entry.dcfclk_mhz = 0; 1890 entry.fabricclk_mhz = 0; 1891 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 1892 1893 get_optimal_ntuple(&entry); 1894 insert_entry_into_table_sorted(table, num_entries, &entry); 1895 } 1896 1897 // If FCLK is coarse grained, insert individual DPMs. 1898 if (num_fclk_dpms > 2) { 1899 for (i = 0; i < num_fclk_dpms; i++) { 1900 entry.dcfclk_mhz = 0; 1901 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 1902 entry.dram_speed_mts = 0; 1903 1904 get_optimal_ntuple(&entry); 1905 insert_entry_into_table_sorted(table, num_entries, &entry); 1906 } 1907 } 1908 // If FCLK fine grained, only insert max 1909 else { 1910 entry.dcfclk_mhz = 0; 1911 entry.fabricclk_mhz = max_fclk_mhz; 1912 entry.dram_speed_mts = 0; 1913 1914 get_optimal_ntuple(&entry); 1915 insert_entry_into_table_sorted(table, num_entries, &entry); 1916 } 1917 1918 // At this point, the table contains all "points of interest" based on 1919 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 1920 // ratios (by derate, are exact). 1921 1922 // Remove states that require higher clocks than are supported 1923 for (i = *num_entries - 1; i >= 0 ; i--) { 1924 if (table[i].dcfclk_mhz > max_dcfclk_mhz || 1925 table[i].fabricclk_mhz > max_fclk_mhz || 1926 table[i].dram_speed_mts > max_uclk_mhz * 16) 1927 remove_entry_from_table_at_index(table, num_entries, i); 1928 } 1929 1930 // At this point, the table only contains supported points of interest 1931 // it could be used as is, but some states may be redundant due to 1932 // coarse grained nature of some clocks, so we want to round up to 1933 // coarse grained DPMs and remove duplicates. 1934 1935 // Round up UCLKs 1936 for (i = *num_entries - 1; i >= 0 ; i--) { 1937 for (j = 0; j < num_uclk_dpms; j++) { 1938 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 1939 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 1940 break; 1941 } 1942 } 1943 } 1944 1945 // If FCLK is coarse grained, round up to next DPMs 1946 if (num_fclk_dpms > 2) { 1947 for (i = *num_entries - 1; i >= 0 ; i--) { 1948 for (j = 0; j < num_fclk_dpms; j++) { 1949 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 1950 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 1951 break; 1952 } 1953 } 1954 } 1955 } 1956 // Otherwise, round up to minimum. 1957 else { 1958 for (i = *num_entries - 1; i >= 0 ; i--) { 1959 if (table[i].fabricclk_mhz < min_fclk_mhz) { 1960 table[i].fabricclk_mhz = min_fclk_mhz; 1961 break; 1962 } 1963 } 1964 } 1965 1966 // Round DCFCLKs up to minimum 1967 for (i = *num_entries - 1; i >= 0 ; i--) { 1968 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 1969 table[i].dcfclk_mhz = min_dcfclk_mhz; 1970 break; 1971 } 1972 } 1973 1974 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 1975 i = 0; 1976 while (i < *num_entries - 1) { 1977 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 1978 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 1979 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 1980 remove_entry_from_table_at_index(table, num_entries, i + 1); 1981 else 1982 i++; 1983 } 1984 1985 // Fix up the state indicies 1986 for (i = *num_entries - 1; i >= 0 ; i--) { 1987 table[i].state = i; 1988 } 1989 1990 return 0; 1991 } 1992 1993 /* dcn321_update_bw_bounding_box 1994 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet 1995 * with actual values as per dGPU SKU: 1996 * -with passed few options from dc->config 1997 * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) 1998 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes 1999 * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU 2000 * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) 2001 * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different 2002 * clocks (which might differ for certain dGPU SKU of the same ASIC) 2003 */ 2004 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2005 { 2006 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2007 /* Overrides from dc->config options */ 2008 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 2009 2010 /* Override from passed dc->bb_overrides if available*/ 2011 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 2012 && dc->bb_overrides.sr_exit_time_ns) { 2013 dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 2014 } 2015 2016 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) 2017 != dc->bb_overrides.sr_enter_plus_exit_time_ns 2018 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 2019 dcn3_21_soc.sr_enter_plus_exit_time_us = 2020 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 2021 } 2022 2023 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 2024 && dc->bb_overrides.urgent_latency_ns) { 2025 dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2026 } 2027 2028 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) 2029 != dc->bb_overrides.dram_clock_change_latency_ns 2030 && dc->bb_overrides.dram_clock_change_latency_ns) { 2031 dcn3_21_soc.dram_clock_change_latency_us = 2032 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 2033 } 2034 2035 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) 2036 != dc->bb_overrides.dummy_clock_change_latency_ns 2037 && dc->bb_overrides.dummy_clock_change_latency_ns) { 2038 dcn3_21_soc.dummy_pstate_latency_us = 2039 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 2040 } 2041 2042 /* Override from VBIOS if VBIOS bb_info available */ 2043 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 2044 struct bp_soc_bb_info bb_info = {0}; 2045 2046 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 2047 if (bb_info.dram_clock_change_latency_100ns > 0) 2048 dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 2049 2050 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 2051 dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 2052 2053 if (bb_info.dram_sr_exit_latency_100ns > 0) 2054 dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 2055 } 2056 } 2057 2058 /* Override from VBIOS for num_chan */ 2059 if (dc->ctx->dc_bios->vram_info.num_chans) 2060 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2061 2062 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2063 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2064 2065 } 2066 2067 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 2068 dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2069 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2070 2071 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 2072 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 2073 if (dc->debug.use_legacy_soc_bb_mechanism) { 2074 unsigned int i = 0, j = 0, num_states = 0; 2075 2076 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2077 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2078 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2079 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2080 2081 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; 2082 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 2083 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 2084 2085 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2086 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2087 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2088 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2089 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2090 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2091 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2092 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2093 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2094 } 2095 if (!max_dcfclk_mhz) 2096 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; 2097 if (!max_dispclk_mhz) 2098 max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; 2099 if (!max_dppclk_mhz) 2100 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; 2101 if (!max_phyclk_mhz) 2102 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 2103 2104 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2105 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2106 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2107 num_dcfclk_sta_targets++; 2108 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2109 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2110 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2111 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2112 dcfclk_sta_targets[i] = max_dcfclk_mhz; 2113 break; 2114 } 2115 } 2116 // Update size of array since we "removed" duplicates 2117 num_dcfclk_sta_targets = i + 1; 2118 } 2119 2120 num_uclk_states = bw_params->clk_table.num_entries; 2121 2122 // Calculate optimal dcfclk for each uclk 2123 for (i = 0; i < num_uclk_states; i++) { 2124 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2125 &optimal_dcfclk_for_uclk[i], NULL); 2126 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2127 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2128 } 2129 } 2130 2131 // Calculate optimal uclk for each dcfclk sta target 2132 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2133 for (j = 0; j < num_uclk_states; j++) { 2134 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2135 optimal_uclk_for_dcfclk_sta_targets[i] = 2136 bw_params->clk_table.entries[j].memclk_mhz * 16; 2137 break; 2138 } 2139 } 2140 } 2141 2142 i = 0; 2143 j = 0; 2144 // create the final dcfclk and uclk table 2145 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2146 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2147 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2148 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2149 } else { 2150 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2151 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2152 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2153 } else { 2154 j = num_uclk_states; 2155 } 2156 } 2157 } 2158 2159 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2160 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2161 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2162 } 2163 2164 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2165 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2166 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2167 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2168 } 2169 2170 dcn3_21_soc.num_states = num_states; 2171 for (i = 0; i < dcn3_21_soc.num_states; i++) { 2172 dcn3_21_soc.clock_limits[i].state = i; 2173 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2174 dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2175 2176 /* Fill all states with max values of all these clocks */ 2177 dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2178 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2179 dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2180 dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 2181 2182 /* Populate from bw_params for DTBCLK, SOCCLK */ 2183 if (i > 0) { 2184 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 2185 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; 2186 } else { 2187 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2188 } 2189 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 2190 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2191 } 2192 2193 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 2194 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; 2195 else 2196 dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 2197 2198 if (!dram_speed_mts[i] && i > 0) 2199 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; 2200 else 2201 dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2202 2203 /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ 2204 /* PHYCLK_D18, PHYCLK_D32 */ 2205 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 2206 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 2207 } 2208 } else { 2209 build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states); 2210 } 2211 2212 /* Re-init DML with updated bb */ 2213 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 2214 if (dc->current_state) 2215 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 2216 } 2217 } 2218 2219 static struct resource_funcs dcn321_res_pool_funcs = { 2220 .destroy = dcn321_destroy_resource_pool, 2221 .link_enc_create = dcn321_link_encoder_create, 2222 .link_enc_create_minimal = NULL, 2223 .panel_cntl_create = dcn32_panel_cntl_create, 2224 .validate_bandwidth = dcn32_validate_bandwidth, 2225 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2226 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2227 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2228 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2229 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2230 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2231 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2232 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2233 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2234 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2235 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2236 .update_bw_bounding_box = dcn321_update_bw_bounding_box, 2237 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2238 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2239 .add_phantom_pipes = dcn32_add_phantom_pipes, 2240 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2241 }; 2242 2243 2244 static bool dcn321_resource_construct( 2245 uint8_t num_virtual_links, 2246 struct dc *dc, 2247 struct dcn321_resource_pool *pool) 2248 { 2249 int i, j; 2250 struct dc_context *ctx = dc->ctx; 2251 struct irq_service_init_data init_data; 2252 struct ddc_service_init_data ddc_init_data = {0}; 2253 uint32_t pipe_fuses = 0; 2254 uint32_t num_pipes = 4; 2255 2256 ctx->dc_bios->regs = &bios_regs; 2257 2258 pool->base.res_cap = &res_cap_dcn321; 2259 /* max number of pipes for ASIC before checking for pipe fuses */ 2260 num_pipes = pool->base.res_cap->num_timing_generator; 2261 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2262 2263 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2264 if (pipe_fuses & 1 << i) 2265 num_pipes--; 2266 2267 if (pipe_fuses & 1) 2268 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2269 2270 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2271 ASSERT(0); //Entire DCN is harvested! 2272 2273 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2274 * value will be changed, update max_num_dpp and max_num_otg for dml. 2275 */ 2276 dcn3_21_ip.max_num_dpp = num_pipes; 2277 dcn3_21_ip.max_num_otg = num_pipes; 2278 2279 pool->base.funcs = &dcn321_res_pool_funcs; 2280 2281 /************************************************* 2282 * Resource + asic cap harcoding * 2283 *************************************************/ 2284 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2285 pool->base.timing_generator_count = num_pipes; 2286 pool->base.pipe_count = num_pipes; 2287 pool->base.mpcc_count = num_pipes; 2288 dc->caps.max_downscale_ratio = 600; 2289 dc->caps.i2c_speed_in_khz = 100; 2290 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2291 dc->caps.max_cursor_size = 256; 2292 dc->caps.min_horizontal_blanking_period = 80; 2293 dc->caps.dmdata_alloc_size = 2048; 2294 dc->caps.mall_size_per_mem_channel = 0; 2295 dc->caps.mall_size_total = 0; 2296 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2297 dc->caps.cache_line_size = 64; 2298 dc->caps.cache_num_ways = 16; 2299 dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 2300 dc->caps.subvp_fw_processing_delay_us = 15; 2301 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2302 dc->caps.subvp_pstate_allow_width_us = 20; 2303 2304 dc->caps.max_slave_planes = 1; 2305 dc->caps.max_slave_yuv_planes = 1; 2306 dc->caps.max_slave_rgb_planes = 1; 2307 dc->caps.post_blend_color_processing = true; 2308 dc->caps.force_dp_tps4_for_cp2520 = true; 2309 dc->caps.dp_hpo = true; 2310 dc->caps.dp_hdmi21_pcon_support = true; 2311 dc->caps.edp_dsc_support = true; 2312 dc->caps.extended_aux_timeout_support = true; 2313 dc->caps.dmcub_support = true; 2314 2315 /* Color pipeline capabilities */ 2316 dc->caps.color.dpp.dcn_arch = 1; 2317 dc->caps.color.dpp.input_lut_shared = 0; 2318 dc->caps.color.dpp.icsc = 1; 2319 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2320 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2321 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2322 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2323 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2324 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2325 dc->caps.color.dpp.post_csc = 1; 2326 dc->caps.color.dpp.gamma_corr = 1; 2327 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2328 2329 dc->caps.color.dpp.hw_3d_lut = 1; 2330 dc->caps.color.dpp.ogam_ram = 1; 2331 // no OGAM ROM on DCN2 and later ASICs 2332 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2333 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2334 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2335 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2336 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2337 dc->caps.color.dpp.ocsc = 0; 2338 2339 dc->caps.color.mpc.gamut_remap = 1; 2340 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2341 dc->caps.color.mpc.ogam_ram = 1; 2342 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2343 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2344 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2345 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2346 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2347 dc->caps.color.mpc.ocsc = 1; 2348 2349 /* read VBIOS LTTPR caps */ 2350 { 2351 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2352 enum bp_result bp_query_result; 2353 uint8_t is_vbios_lttpr_enable = 0; 2354 2355 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2356 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2357 } 2358 2359 /* interop bit is implicit */ 2360 { 2361 dc->caps.vbios_lttpr_aware = true; 2362 } 2363 } 2364 2365 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2366 dc->debug = debug_defaults_drv; 2367 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2368 dc->debug = debug_defaults_diags; 2369 } else 2370 dc->debug = debug_defaults_diags; 2371 // Init the vm_helper 2372 if (dc->vm_helper) 2373 vm_helper_init(dc->vm_helper, 16); 2374 2375 /************************************************* 2376 * Create resources * 2377 *************************************************/ 2378 2379 /* Clock Sources for Pixel Clock*/ 2380 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = 2381 dcn321_clock_source_create(ctx, ctx->dc_bios, 2382 CLOCK_SOURCE_COMBO_PHY_PLL0, 2383 &clk_src_regs[0], false); 2384 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = 2385 dcn321_clock_source_create(ctx, ctx->dc_bios, 2386 CLOCK_SOURCE_COMBO_PHY_PLL1, 2387 &clk_src_regs[1], false); 2388 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = 2389 dcn321_clock_source_create(ctx, ctx->dc_bios, 2390 CLOCK_SOURCE_COMBO_PHY_PLL2, 2391 &clk_src_regs[2], false); 2392 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = 2393 dcn321_clock_source_create(ctx, ctx->dc_bios, 2394 CLOCK_SOURCE_COMBO_PHY_PLL3, 2395 &clk_src_regs[3], false); 2396 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = 2397 dcn321_clock_source_create(ctx, ctx->dc_bios, 2398 CLOCK_SOURCE_COMBO_PHY_PLL4, 2399 &clk_src_regs[4], false); 2400 2401 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; 2402 2403 /* todo: not reuse phy_pll registers */ 2404 pool->base.dp_clock_source = 2405 dcn321_clock_source_create(ctx, ctx->dc_bios, 2406 CLOCK_SOURCE_ID_DP_DTO, 2407 &clk_src_regs[0], true); 2408 2409 for (i = 0; i < pool->base.clk_src_count; i++) { 2410 if (pool->base.clock_sources[i] == NULL) { 2411 dm_error("DC: failed to create clock sources!\n"); 2412 BREAK_TO_DEBUGGER(); 2413 goto create_fail; 2414 } 2415 } 2416 2417 /* DCCG */ 2418 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2419 if (pool->base.dccg == NULL) { 2420 dm_error("DC: failed to create dccg!\n"); 2421 BREAK_TO_DEBUGGER(); 2422 goto create_fail; 2423 } 2424 2425 /* DML */ 2426 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2427 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 2428 2429 /* IRQ Service */ 2430 init_data.ctx = dc->ctx; 2431 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2432 if (!pool->base.irqs) 2433 goto create_fail; 2434 2435 /* HUBBUB */ 2436 pool->base.hubbub = dcn321_hubbub_create(ctx); 2437 if (pool->base.hubbub == NULL) { 2438 BREAK_TO_DEBUGGER(); 2439 dm_error("DC: failed to create hubbub!\n"); 2440 goto create_fail; 2441 } 2442 2443 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2444 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2445 2446 /* if pipe is disabled, skip instance of HW pipe, 2447 * i.e, skip ASIC register instance 2448 */ 2449 if (pipe_fuses & 1 << i) 2450 continue; 2451 2452 pool->base.hubps[j] = dcn321_hubp_create(ctx, i); 2453 if (pool->base.hubps[j] == NULL) { 2454 BREAK_TO_DEBUGGER(); 2455 dm_error( 2456 "DC: failed to create hubps!\n"); 2457 goto create_fail; 2458 } 2459 2460 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); 2461 if (pool->base.dpps[j] == NULL) { 2462 BREAK_TO_DEBUGGER(); 2463 dm_error( 2464 "DC: failed to create dpps!\n"); 2465 goto create_fail; 2466 } 2467 2468 pool->base.opps[j] = dcn321_opp_create(ctx, i); 2469 if (pool->base.opps[j] == NULL) { 2470 BREAK_TO_DEBUGGER(); 2471 dm_error( 2472 "DC: failed to create output pixel processor!\n"); 2473 goto create_fail; 2474 } 2475 2476 pool->base.timing_generators[j] = dcn321_timing_generator_create( 2477 ctx, i); 2478 if (pool->base.timing_generators[j] == NULL) { 2479 BREAK_TO_DEBUGGER(); 2480 dm_error("DC: failed to create tg!\n"); 2481 goto create_fail; 2482 } 2483 2484 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2485 &abm_regs[i], 2486 &abm_shift, 2487 &abm_mask); 2488 if (pool->base.multiple_abms[j] == NULL) { 2489 dm_error("DC: failed to create abm for pipe %d!\n", i); 2490 BREAK_TO_DEBUGGER(); 2491 goto create_fail; 2492 } 2493 2494 /* index for resource pool arrays for next valid pipe */ 2495 j++; 2496 } 2497 2498 /* PSR */ 2499 pool->base.psr = dmub_psr_create(ctx); 2500 if (pool->base.psr == NULL) { 2501 dm_error("DC: failed to create psr obj!\n"); 2502 BREAK_TO_DEBUGGER(); 2503 goto create_fail; 2504 } 2505 2506 /* MPCCs */ 2507 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2508 if (pool->base.mpc == NULL) { 2509 BREAK_TO_DEBUGGER(); 2510 dm_error("DC: failed to create mpc!\n"); 2511 goto create_fail; 2512 } 2513 2514 /* DSCs */ 2515 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2516 pool->base.dscs[i] = dcn321_dsc_create(ctx, i); 2517 if (pool->base.dscs[i] == NULL) { 2518 BREAK_TO_DEBUGGER(); 2519 dm_error("DC: failed to create display stream compressor %d!\n", i); 2520 goto create_fail; 2521 } 2522 } 2523 2524 /* DWB */ 2525 if (!dcn321_dwbc_create(ctx, &pool->base)) { 2526 BREAK_TO_DEBUGGER(); 2527 dm_error("DC: failed to create dwbc!\n"); 2528 goto create_fail; 2529 } 2530 2531 /* MMHUBBUB */ 2532 if (!dcn321_mmhubbub_create(ctx, &pool->base)) { 2533 BREAK_TO_DEBUGGER(); 2534 dm_error("DC: failed to create mcif_wb!\n"); 2535 goto create_fail; 2536 } 2537 2538 /* AUX and I2C */ 2539 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2540 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); 2541 if (pool->base.engines[i] == NULL) { 2542 BREAK_TO_DEBUGGER(); 2543 dm_error( 2544 "DC:failed to create aux engine!!\n"); 2545 goto create_fail; 2546 } 2547 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); 2548 if (pool->base.hw_i2cs[i] == NULL) { 2549 BREAK_TO_DEBUGGER(); 2550 dm_error( 2551 "DC:failed to create hw i2c!!\n"); 2552 goto create_fail; 2553 } 2554 pool->base.sw_i2cs[i] = NULL; 2555 } 2556 2557 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2558 if (!resource_construct(num_virtual_links, dc, &pool->base, 2559 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2560 &res_create_funcs : &res_create_maximus_funcs))) 2561 goto create_fail; 2562 2563 /* HW Sequencer init functions and Plane caps */ 2564 dcn32_hw_sequencer_init_functions(dc); 2565 2566 dc->caps.max_planes = pool->base.pipe_count; 2567 2568 for (i = 0; i < dc->caps.max_planes; ++i) 2569 dc->caps.planes[i] = plane_cap; 2570 2571 dc->cap_funcs = cap_funcs; 2572 2573 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2574 ddc_init_data.ctx = dc->ctx; 2575 ddc_init_data.link = NULL; 2576 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2577 ddc_init_data.id.enum_id = 0; 2578 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2579 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2580 } else { 2581 pool->base.oem_device = NULL; 2582 } 2583 2584 return true; 2585 2586 create_fail: 2587 2588 dcn321_resource_destruct(pool); 2589 2590 return false; 2591 } 2592 2593 struct resource_pool *dcn321_create_resource_pool( 2594 const struct dc_init_data *init_data, 2595 struct dc *dc) 2596 { 2597 struct dcn321_resource_pool *pool = 2598 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); 2599 2600 if (!pool) 2601 return NULL; 2602 2603 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) 2604 return &pool->base; 2605 2606 BREAK_TO_DEBUGGER(); 2607 kfree(pool); 2608 return NULL; 2609 } 2610