1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 // header file of functions being implemented 27 #include "dcn32_resource.h" 28 #include "dcn20/dcn20_resource.h" 29 #include "dml/dcn32/display_mode_vba_util_32.h" 30 31 static bool is_dual_plane(enum surface_pixel_format format) 32 { 33 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 34 } 35 36 /** 37 * ******************************************************************************************** 38 * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed for SubVP 39 * 40 * This function first checks the bytes required per pixel on the SubVP pipe, then calculates 41 * the total number of pixels required in the SubVP MALL region. These are used to calculate 42 * the number of cache lines used (then number of ways required) for SubVP MCLK switching. 43 * 44 * @param [in] dc: current dc state 45 * @param [in] context: new dc state 46 * 47 * @return: number of ways required for SubVP 48 * 49 * ******************************************************************************************** 50 */ 51 uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_state *context) 52 { 53 uint32_t num_ways = 0; 54 uint32_t bytes_per_pixel = 0; 55 uint32_t cache_lines_used = 0; 56 uint32_t lines_per_way = 0; 57 uint32_t total_cache_lines = 0; 58 uint32_t bytes_in_mall = 0; 59 uint32_t num_mblks = 0; 60 uint32_t cache_lines_per_plane = 0; 61 uint32_t i = 0, j = 0; 62 uint16_t mblk_width = 0; 63 uint16_t mblk_height = 0; 64 uint32_t full_vp_width_blk_aligned = 0; 65 uint32_t full_vp_height_blk_aligned = 0; 66 uint32_t mall_alloc_width_blk_aligned = 0; 67 uint32_t mall_alloc_height_blk_aligned = 0; 68 uint16_t full_vp_height = 0; 69 bool subvp_in_use = false; 70 71 for (i = 0; i < dc->res_pool->pipe_count; i++) { 72 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 73 74 /* Find the phantom pipes. 75 * - For pipe split case we need to loop through the bottom and next ODM 76 * pipes or only half the viewport size is counted 77 */ 78 if (pipe->stream && pipe->plane_state && 79 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 80 struct pipe_ctx *main_pipe = NULL; 81 82 subvp_in_use = true; 83 /* Get full viewport height from main pipe (required for MBLK calculation) */ 84 for (j = 0; j < dc->res_pool->pipe_count; j++) { 85 main_pipe = &context->res_ctx.pipe_ctx[j]; 86 if (main_pipe->stream == pipe->stream->mall_stream_config.paired_stream) { 87 full_vp_height = main_pipe->plane_res.scl_data.viewport.height; 88 break; 89 } 90 } 91 92 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 93 mblk_width = DCN3_2_MBLK_WIDTH; 94 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 95 96 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 97 * FLOOR(vp_x_start, blk_width) 98 */ 99 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 100 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - 101 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 102 103 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 104 * FLOOR(vp_y_start, blk_height) 105 */ 106 full_vp_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 107 full_vp_height + mblk_height - 1) / mblk_height * mblk_height) - 108 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 109 110 /* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ 111 mall_alloc_width_blk_aligned = full_vp_width_blk_aligned; 112 113 /* mall_alloc_height_blk_aligned_l/c = CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */ 114 mall_alloc_height_blk_aligned = (pipe->plane_res.scl_data.viewport.height - 1 + mblk_height - 1) / 115 mblk_height * mblk_height + mblk_height; 116 117 /* full_mblk_width_ub_l/c = mall_alloc_width_blk_aligned_l/c; 118 * full_mblk_height_ub_l/c = mall_alloc_height_blk_aligned_l/c; 119 * num_mblk_l/c = (full_mblk_width_ub_l/c / mblk_width_l/c) * (full_mblk_height_ub_l/c / mblk_height_l/c); 120 * (Should be divisible, but round up if not) 121 */ 122 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 123 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 124 125 /*For DCC: 126 * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1) 127 */ 128 if (pipe->plane_state->dcc.enable) 129 num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel + 130 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 131 132 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 133 // cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 134 // (MALL is 64-byte aligned) 135 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 136 137 cache_lines_used += cache_lines_per_plane; 138 } 139 } 140 141 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 142 lines_per_way = total_cache_lines / dc->caps.cache_num_ways; 143 num_ways = cache_lines_used / lines_per_way; 144 if (cache_lines_used % lines_per_way > 0) 145 num_ways++; 146 147 if (subvp_in_use && dc->debug.force_subvp_num_ways > 0) 148 num_ways = dc->debug.force_subvp_num_ways; 149 150 return num_ways; 151 } 152 153 void dcn32_merge_pipes_for_subvp(struct dc *dc, 154 struct dc_state *context) 155 { 156 uint32_t i; 157 158 /* merge pipes if necessary */ 159 for (i = 0; i < dc->res_pool->pipe_count; i++) { 160 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 161 162 // For now merge all pipes for SubVP since pipe split case isn't supported yet 163 164 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 165 if (pipe->prev_odm_pipe) { 166 /*split off odm pipe*/ 167 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 168 if (pipe->next_odm_pipe) 169 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 170 171 pipe->bottom_pipe = NULL; 172 pipe->next_odm_pipe = NULL; 173 pipe->plane_state = NULL; 174 pipe->stream = NULL; 175 pipe->top_pipe = NULL; 176 pipe->prev_odm_pipe = NULL; 177 if (pipe->stream_res.dsc) 178 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 179 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 180 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 181 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 182 struct pipe_ctx *top_pipe = pipe->top_pipe; 183 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 184 185 top_pipe->bottom_pipe = bottom_pipe; 186 if (bottom_pipe) 187 bottom_pipe->top_pipe = top_pipe; 188 189 pipe->top_pipe = NULL; 190 pipe->bottom_pipe = NULL; 191 pipe->plane_state = NULL; 192 pipe->stream = NULL; 193 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 194 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 195 } 196 } 197 } 198 199 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, 200 struct dc_state *context) 201 { 202 uint32_t i; 203 204 for (i = 0; i < dc->res_pool->pipe_count; i++) { 205 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 206 207 if (!pipe->stream) 208 continue; 209 210 if (!pipe->plane_state) 211 return false; 212 } 213 return true; 214 } 215 216 bool dcn32_subvp_in_use(struct dc *dc, 217 struct dc_state *context) 218 { 219 uint32_t i; 220 221 for (i = 0; i < dc->res_pool->pipe_count; i++) { 222 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 223 224 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) 225 return true; 226 } 227 return false; 228 } 229 230 bool dcn32_mpo_in_use(struct dc_state *context) 231 { 232 uint32_t i; 233 234 for (i = 0; i < context->stream_count; i++) { 235 if (context->stream_status[i].plane_count > 1) 236 return true; 237 } 238 return false; 239 } 240 241 242 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context) 243 { 244 uint32_t i; 245 246 for (i = 0; i < dc->res_pool->pipe_count; i++) { 247 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 248 249 if (!pipe->stream) 250 continue; 251 252 if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0) 253 return true; 254 } 255 return false; 256 } 257 258 /** 259 * ******************************************************************************************* 260 * dcn32_determine_det_override: Determine DET allocation for each pipe 261 * 262 * This function determines how much DET to allocate for each pipe. The total number of 263 * DET segments will be split equally among each of the streams, and after that the DET 264 * segments per stream will be split equally among the planes for the given stream. 265 * 266 * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the 267 * number of DET for that given plane will be split among the pipes driving that plane. 268 * 269 * 270 * High level algorithm: 271 * 1. Split total DET among number of streams 272 * 2. For each stream, split DET among the planes 273 * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation 274 * among those pipes. 275 * 4. Assign the DET override to the DML pipes. 276 * 277 * @param [in]: dc: Current DC state 278 * @param [in]: context: New DC state to be programmed 279 * @param [in]: pipes: Array of DML pipes 280 * 281 * @return: void 282 * 283 * ******************************************************************************************* 284 */ 285 void dcn32_determine_det_override(struct dc *dc, 286 struct dc_state *context, 287 display_e2e_pipe_params_st *pipes) 288 { 289 uint32_t i, j, k; 290 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0}; 291 uint8_t pipe_counted[MAX_PIPES] = {0}; 292 uint8_t pipe_cnt = 0; 293 struct dc_plane_state *current_plane = NULL; 294 uint8_t stream_count = 0; 295 296 for (i = 0; i < context->stream_count; i++) { 297 /* Don't count SubVP streams for DET allocation */ 298 if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { 299 stream_count++; 300 } 301 } 302 303 if (stream_count > 0) { 304 stream_segments = 18 / stream_count; 305 for (i = 0; i < context->stream_count; i++) { 306 if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM) 307 continue; 308 if (context->stream_status[i].plane_count > 0) 309 plane_segments = stream_segments / context->stream_status[i].plane_count; 310 else 311 plane_segments = stream_segments; 312 for (j = 0; j < dc->res_pool->pipe_count; j++) { 313 pipe_plane_count = 0; 314 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] && 315 pipe_counted[j] != 1) { 316 /* Note: pipe_plane_count indicates the number of pipes to be used for a 317 * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split), 318 * pipe_plane_count = 2 means 2:1 split, etc. 319 */ 320 pipe_plane_count++; 321 pipe_counted[j] = 1; 322 current_plane = context->res_ctx.pipe_ctx[j].plane_state; 323 for (k = 0; k < dc->res_pool->pipe_count; k++) { 324 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && 325 context->res_ctx.pipe_ctx[k].plane_state == current_plane) { 326 pipe_plane_count++; 327 pipe_counted[k] = 1; 328 } 329 } 330 331 pipe_segments[j] = plane_segments / pipe_plane_count; 332 for (k = 0; k < dc->res_pool->pipe_count; k++) { 333 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && 334 context->res_ctx.pipe_ctx[k].plane_state == current_plane) { 335 pipe_segments[k] = plane_segments / pipe_plane_count; 336 } 337 } 338 } 339 } 340 } 341 342 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 343 if (!context->res_ctx.pipe_ctx[i].stream) 344 continue; 345 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; 346 pipe_cnt++; 347 } 348 } else { 349 for (i = 0; i < dc->res_pool->pipe_count; i++) 350 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE 351 } 352 } 353 354 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, 355 display_e2e_pipe_params_st *pipes) 356 { 357 int i, pipe_cnt; 358 struct resource_context *res_ctx = &context->res_ctx; 359 struct pipe_ctx *pipe; 360 361 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 362 363 if (!res_ctx->pipe_ctx[i].stream) 364 continue; 365 366 pipe = &res_ctx->pipe_ctx[i]; 367 pipe_cnt++; 368 } 369 370 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 371 * the DET available for each pipe). Use the DET override input to maintain our driver 372 * policy. 373 */ 374 if (pipe_cnt == 1) { 375 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; 376 if (pipe->plane_state && !dc->debug.disable_z9_mpc && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { 377 if (!is_dual_plane(pipe->plane_state->format)) { 378 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; 379 pipes[0].pipe.src.unbounded_req_mode = true; 380 if (pipe->plane_state->src_rect.width >= 5120 && 381 pipe->plane_state->src_rect.height >= 2880) 382 pipes[0].pipe.src.det_size_override = 320; // 5K or higher 383 } 384 } 385 } else 386 dcn32_determine_det_override(dc, context, pipes); 387 } 388 389 /** 390 * ******************************************************************************************* 391 * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases 392 * 393 * This function saves the MALL (SubVP) case for fast validation cases. For fast validation, 394 * there are situations where a shallow copy of the dc->current_state is created for the 395 * validation. In this case we want to save and restore the mall config because we always 396 * teardown subvp at the beginning of validation (and don't attempt to add it back if it's 397 * fast validation). If we don't restore the subvp config in cases of fast validation + 398 * shallow copy of the dc->current_state, the dc->current_state will have a partially 399 * removed subvp state when we did not intend to remove it. 400 * 401 * NOTE: This function ONLY works if the streams are not moved to a different pipe in the 402 * validation. We don't expect this to happen in fast_validation=1 cases. 403 * 404 * @param [in]: dc: Current DC state 405 * @param [in]: context: New DC state to be programmed 406 * @param [out]: temp_config: struct used to cache the existing MALL state 407 * 408 * @return: void 409 * 410 * ******************************************************************************************* 411 */ 412 void dcn32_save_mall_state(struct dc *dc, 413 struct dc_state *context, 414 struct mall_temp_config *temp_config) 415 { 416 uint32_t i; 417 418 for (i = 0; i < dc->res_pool->pipe_count; i++) { 419 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 420 421 if (pipe->stream) 422 temp_config->mall_stream_config[i] = pipe->stream->mall_stream_config; 423 424 if (pipe->plane_state) 425 temp_config->is_phantom_plane[i] = pipe->plane_state->is_phantom; 426 } 427 } 428 429 /** 430 * ******************************************************************************************* 431 * dcn32_restore_mall_state: Restore MALL (SubVP) state for fast validation cases 432 * 433 * Restore the MALL state based on the previously saved state from dcn32_save_mall_state 434 * 435 * @param [in]: dc: Current DC state 436 * @param [in/out]: context: New DC state to be programmed, restore MALL state into here 437 * @param [in]: temp_config: struct that has the cached MALL state 438 * 439 * @return: void 440 * 441 * ******************************************************************************************* 442 */ 443 void dcn32_restore_mall_state(struct dc *dc, 444 struct dc_state *context, 445 struct mall_temp_config *temp_config) 446 { 447 uint32_t i; 448 449 for (i = 0; i < dc->res_pool->pipe_count; i++) { 450 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 451 452 if (pipe->stream) 453 pipe->stream->mall_stream_config = temp_config->mall_stream_config[i]; 454 455 if (pipe->plane_state) 456 pipe->plane_state->is_phantom = temp_config->is_phantom_plane[i]; 457 } 458 } 459