1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef _DCN32_RESOURCE_H_
27 #define _DCN32_RESOURCE_H_
28 
29 #include "core_types.h"
30 
31 #define DCN3_2_DEFAULT_DET_SIZE 256
32 #define DCN3_2_MAX_DET_SIZE 1152
33 #define DCN3_2_MIN_DET_SIZE 128
34 #define DCN3_2_MIN_COMPBUF_SIZE_KB 128
35 #define DCN3_2_DET_SEG_SIZE 64
36 #define DCN3_2_MALL_MBLK_SIZE_BYTES 65536 // 64 * 1024
37 #define DCN3_2_MBLK_WIDTH 128
38 #define DCN3_2_MBLK_HEIGHT_4BPE 128
39 #define DCN3_2_MBLK_HEIGHT_8BPE 64
40 #define DCN3_2_VMIN_DISPCLK_HZ 717000000
41 
42 #define TO_DCN32_RES_POOL(pool)\
43 	container_of(pool, struct dcn32_resource_pool, base)
44 
45 extern struct _vcs_dpi_ip_params_st dcn3_2_ip;
46 extern struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc;
47 
48 /* Temp struct used to save and restore MALL config
49  * during validation.
50  *
51  * TODO: Move MALL config into dc_state instead of stream struct
52  * to avoid needing to save/restore.
53  */
54 struct mall_temp_config {
55 	struct mall_stream_config mall_stream_config[MAX_PIPES];
56 	bool is_phantom_plane[MAX_PIPES];
57 };
58 
59 struct dcn32_resource_pool {
60 	struct resource_pool base;
61 };
62 
63 struct resource_pool *dcn32_create_resource_pool(
64 		const struct dc_init_data *init_data,
65 		struct dc *dc);
66 
67 struct panel_cntl *dcn32_panel_cntl_create(
68 		const struct panel_cntl_init_data *init_data);
69 
70 bool dcn32_acquire_post_bldn_3dlut(
71 		struct resource_context *res_ctx,
72 		const struct resource_pool *pool,
73 		int mpcc_id,
74 		struct dc_3dlut **lut,
75 		struct dc_transfer_func **shaper);
76 
77 bool dcn32_release_post_bldn_3dlut(
78 		struct resource_context *res_ctx,
79 		const struct resource_pool *pool,
80 		struct dc_3dlut **lut,
81 		struct dc_transfer_func **shaper);
82 
83 bool dcn32_remove_phantom_pipes(struct dc *dc,
84 		struct dc_state *context);
85 
86 void dcn32_add_phantom_pipes(struct dc *dc,
87 		struct dc_state *context,
88 		display_e2e_pipe_params_st *pipes,
89 		unsigned int pipe_cnt,
90 		unsigned int index);
91 
92 bool dcn32_validate_bandwidth(struct dc *dc,
93 		struct dc_state *context,
94 		bool fast_validate);
95 
96 int dcn32_populate_dml_pipes_from_context(
97 	struct dc *dc, struct dc_state *context,
98 	display_e2e_pipe_params_st *pipes,
99 	bool fast_validate);
100 
101 void dcn32_calculate_wm_and_dlg(
102 		struct dc *dc, struct dc_state *context,
103 		display_e2e_pipe_params_st *pipes,
104 		int pipe_cnt,
105 		int vlevel);
106 
107 uint32_t dcn32_helper_calculate_num_ways_for_subvp
108 		(struct dc *dc,
109 		struct dc_state *context);
110 
111 void dcn32_merge_pipes_for_subvp(struct dc *dc,
112 		struct dc_state *context);
113 
114 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
115 		struct dc_state *context);
116 
117 bool dcn32_subvp_in_use(struct dc *dc,
118 		struct dc_state *context);
119 
120 bool dcn32_mpo_in_use(struct dc_state *context);
121 
122 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
123 
124 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
125 		struct dc_state *state,
126 		const struct resource_pool *pool,
127 		struct dc_stream_state *stream,
128 		struct pipe_ctx *head_pipe);
129 
130 void dcn32_determine_det_override(struct dc *dc,
131 		struct dc_state *context,
132 		display_e2e_pipe_params_st *pipes);
133 
134 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
135 	display_e2e_pipe_params_st *pipes);
136 
137 void dcn32_save_mall_state(struct dc *dc,
138 		struct dc_state *context,
139 		struct mall_temp_config *temp_config);
140 
141 void dcn32_restore_mall_state(struct dc *dc,
142 		struct dc_state *context,
143 		struct mall_temp_config *temp_config);
144 
145 /* definitions for run time init of reg offsets */
146 
147 /* CLK SRC */
148 #define CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)                             \
149   (                                                                            \
150   SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid),                  \
151       SRII_ARR_2(PHASE, DP_DTO, 0, index),                                     \
152       SRII_ARR_2(PHASE, DP_DTO, 1, index),                                     \
153       SRII_ARR_2(PHASE, DP_DTO, 2, index),                                     \
154       SRII_ARR_2(PHASE, DP_DTO, 3, index),                                     \
155       SRII_ARR_2(MODULO, DP_DTO, 0, index),                                    \
156       SRII_ARR_2(MODULO, DP_DTO, 1, index),                                    \
157       SRII_ARR_2(MODULO, DP_DTO, 2, index),                                    \
158       SRII_ARR_2(MODULO, DP_DTO, 3, index),                                    \
159       SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index),                              \
160       SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index),                              \
161       SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index),                              \
162       SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)                               \
163   )
164 
165 /* ABM */
166 #define ABM_DCN32_REG_LIST_RI(id)                                              \
167   ( \
168   SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id),                                    \
169       SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id),                                \
170       SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id),                         \
171       SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id),                                  \
172       SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id),                               \
173       SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id),                             \
174       SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id),                              \
175       SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id),                                    \
176       SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id),                  \
177       SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id),                        \
178       SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id),                            \
179       SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id)  \
180   )
181 
182 /* Audio */
183 #define AUD_COMMON_REG_LIST_RI(id)                                             \
184   ( \
185   SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),                   \
186       SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),                \
187       SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, id),           \
188       SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, id),     \
189       SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, id),             \
190       SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id),   \
191       SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id),   \
192       SR_ARR(DCCG_AUDIO_DTO1_PHASE, id)                                        \
193   )
194 
195 /* VPG */
196 
197 #define VPG_DCN3_REG_LIST_RI(id)                                               \
198   ( \
199   SRI_ARR(VPG_GENERIC_STATUS, VPG, id),                                        \
200       SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id),                        \
201       SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id),                               \
202       SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id),                             \
203       SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id)                          \
204   )
205 
206 /* AFMT */
207 #define AFMT_DCN3_REG_LIST_RI(id)                                              \
208   ( \
209   SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id),                                  \
210       SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id),                              \
211       SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id),                            \
212       SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id),                           \
213       SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id),                               \
214       SRI_ARR(AFMT_60958_0, AFMT, id), SRI_ARR(AFMT_60958_1, AFMT, id),        \
215       SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id)         \
216   )
217 
218 /* APG */
219 #define APG_DCN31_REG_LIST_RI(id)                                              \
220   (\
221   SRI_ARR(APG_CONTROL, APG, id), SRI_ARR(APG_CONTROL2, APG, id),               \
222       SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id)     \
223   )
224 
225 /* Stream encoder */
226 #define SE_DCN32_REG_LIST_RI(id)                                               \
227   ( \
228   SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id),                  \
229       SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id),       \
230       SRI_ARR(HDMI_GC, DIG, id),                                               \
231       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id),                          \
232       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id),                          \
233       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id),                          \
234       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id),                          \
235       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id),                          \
236       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id),                          \
237       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id),                          \
238       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id),                          \
239       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id),                          \
240       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id),                          \
241       SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id),                         \
242       SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id),                               \
243       SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id),                               \
244       SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id),                               \
245       SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),                             \
246       SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),                               \
247       SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id),        \
248       SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id),        \
249       SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id),        \
250       SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id),               \
251       SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id),  \
252       SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id),                                   \
253       SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id),                                   \
254       SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id),                                   \
255       SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id),                                   \
256       SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id),  \
257       SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id),          \
258       SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id),            \
259       SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id),            \
260       SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id),               \
261       SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),          \
262       SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id),           \
263       SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id),         \
264       SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \
265       SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \
266       SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id),        \
267       SRI_ARR(DME_CONTROL, DME, id),                                           \
268       SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \
269       SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \
270       SRI_ARR(DIG_FE_CNTL, DIG, id), SRI_ARR(DIG_CLOCK_PATTERN, DIG, id),      \
271       SRI_ARR(DIG_FIFO_CTRL0, DIG, id)                                         \
272   )
273 
274 /* Aux regs */
275 
276 #define AUX_REG_LIST_RI(id)                                                    \
277   ( \
278   SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
279       SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id)                                \
280   )
281 
282 #define DCN2_AUX_REG_LIST_RI(id)                                               \
283   ( \
284   AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id)                \
285   )
286 
287 /* HDP */
288 #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id)
289 
290 /* Link encoder */
291 #define LE_DCN3_REG_LIST_RI(id)                                                \
292   ( \
293   SRI_ARR(DIG_BE_CNTL, DIG, id), SRI_ARR(DIG_BE_EN_CNTL, DIG, id),             \
294       SRI_ARR(TMDS_CTL_BITS, DIG, id),                                         \
295       SRI_ARR(TMDS_DCBALANCER_CONTROL, DIG, id), SRI_ARR(DP_CONFIG, DP, id),   \
296       SRI_ARR(DP_DPHY_CNTL, DP, id), SRI_ARR(DP_DPHY_PRBS_CNTL, DP, id),       \
297       SRI_ARR(DP_DPHY_SCRAM_CNTL, DP, id), SRI_ARR(DP_DPHY_SYM0, DP, id),      \
298       SRI_ARR(DP_DPHY_SYM1, DP, id), SRI_ARR(DP_DPHY_SYM2, DP, id),            \
299       SRI_ARR(DP_DPHY_TRAINING_PATTERN_SEL, DP, id),                           \
300       SRI_ARR(DP_LINK_CNTL, DP, id), SRI_ARR(DP_LINK_FRAMING_CNTL, DP, id),    \
301       SRI_ARR(DP_MSE_SAT0, DP, id), SRI_ARR(DP_MSE_SAT1, DP, id),              \
302       SRI_ARR(DP_MSE_SAT2, DP, id), SRI_ARR(DP_MSE_SAT_UPDATE, DP, id),        \
303       SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),       \
304       SRI_ARR(DP_DPHY_FAST_TRAINING, DP, id), SRI_ARR(DP_SEC_CNTL1, DP, id),   \
305       SRI_ARR(DP_DPHY_BS_SR_SWAP_CNTL, DP, id),                                \
306       SRI_ARR(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)                            \
307   )
308 
309 #define LE_DCN31_REG_LIST_RI(id)                                               \
310   ( \
311   LE_DCN3_REG_LIST_RI(id), SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id),             \
312       SR_ARR(DIO_LINKA_CNTL, id), SR_ARR(DIO_LINKB_CNTL, id),                  \
313       SR_ARR(DIO_LINKC_CNTL, id), SR_ARR(DIO_LINKD_CNTL, id),                  \
314       SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id)                   \
315   )
316 
317 #define UNIPHY_DCN2_REG_LIST_RI(id, phyid)                                     \
318   ( \
319   SRI_ARR_ALPHABET(CLOCK_ENABLE, SYMCLK, id, phyid),                           \
320       SRI_ARR_ALPHABET(CHANNEL_XBAR_CNTL, UNIPHY, id, phyid)                   \
321   )
322 
323 /* HPO DP stream encoder */
324 #define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)                               \
325   ( \
326   SR_ARR(DP_STREAM_MAPPER_CONTROL0, id),                                       \
327       SR_ARR(DP_STREAM_MAPPER_CONTROL1, id),                                   \
328       SR_ARR(DP_STREAM_MAPPER_CONTROL2, id),                                   \
329       SR_ARR(DP_STREAM_MAPPER_CONTROL3, id),                                   \
330       SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),                 \
331       SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),             \
332       SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),                 \
333       SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
334       SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),                         \
335       SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),                \
336       SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
337       SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),                        \
338       SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),                        \
339       SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),                        \
340       SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),                        \
341       SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),                        \
342       SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),                        \
343       SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),                        \
344       SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),                        \
345       SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),                        \
346       SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),                 \
347       SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),   \
348       SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),                \
349       SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),              \
350       SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),                \
351       SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),                     \
352       SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),                \
353       SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),                \
354       SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),                \
355       SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),                \
356       SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),               \
357       SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),     \
358       SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),              \
359       SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id),                 \
360       SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)                   \
361   )
362 
363 /* HPO DP link encoder regs */
364 #define DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)                                 \
365   ( \
366   SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id),                         \
367       SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id),                       \
368       SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id),                        \
369       SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id),                     \
370       SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id),                 \
371       SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id),                 \
372       SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id),                 \
373       SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id),                 \
374       SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id),                   \
375       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id),                    \
376       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id),                    \
377       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id),                    \
378       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id),                    \
379       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id),                    \
380       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id),                    \
381       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id),                    \
382       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id),                    \
383       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id),                    \
384       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id),                    \
385       SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id),                   \
386       SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id),                       \
387       SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id),                       \
388       SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id),                       \
389       SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id),                       \
390       SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id),                 \
391       SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id),                 \
392       SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id),                 \
393       SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id),                 \
394       SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)                     \
395   )
396 
397 /* DPP */
398 #define DPP_REG_LIST_DCN30_COMMON_RI(id)                                       \
399   ( \
400   SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id),             \
401       SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id),        \
402       SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id),    \
403       SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id),                                  \
404       SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \
405       SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \
406       SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id),                                     \
407       SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),                            \
408       SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),                            \
409       SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),                            \
410       SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),                      \
411       SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),                      \
412       SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),                      \
413       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),                             \
414       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),                             \
415       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),                             \
416       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),                             \
417       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),                             \
418       SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),                             \
419       SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id),                              \
420       SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id),                            \
421       SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id),                                \
422       SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id),                                \
423       SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id),                                \
424       SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),                       \
425       SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),                       \
426       SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),                       \
427       SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),                            \
428       SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),                            \
429       SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),                            \
430       SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),                      \
431       SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),                      \
432       SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),                      \
433       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),                             \
434       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),                             \
435       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),                             \
436       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),                             \
437       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),                             \
438       SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),                             \
439       SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id),                              \
440       SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id),                            \
441       SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id),                                \
442       SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id),                                \
443       SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id),                                \
444       SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),                       \
445       SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),                       \
446       SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),                       \
447       SRI_ARR(CM_GAMUT_REMAP_CONTROL, CM, id),                                 \
448       SRI_ARR(CM_GAMUT_REMAP_C11_C12, CM, id),                                 \
449       SRI_ARR(CM_GAMUT_REMAP_C13_C14, CM, id),                                 \
450       SRI_ARR(CM_GAMUT_REMAP_C21_C22, CM, id),                                 \
451       SRI_ARR(CM_GAMUT_REMAP_C23_C24, CM, id),                                 \
452       SRI_ARR(CM_GAMUT_REMAP_C31_C32, CM, id),                                 \
453       SRI_ARR(CM_GAMUT_REMAP_C33_C34, CM, id),                                 \
454       SRI_ARR(CM_GAMUT_REMAP_B_C11_C12, CM, id),                               \
455       SRI_ARR(CM_GAMUT_REMAP_B_C13_C14, CM, id),                               \
456       SRI_ARR(CM_GAMUT_REMAP_B_C21_C22, CM, id),                               \
457       SRI_ARR(CM_GAMUT_REMAP_B_C23_C24, CM, id),                               \
458       SRI_ARR(CM_GAMUT_REMAP_B_C31_C32, CM, id),                               \
459       SRI_ARR(CM_GAMUT_REMAP_B_C33_C34, CM, id),                               \
460       SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id),                         \
461       SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id),                         \
462       SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),          \
463       SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),          \
464       SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),      \
465       SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                      \
466       SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                              \
467       SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                                \
468       SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id),       \
469       SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id),                          \
470       SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id),                          \
471       SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id),                        \
472       SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id),                        \
473       SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id),                                 \
474       SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id),                               \
475       SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id),                                 \
476       SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id),                               \
477       SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id),         \
478       SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id),  \
479       SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id),                                     \
480       SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id),                                  \
481       SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id),                                  \
482       SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id),                                \
483       SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id),                                \
484       SRI_ARR(CM_POST_CSC_CONTROL, CM, id),                                    \
485       SRI_ARR(CM_POST_CSC_C11_C12, CM, id),                                    \
486       SRI_ARR(CM_POST_CSC_C33_C34, CM, id),                                    \
487       SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                  \
488       SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                  \
489       SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),           \
490       SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                   \
491       SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                        \
492       SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id),                                  \
493       SRI_ARR(CURSOR0_COLOR0, CNVC_CUR, id),                                   \
494       SRI_ARR(CURSOR0_COLOR1, CNVC_CUR, id),                                   \
495       SRI_ARR(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id),                            \
496       SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id),    \
497       SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \
498       SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id),                                   \
499       SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id),                                   \
500       SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id),                                   \
501       SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id),                                   \
502       SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id),                                  \
503       SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id),                                  \
504       SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id),                                  \
505       SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id),                              \
506       SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id),                                \
507       SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id),                                  \
508       SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id),                                \
509       SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id),                                 \
510       SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \
511       SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id),                                    \
512       SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id),                                  \
513       SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id)                                     \
514   )
515 
516 /* OPP */
517 #define OPP_REG_LIST_DCN_RI(id)                                                \
518   ( \
519   SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id),      \
520       SRI_ARR(FMT_DITHER_RAND_R_SEED, FMT, id),                                \
521       SRI_ARR(FMT_DITHER_RAND_G_SEED, FMT, id),                                \
522       SRI_ARR(FMT_DITHER_RAND_B_SEED, FMT, id),                                \
523       SRI_ARR(FMT_CLAMP_CNTL, FMT, id),                                        \
524       SRI_ARR(FMT_DYNAMIC_EXP_CNTL, FMT, id),                                  \
525       SRI_ARR(FMT_MAP420_MEMORY_CONTROL, FMT, id),                             \
526       SRI_ARR(OPPBUF_CONTROL, OPPBUF, id),                                     \
527       SRI_ARR(OPPBUF_3D_PARAMETERS_0, OPPBUF, id),                             \
528       SRI_ARR(OPPBUF_3D_PARAMETERS_1, OPPBUF, id),                             \
529       SRI_ARR(OPP_PIPE_CONTROL, OPP_PIPE, id)                                  \
530   )
531 
532 #define OPP_REG_LIST_DCN10_RI(id) OPP_REG_LIST_DCN_RI(id)
533 
534 #define OPP_DPG_REG_LIST_RI(id)                                                \
535   ( \
536   SRI_ARR(DPG_CONTROL, DPG, id), SRI_ARR(DPG_DIMENSIONS, DPG, id),             \
537       SRI_ARR(DPG_OFFSET_SEGMENT, DPG, id), SRI_ARR(DPG_COLOUR_B_CB, DPG, id), \
538       SRI_ARR(DPG_COLOUR_G_Y, DPG, id), SRI_ARR(DPG_COLOUR_R_CR, DPG, id),     \
539       SRI_ARR(DPG_RAMP_CONTROL, DPG, id), SRI_ARR(DPG_STATUS, DPG, id)         \
540   )
541 
542 #define OPP_REG_LIST_DCN30_RI(id)                                              \
543   ( \
544   OPP_REG_LIST_DCN10_RI(id), OPP_DPG_REG_LIST_RI(id),                          \
545       SRI_ARR(FMT_422_CONTROL, FMT, id)                                        \
546   )
547 
548 /* Aux engine regs */
549 #define AUX_COMMON_REG_LIST0_RI(id)                                            \
550   ( \
551   SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_ARB_CONTROL, DP_AUX, id),      \
552       SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id),   \
553       SRI_ARR(AUX_INTERRUPT_CONTROL, DP_AUX, id),                              \
554       SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id),                               \
555       SRI_ARR(AUX_SW_STATUS, DP_AUX, id)                                       \
556   )
557 
558 /* DWBC */
559 #define DWBC_COMMON_REG_LIST_DCN30_RI(id)                                      \
560   ( \
561   SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id),               \
562       SR_ARR(FC_MODE_CTRL, id), SR_ARR(FC_FLOW_CTRL, id),                      \
563       SR_ARR(FC_WINDOW_START, id), SR_ARR(FC_WINDOW_SIZE, id),                 \
564       SR_ARR(FC_SOURCE_SIZE, id), SR_ARR(DWB_UPDATE_CTRL, id),                 \
565       SR_ARR(DWB_CRC_CTRL, id), SR_ARR(DWB_CRC_MASK_R_G, id),                  \
566       SR_ARR(DWB_CRC_MASK_B_A, id), SR_ARR(DWB_CRC_VAL_R_G, id),               \
567       SR_ARR(DWB_CRC_VAL_B_A, id), SR_ARR(DWB_OUT_CTRL, id),                   \
568       SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, id),                            \
569       SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT, id),                               \
570       SR_ARR(DWB_HOST_READ_CONTROL, id), SR_ARR(DWB_SOFT_RESET, id),           \
571       SR_ARR(DWB_HDR_MULT_COEF, id), SR_ARR(DWB_GAMUT_REMAP_MODE, id),         \
572       SR_ARR(DWB_GAMUT_REMAP_COEF_FORMAT, id),                                 \
573       SR_ARR(DWB_GAMUT_REMAPA_C11_C12, id),                                    \
574       SR_ARR(DWB_GAMUT_REMAPA_C13_C14, id),                                    \
575       SR_ARR(DWB_GAMUT_REMAPA_C21_C22, id),                                    \
576       SR_ARR(DWB_GAMUT_REMAPA_C23_C24, id),                                    \
577       SR_ARR(DWB_GAMUT_REMAPA_C31_C32, id),                                    \
578       SR_ARR(DWB_GAMUT_REMAPA_C33_C34, id),                                    \
579       SR_ARR(DWB_GAMUT_REMAPB_C11_C12, id),                                    \
580       SR_ARR(DWB_GAMUT_REMAPB_C13_C14, id),                                    \
581       SR_ARR(DWB_GAMUT_REMAPB_C21_C22, id),                                    \
582       SR_ARR(DWB_GAMUT_REMAPB_C23_C24, id),                                    \
583       SR_ARR(DWB_GAMUT_REMAPB_C31_C32, id),                                    \
584       SR_ARR(DWB_GAMUT_REMAPB_C33_C34, id), SR_ARR(DWB_OGAM_CONTROL, id),      \
585       SR_ARR(DWB_OGAM_LUT_INDEX, id), SR_ARR(DWB_OGAM_LUT_DATA, id),           \
586       SR_ARR(DWB_OGAM_LUT_CONTROL, id),                                        \
587       SR_ARR(DWB_OGAM_RAMA_START_CNTL_B, id),                                  \
588       SR_ARR(DWB_OGAM_RAMA_START_CNTL_G, id),                                  \
589       SR_ARR(DWB_OGAM_RAMA_START_CNTL_R, id),                                  \
590       SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_B, id),                             \
591       SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, id),                            \
592       SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_G, id),                             \
593       SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, id),                            \
594       SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_R, id),                             \
595       SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, id),                            \
596       SR_ARR(DWB_OGAM_RAMA_END_CNTL1_B, id),                                   \
597       SR_ARR(DWB_OGAM_RAMA_END_CNTL2_B, id),                                   \
598       SR_ARR(DWB_OGAM_RAMA_END_CNTL1_G, id),                                   \
599       SR_ARR(DWB_OGAM_RAMA_END_CNTL2_G, id),                                   \
600       SR_ARR(DWB_OGAM_RAMA_END_CNTL1_R, id),                                   \
601       SR_ARR(DWB_OGAM_RAMA_END_CNTL2_R, id),                                   \
602       SR_ARR(DWB_OGAM_RAMA_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMA_OFFSET_G, id),  \
603       SR_ARR(DWB_OGAM_RAMA_OFFSET_R, id),                                      \
604       SR_ARR(DWB_OGAM_RAMA_REGION_0_1, id),                                    \
605       SR_ARR(DWB_OGAM_RAMA_REGION_2_3, id),                                    \
606       SR_ARR(DWB_OGAM_RAMA_REGION_4_5, id),                                    \
607       SR_ARR(DWB_OGAM_RAMA_REGION_6_7, id),                                    \
608       SR_ARR(DWB_OGAM_RAMA_REGION_8_9, id),                                    \
609       SR_ARR(DWB_OGAM_RAMA_REGION_10_11, id),                                  \
610       SR_ARR(DWB_OGAM_RAMA_REGION_12_13, id),                                  \
611       SR_ARR(DWB_OGAM_RAMA_REGION_14_15, id),                                  \
612       SR_ARR(DWB_OGAM_RAMA_REGION_16_17, id),                                  \
613       SR_ARR(DWB_OGAM_RAMA_REGION_18_19, id),                                  \
614       SR_ARR(DWB_OGAM_RAMA_REGION_20_21, id),                                  \
615       SR_ARR(DWB_OGAM_RAMA_REGION_22_23, id),                                  \
616       SR_ARR(DWB_OGAM_RAMA_REGION_24_25, id),                                  \
617       SR_ARR(DWB_OGAM_RAMA_REGION_26_27, id),                                  \
618       SR_ARR(DWB_OGAM_RAMA_REGION_28_29, id),                                  \
619       SR_ARR(DWB_OGAM_RAMA_REGION_30_31, id),                                  \
620       SR_ARR(DWB_OGAM_RAMA_REGION_32_33, id),                                  \
621       SR_ARR(DWB_OGAM_RAMB_START_CNTL_B, id),                                  \
622       SR_ARR(DWB_OGAM_RAMB_START_CNTL_G, id),                                  \
623       SR_ARR(DWB_OGAM_RAMB_START_CNTL_R, id),                                  \
624       SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_B, id),                             \
625       SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, id),                            \
626       SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_G, id),                             \
627       SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, id),                            \
628       SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_R, id),                             \
629       SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, id),                            \
630       SR_ARR(DWB_OGAM_RAMB_END_CNTL1_B, id),                                   \
631       SR_ARR(DWB_OGAM_RAMB_END_CNTL2_B, id),                                   \
632       SR_ARR(DWB_OGAM_RAMB_END_CNTL1_G, id),                                   \
633       SR_ARR(DWB_OGAM_RAMB_END_CNTL2_G, id),                                   \
634       SR_ARR(DWB_OGAM_RAMB_END_CNTL1_R, id),                                   \
635       SR_ARR(DWB_OGAM_RAMB_END_CNTL2_R, id),                                   \
636       SR_ARR(DWB_OGAM_RAMB_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMB_OFFSET_G, id),  \
637       SR_ARR(DWB_OGAM_RAMB_OFFSET_R, id),                                      \
638       SR_ARR(DWB_OGAM_RAMB_REGION_0_1, id),                                    \
639       SR_ARR(DWB_OGAM_RAMB_REGION_2_3, id),                                    \
640       SR_ARR(DWB_OGAM_RAMB_REGION_4_5, id),                                    \
641       SR_ARR(DWB_OGAM_RAMB_REGION_6_7, id),                                    \
642       SR_ARR(DWB_OGAM_RAMB_REGION_8_9, id),                                    \
643       SR_ARR(DWB_OGAM_RAMB_REGION_10_11, id),                                  \
644       SR_ARR(DWB_OGAM_RAMB_REGION_12_13, id),                                  \
645       SR_ARR(DWB_OGAM_RAMB_REGION_14_15, id),                                  \
646       SR_ARR(DWB_OGAM_RAMB_REGION_16_17, id),                                  \
647       SR_ARR(DWB_OGAM_RAMB_REGION_18_19, id),                                  \
648       SR_ARR(DWB_OGAM_RAMB_REGION_20_21, id),                                  \
649       SR_ARR(DWB_OGAM_RAMB_REGION_22_23, id),                                  \
650       SR_ARR(DWB_OGAM_RAMB_REGION_24_25, id),                                  \
651       SR_ARR(DWB_OGAM_RAMB_REGION_26_27, id),                                  \
652       SR_ARR(DWB_OGAM_RAMB_REGION_28_29, id),                                  \
653       SR_ARR(DWB_OGAM_RAMB_REGION_30_31, id),                                  \
654       SR_ARR(DWB_OGAM_RAMB_REGION_32_33, id)                                   \
655   )
656 
657 /* MCIF */
658 
659 #define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst)                                 \
660   ( \
661   SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),                          \
662       SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),                          \
663       SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst),                              \
664       SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),                           \
665       SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),                          \
666       SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),                           \
667       SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),                          \
668       SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),                           \
669       SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),                          \
670       SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),                           \
671       SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),                          \
672       SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),                    \
673       SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),                            \
674       SRI2_ARR(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),                       \
675       SRI2_ARR(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),                        \
676       SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),                           \
677       SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),                           \
678       SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),                           \
679       SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),                           \
680       SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),                           \
681       SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),                           \
682       SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),                           \
683       SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),                           \
684       SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),                     \
685       SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),           \
686       SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),                      \
687       SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst),                             \
688       SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),                    \
689       SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),                   \
690       SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),                           \
691       SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),                         \
692       SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),                          \
693       SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),                        \
694       SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),                      \
695       SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),                      \
696       SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),                      \
697       SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),                      \
698       SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),                      \
699       SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),                      \
700       SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),                      \
701       SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),                      \
702       SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),                       \
703       SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),                       \
704       SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),                       \
705       SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),                       \
706       SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),                         \
707       SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),                   \
708       SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),                \
709       SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),                 \
710       SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)                 \
711   )
712 
713 /* DSC */
714 
715 #define DSC_REG_LIST_DCN20_RI(id)                                              \
716   ( \
717   SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id),                                       \
718       SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id),                                 \
719       SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id),        \
720       SRI_ARR(DSCC_STATUS, DSCC, id),                                          \
721       SRI_ARR(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),                        \
722       SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id),                                     \
723       SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id),                                     \
724       SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id),                                     \
725       SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id),                                     \
726       SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id),                                     \
727       SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id),                                     \
728       SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id),                                     \
729       SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id),                                     \
730       SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id),                                     \
731       SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id),                                     \
732       SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id),                                    \
733       SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id),                                    \
734       SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id),                                    \
735       SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id),                                    \
736       SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id),                                    \
737       SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id),                                    \
738       SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id),                                    \
739       SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id),                                    \
740       SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id),                                    \
741       SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id),                                    \
742       SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id),                                    \
743       SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id),                                    \
744       SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id),                                    \
745       SRI_ARR(DSCC_MEM_POWER_CONTROL, DSCC, id),                               \
746       SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),                         \
747       SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),                         \
748       SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),                        \
749       SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),                        \
750       SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),                        \
751       SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),                        \
752       SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id),                                  \
753       SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id),                                  \
754       SRI_ARR(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),                 \
755       SRI_ARR(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),                 \
756       SRI_ARR(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),                 \
757       SRI_ARR(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),                 \
758       SRI_ARR(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),         \
759       SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),         \
760       SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),         \
761       SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),         \
762       SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id),                                     \
763       SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id),                                     \
764       SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)                             \
765   )
766 
767 /* MPC */
768 
769 #define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)                                   \
770   SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)
771 
772 #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)                            \
773   ( \
774   SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)          \
775   )
776 
777 #define MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)                                   \
778   ( \
779   MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(CSC_MODE, MPC_OUT, inst),  \
780       SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst),  \
781       SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst),  \
782       SRII(DENORM_CONTROL, MPC_OUT, inst),                                     \
783       SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),                                   \
784       SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT)      \
785   )
786 
787 #define MPC_COMMON_REG_LIST_DCN1_0_RI(inst)                                    \
788   ( \
789   SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst),              \
790       SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst),           \
791       SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst),            \
792       SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst),          \
793       SRII(MPCC_SM_CONTROL, MPCC, inst),                                       \
794       SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)                                   \
795   )
796 
797 #define MPC_REG_LIST_DCN3_0_RI(inst)                                           \
798   ( \
799   MPC_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(MPCC_TOP_GAIN, MPCC, inst),        \
800       SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),                                  \
801       SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),                                 \
802       SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),                                     \
803       SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),                              \
804       SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),                               \
805       SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),                     \
806       SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),                            \
807       SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),                        \
808       SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),                        \
809       SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),                        \
810       SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),                        \
811       SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),                      \
812       SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),                      \
813       SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),                      \
814       SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),                \
815       SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),                \
816       SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),                \
817       SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),                       \
818       SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),                       \
819       SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),                       \
820       SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),                       \
821       SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),                       \
822       SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),                       \
823       SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),                        \
824       SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),                      \
825       SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),                          \
826       SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),                          \
827       SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),                          \
828       SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),                 \
829       SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),                 \
830       SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),                 \
831       SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),                      \
832       SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),                      \
833       SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),                      \
834       SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),                \
835       SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),                \
836       SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),                \
837       SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),                       \
838       SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),                       \
839       SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),                       \
840       SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),                       \
841       SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),                       \
842       SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),                       \
843       SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),                        \
844       SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),                      \
845       SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),                          \
846       SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),                          \
847       SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),                          \
848       SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),                 \
849       SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),                 \
850       SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),                 \
851       SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),                                \
852       SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)                             \
853   )
854 
855 #define MPC_REG_LIST_DCN3_2_RI(inst) \
856 	MPC_REG_LIST_DCN3_0_RI(inst),\
857 	SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
858 	SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
859 	SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
860 	SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
861 	SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
862 	SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
863 	SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
864 	SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
865 	SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
866 	SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
867 	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
868 	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
869 	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
870 	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
871 	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
872 	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
873 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
874 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
875 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
876 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
877 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
878 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
879 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
880 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
881 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
882 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
883 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
884 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
885 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
886 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
887 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
888 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
889 	SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
890 	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
891 	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
892 	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
893 	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
894 	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
895 	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
896 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
897 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
898 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
899 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
900 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
901 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
902 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
903 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
904 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
905 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
906 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
907 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
908 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
909 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
910 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
911 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
912 	SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\
913 	SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\
914 	SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
915 	SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
916 	SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
917 	SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
918 	SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
919 	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
920 	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
921 	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
922 	SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
923 	SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\
924 	SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\
925 	SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\
926 	SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\
927 	SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\
928 	SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\
929 	SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
930 	SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
931 	SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
932 	SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\
933 	SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\
934 	SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\
935 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\
936 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\
937 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\
938 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\
939 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\
940 	SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\
941 	SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\
942 	SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\
943 	SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\
944 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\
945 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\
946 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\
947 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\
948 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\
949 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\
950 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\
951 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\
952 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\
953 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\
954 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\
955 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\
956 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\
957 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\
958 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\
959 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\
960 	SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\
961 	SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\
962 	SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\
963 	SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\
964 	SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
965 	SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
966 	SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
967 	SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\
968 	SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\
969 	SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\
970 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\
971 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\
972 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\
973 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\
974 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\
975 	SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\
976 	SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\
977 	SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\
978 	SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\
979 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\
980 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\
981 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\
982 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\
983 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\
984 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\
985 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\
986 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\
987 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\
988 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\
989 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\
990 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\
991 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\
992 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\
993 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\
994 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\
995 	SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\
996 	SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
997 
998 /* OPTC */
999 
1000 #define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst)                                   \
1001   ( \
1002   SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),                                      \
1003       SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),                                   \
1004       SRI_ARR(OTG_VREADY_PARAM, OTG, inst),                                    \
1005       SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),                              \
1006       SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),                                 \
1007       SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
1008       SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
1009       SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),                                 \
1010       SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),                           \
1011       SRI_ARR(OTG_H_TOTAL, OTG, inst),                                         \
1012       SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),                               \
1013       SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
1014       SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst),  \
1015       SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),                               \
1016       SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
1017       SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
1018       SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),                            \
1019       SRI_ARR(OTG_STEREO_STATUS, OTG, inst),                                   \
1020       SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),                                     \
1021       SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),                                     \
1022       SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),                                 \
1023       SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),                                      \
1024       SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),                            \
1025       SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),                           \
1026       SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),                              \
1027       SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
1028       SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),                               \
1029       SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),                                    \
1030       SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),                                    \
1031       SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),                                   \
1032       SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),                     \
1033       SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),                    \
1034       SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),                     \
1035       SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),                    \
1036       SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),                     \
1037       SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),                    \
1038       SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),                            \
1039       SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),                             \
1040       SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),                           \
1041       SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),  \
1042       SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst),   \
1043       SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),                                    \
1044       SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),                                     \
1045       SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),                          \
1046       SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),                          \
1047       SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),                          \
1048       SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),                          \
1049       SR_ARR(GSL_SOURCE_SELECT, inst),                                         \
1050       SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),                               \
1051       SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
1052       SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
1053       SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),                                    \
1054       SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),                                    \
1055       SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),                                 \
1056       SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),                              \
1057       SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),                              \
1058       SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),                              \
1059       SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),                            \
1060       SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \
1061       SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \
1062       SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
1063       SRI_ARR(OTG_DRR_CONTROL, OTG, inst)                                      \
1064   )
1065 
1066 /* HUBP */
1067 
1068 #define HUBP_REG_LIST_DCN_VM_RI(id)                                            \
1069   ( \
1070   SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id),                                      \
1071       SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id),                                  \
1072       SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id),                                  \
1073       SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id),                                  \
1074       SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)                              \
1075   )
1076 
1077 #define HUBP_REG_LIST_DCN_RI(id)                                               \
1078   ( \
1079   SRI_ARR(DCHUBP_CNTL, HUBP, id), SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id),         \
1080       SRI_ARR(HUBPREQ_DEBUG, HUBP, id), SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
1081       SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id),                                 \
1082       SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id),                              \
1083       SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),                            \
1084       SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id),                                \
1085       SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id),                               \
1086       SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id),                        \
1087       SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id),                            \
1088       SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id),                        \
1089       SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id),                            \
1090       SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id),                      \
1091       SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id),                          \
1092       SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id),                      \
1093       SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id),                          \
1094       SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),               \
1095       SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),                    \
1096       SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),             \
1097       SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),                  \
1098       SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),          \
1099       SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),               \
1100       SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),        \
1101       SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),             \
1102       SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),             \
1103       SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),                  \
1104       SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),           \
1105       SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),                \
1106       SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),        \
1107       SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),             \
1108       SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),      \
1109       SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),           \
1110       SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id),                              \
1111       SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),                         \
1112       SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),                            \
1113       SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),                       \
1114       SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),                     \
1115       SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),                \
1116       SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),                   \
1117       SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),              \
1118       SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id),                            \
1119       SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),                     \
1120       SRI_ARR(HUBPRET_CONTROL, HUBPRET, id),                                   \
1121       SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id),                          \
1122       SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id),                                \
1123       SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),                               \
1124       SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),                             \
1125       SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id),                                    \
1126       SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id),                                    \
1127       SRI_ARR(DST_DIMENSIONS, HUBPREQ, id),                                    \
1128       SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id),                                  \
1129       SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id),                               \
1130       SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),                              \
1131       SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id),                               \
1132       SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id),                               \
1133       SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id),                                  \
1134       SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id),                                  \
1135       SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id),                             \
1136       SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id),                                 \
1137       SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id),                               \
1138       SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id),                               \
1139       SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id),                                  \
1140       SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id),                                  \
1141       SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id),                                    \
1142       SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),                               \
1143       SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),                               \
1144       SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),                               \
1145       SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),                               \
1146       SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),                               \
1147       SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),                                \
1148       SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),                                \
1149       SRI_ARR(HUBP_CLK_CNTL, HUBP, id)                                         \
1150   )
1151 
1152 #define HUBP_REG_LIST_DCN2_COMMON_RI(id)                                       \
1153   ( \
1154   HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id),                       \
1155       SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id),                                 \
1156       SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id),                               \
1157       SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),                   \
1158       SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),                  \
1159       SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id),                                   \
1160       SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id),                      \
1161       SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id),                           \
1162       SRI_ARR(CURSOR_SIZE, CURSOR0_, id),                                      \
1163       SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \
1164       SRI_ARR(CURSOR_POSITION, CURSOR0_, id),                                  \
1165       SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id),                                  \
1166       SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id),                                \
1167       SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id),                              \
1168       SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id),                               \
1169       SRI_ARR(DMDATA_CNTL, CURSOR0_, id),                                      \
1170       SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id),                                   \
1171       SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id),                                  \
1172       SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id),                                   \
1173       SRI_ARR(DMDATA_STATUS, CURSOR0_, id),                                    \
1174       SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id),                                 \
1175       SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id),                                 \
1176       SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id),                                 \
1177       SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),                                \
1178       SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),                                \
1179       SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id),                              \
1180       SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id)                                    \
1181   )
1182 
1183 #define HUBP_REG_LIST_DCN21_RI(id)                                             \
1184   ( \
1185   HUBP_REG_LIST_DCN2_COMMON_RI(id), SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id),   \
1186       SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id),                                 \
1187       SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id),                                 \
1188       SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id),                                 \
1189       SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id),                               \
1190       SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id)                                \
1191   )
1192 
1193 #define HUBP_REG_LIST_DCN30_RI(id)                                             \
1194   ( \
1195   HUBP_REG_LIST_DCN21_RI(id), SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id)         \
1196   )
1197 
1198 #define HUBP_REG_LIST_DCN32_RI(id)                                             \
1199   ( \
1200   HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id),           \
1201       SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),                                   \
1202       SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id)                                  \
1203   )
1204 
1205 /* HUBBUB */
1206 
1207 #define HUBBUB_REG_LIST_DCN32_RI(id)                                           \
1208   ( \
1209   SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),                                   \
1210       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),                               \
1211       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),                               \
1212       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),                               \
1213       SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),                                  \
1214       SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL),            \
1215       SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL),        \
1216       SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL),                          \
1217       SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP),                 \
1218       SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP),            \
1219       SR(DCN_VM_AGP_BASE), HUBBUB_SR_WATERMARK_REG_LIST(),                     \
1220       SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),  \
1221       SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),  \
1222       SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),                                     \
1223       SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),                                     \
1224       SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),                                     \
1225       SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),                                     \
1226       SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),                            \
1227       SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),                            \
1228       SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),                            \
1229       SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D), SR(DCHUBBUB_DET0_CTRL),    \
1230       SR(DCHUBBUB_DET1_CTRL), SR(DCHUBBUB_DET2_CTRL), SR(DCHUBBUB_DET3_CTRL),  \
1231       SR(DCHUBBUB_COMPBUF_CTRL), SR(COMPBUF_RESERVED_SPACE),                   \
1232       SR(DCHUBBUB_DEBUG_CTRL_0),                                               \
1233       SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),                                    \
1234       SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),                             \
1235       SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),                             \
1236       SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),                             \
1237       SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),                             \
1238       SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),                         \
1239       SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),                         \
1240       SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),                         \
1241       SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),                         \
1242       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),                         \
1243       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),                         \
1244       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),                         \
1245       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),                         \
1246       SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \
1247       SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS)                           \
1248   )
1249 
1250 /* DCCG */
1251 
1252 #define DCCG_REG_LIST_DCN32_RI()                                               \
1253   ( \
1254   SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0),                        \
1255       DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2),        \
1256       DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),  \
1257       SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL),                    \
1258       SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL),                    \
1259       SR(PHYESYMCLK_CLOCK_CNTL), SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \
1260       SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL),                              \
1261       DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),  \
1262       DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),  \
1263       DCCG_SRII(MODULO, DTBCLK_DTO, 0), DCCG_SRII(MODULO, DTBCLK_DTO, 1),      \
1264       DCCG_SRII(MODULO, DTBCLK_DTO, 2), DCCG_SRII(MODULO, DTBCLK_DTO, 3),      \
1265       DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1),        \
1266       DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3),        \
1267       SR(DCCG_AUDIO_DTBCLK_DTO_MODULO), SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),       \
1268       SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), SR(DCCG_AUDIO_DTO_SOURCE)     \
1269   )
1270 
1271 /* VMID */
1272 #define DCN20_VMID_REG_LIST_RI(id)                                             \
1273   ( \
1274   SRI_ARR(CNTL, DCN_VM_CONTEXT, id),                                           \
1275       SRI_ARR(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),                  \
1276       SRI_ARR(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),                  \
1277       SRI_ARR(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),                 \
1278       SRI_ARR(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),                 \
1279       SRI_ARR(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),                   \
1280       SRI_ARR(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)                    \
1281   )
1282 
1283 /* I2C HW */
1284 
1285 #define I2C_HW_ENGINE_COMMON_REG_LIST_RI(id)                                   \
1286   ( \
1287       SRI_ARR_I2C(SETUP, DC_I2C_DDC, id), SRI_ARR_I2C(SPEED, DC_I2C_DDC, id),  \
1288       SRI_ARR_I2C(HW_STATUS, DC_I2C_DDC, id),                                  \
1289       SR_ARR_I2C(DC_I2C_ARBITRATION, id),                                      \
1290       SR_ARR_I2C(DC_I2C_CONTROL, id), SR_ARR_I2C(DC_I2C_SW_STATUS, id),        \
1291       SR_ARR_I2C(DC_I2C_TRANSACTION0, id), SR_ARR_I2C(DC_I2C_TRANSACTION1, id),\
1292       SR_ARR_I2C(DC_I2C_TRANSACTION2, id), SR_ARR_I2C(DC_I2C_TRANSACTION3, id),\
1293       SR_ARR_I2C(DC_I2C_DATA, id), SR_ARR_I2C(MICROSECOND_TIME_BASE_DIV, id)          \
1294   )
1295 
1296 #define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)                             \
1297   ( \
1298       I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR_I2C(DIO_MEM_PWR_CTRL, id),  \
1299       SR_ARR_I2C(DIO_MEM_PWR_STATUS, id)                                           \
1300   )
1301 
1302 #endif /* _DCN32_RESOURCE_H_ */
1303