1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dcn31/dcn31_apg.h" 61 #include "dcn31/dcn31_dio_link_encoder.h" 62 #include "dcn32/dcn32_dio_link_encoder.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn32/dcn32_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "link.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn32/dcn32_mmhubbub.h" 76 77 #include "dcn/dcn_3_2_0_offset.h" 78 #include "dcn/dcn_3_2_0_sh_mask.h" 79 #include "nbio/nbio_4_3_0_offset.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/display_mode_vba_30.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dml/dcn32/dcn32_fpu.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 enum dcn32_clk_src_array_id { 95 DCN32_CLK_SRC_PLL0, 96 DCN32_CLK_SRC_PLL1, 97 DCN32_CLK_SRC_PLL2, 98 DCN32_CLK_SRC_PLL3, 99 DCN32_CLK_SRC_PLL4, 100 DCN32_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 109 110 #define BASE(seg) BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 114 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 117 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name = value 120 121 #define SRI(reg_name, block, id)\ 122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 reg ## block ## id ## _ ## reg_name 124 125 #define SRI_ARR(reg_name, block, id)\ 126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SR_ARR_I2C(reg_name, id) \ 130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 131 132 #define SRI_ARR_I2C(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI2(reg_name, block, id)\ 141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 142 reg ## reg_name 143 #define SRI2_ARR(reg_name, block, id)\ 144 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRIR(var_name, reg_name, block, id)\ 148 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRII(reg_name, block, id)\ 152 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII_ARR_2(reg_name, block, id, inst)\ 156 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_MPC_RMU(reg_name, block, id)\ 160 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_DWB(reg_name, temp_name, block, id)\ 164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## temp_name 166 167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 //DPCS_DCN31_MASK_SH_LIST(_MASK) 328 }; 329 330 #define hpo_dp_stream_encoder_reg_init(id)\ 331 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 332 333 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 334 335 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 336 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 337 }; 338 339 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 341 }; 342 343 344 #define hpo_dp_link_encoder_reg_init(id)\ 345 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 346 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 347 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 350 351 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 352 353 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 354 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 355 }; 356 357 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 359 }; 360 361 #define dpp_regs_init(id)\ 362 DPP_REG_LIST_DCN30_COMMON_RI(id) 363 364 static struct dcn3_dpp_registers dpp_regs[4]; 365 366 static const struct dcn3_dpp_shift tf_shift = { 367 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 368 }; 369 370 static const struct dcn3_dpp_mask tf_mask = { 371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 372 }; 373 374 375 #define opp_regs_init(id)\ 376 OPP_REG_LIST_DCN30_RI(id) 377 378 static struct dcn20_opp_registers opp_regs[4]; 379 380 static const struct dcn20_opp_shift opp_shift = { 381 OPP_MASK_SH_LIST_DCN20(__SHIFT) 382 }; 383 384 static const struct dcn20_opp_mask opp_mask = { 385 OPP_MASK_SH_LIST_DCN20(_MASK) 386 }; 387 388 #define aux_engine_regs_init(id)\ 389 ( \ 390 AUX_COMMON_REG_LIST0_RI(id), \ 391 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 392 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 395 ) 396 397 static struct dce110_aux_registers aux_engine_regs[5]; 398 399 static const struct dce110_aux_registers_shift aux_shift = { 400 DCN_AUX_MASK_SH_LIST(__SHIFT) 401 }; 402 403 static const struct dce110_aux_registers_mask aux_mask = { 404 DCN_AUX_MASK_SH_LIST(_MASK) 405 }; 406 407 #define dwbc_regs_dcn3_init(id)\ 408 DWBC_COMMON_REG_LIST_DCN30_RI(id) 409 410 static struct dcn30_dwbc_registers dwbc30_regs[1]; 411 412 static const struct dcn30_dwbc_shift dwbc30_shift = { 413 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 414 }; 415 416 static const struct dcn30_dwbc_mask dwbc30_mask = { 417 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 418 }; 419 420 #define mcif_wb_regs_dcn3_init(id)\ 421 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 422 423 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 424 425 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 426 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 427 }; 428 429 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 430 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 431 }; 432 433 #define dsc_regsDCN20_init(id)\ 434 DSC_REG_LIST_DCN20_RI(id) 435 436 static struct dcn20_dsc_registers dsc_regs[4]; 437 438 static const struct dcn20_dsc_shift dsc_shift = { 439 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 440 }; 441 442 static const struct dcn20_dsc_mask dsc_mask = { 443 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 444 }; 445 446 static struct dcn30_mpc_registers mpc_regs; 447 448 #define dcn_mpc_regs_init() \ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id)\ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 486 static const struct dcn_hubp2_shift hubp_shift = { 487 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 488 }; 489 490 static const struct dcn_hubp2_mask hubp_mask = { 491 HUBP_MASK_SH_LIST_DCN32(_MASK) 492 }; 493 494 static struct dcn_hubbub_registers hubbub_reg; 495 #define hubbub_reg_init()\ 496 HUBBUB_REG_LIST_DCN32_RI(0) 497 498 static const struct dcn_hubbub_shift hubbub_shift = { 499 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 500 }; 501 502 static const struct dcn_hubbub_mask hubbub_mask = { 503 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 504 }; 505 506 static struct dccg_registers dccg_regs; 507 508 #define dccg_regs_init()\ 509 DCCG_REG_LIST_DCN32_RI() 510 511 static const struct dccg_shift dccg_shift = { 512 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 513 }; 514 515 static const struct dccg_mask dccg_mask = { 516 DCCG_MASK_SH_LIST_DCN32(_MASK) 517 }; 518 519 520 #define SRII2(reg_name_pre, reg_name_post, id)\ 521 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 522 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 523 reg ## reg_name_pre ## id ## _ ## reg_name_post 524 525 526 #define HWSEQ_DCN32_REG_LIST()\ 527 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 528 SR(DIO_MEM_PWR_CTRL), \ 529 SR(ODM_MEM_PWR_CTRL3), \ 530 SR(MMHUBBUB_MEM_PWR_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL2), \ 533 SR(DCFCLK_CNTL),\ 534 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 543 SR(MICROSECOND_TIME_BASE_DIV), \ 544 SR(MILLISECOND_TIME_BASE_DIV), \ 545 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 546 SR(RBBMIF_TIMEOUT_DIS), \ 547 SR(RBBMIF_TIMEOUT_DIS_2), \ 548 SR(DCHUBBUB_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 552 SR(MPC_CRC_CTRL), \ 553 SR(MPC_CRC_RESULT_GB), \ 554 SR(MPC_CRC_RESULT_C), \ 555 SR(MPC_CRC_RESULT_AR), \ 556 SR(DOMAIN0_PG_CONFIG), \ 557 SR(DOMAIN1_PG_CONFIG), \ 558 SR(DOMAIN2_PG_CONFIG), \ 559 SR(DOMAIN3_PG_CONFIG), \ 560 SR(DOMAIN16_PG_CONFIG), \ 561 SR(DOMAIN17_PG_CONFIG), \ 562 SR(DOMAIN18_PG_CONFIG), \ 563 SR(DOMAIN19_PG_CONFIG), \ 564 SR(DOMAIN0_PG_STATUS), \ 565 SR(DOMAIN1_PG_STATUS), \ 566 SR(DOMAIN2_PG_STATUS), \ 567 SR(DOMAIN3_PG_STATUS), \ 568 SR(DOMAIN16_PG_STATUS), \ 569 SR(DOMAIN17_PG_STATUS), \ 570 SR(DOMAIN18_PG_STATUS), \ 571 SR(DOMAIN19_PG_STATUS), \ 572 SR(D1VGA_CONTROL), \ 573 SR(D2VGA_CONTROL), \ 574 SR(D3VGA_CONTROL), \ 575 SR(D4VGA_CONTROL), \ 576 SR(D5VGA_CONTROL), \ 577 SR(D6VGA_CONTROL), \ 578 SR(DC_IP_REQUEST_CNTL), \ 579 SR(AZALIA_AUDIO_DTO), \ 580 SR(AZALIA_CONTROLLER_CLOCK_GATING) 581 582 static struct dce_hwseq_registers hwseq_reg; 583 584 #define hwseq_reg_init()\ 585 HWSEQ_DCN32_REG_LIST() 586 587 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 588 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 589 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 615 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 616 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 619 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 620 621 static const struct dce_hwseq_shift hwseq_shift = { 622 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 623 }; 624 625 static const struct dce_hwseq_mask hwseq_mask = { 626 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 627 }; 628 #define vmid_regs_init(id)\ 629 DCN20_VMID_REG_LIST_RI(id) 630 631 static struct dcn_vmid_registers vmid_regs[16]; 632 633 static const struct dcn20_vmid_shift vmid_shifts = { 634 DCN20_VMID_MASK_SH_LIST(__SHIFT) 635 }; 636 637 static const struct dcn20_vmid_mask vmid_masks = { 638 DCN20_VMID_MASK_SH_LIST(_MASK) 639 }; 640 641 static const struct resource_caps res_cap_dcn32 = { 642 .num_timing_generator = 4, 643 .num_opp = 4, 644 .num_video_plane = 4, 645 .num_audio = 5, 646 .num_stream_encoder = 5, 647 .num_hpo_dp_stream_encoder = 4, 648 .num_hpo_dp_link_encoder = 2, 649 .num_pll = 5, 650 .num_dwb = 1, 651 .num_ddc = 5, 652 .num_vmid = 16, 653 .num_mpc_3dlut = 4, 654 .num_dsc = 4, 655 }; 656 657 static const struct dc_plane_cap plane_cap = { 658 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 659 .per_pixel_alpha = true, 660 661 .pixel_format_support = { 662 .argb8888 = true, 663 .nv12 = true, 664 .fp16 = true, 665 .p010 = true, 666 .ayuv = false, 667 }, 668 669 .max_upscale_factor = { 670 .argb8888 = 16000, 671 .nv12 = 16000, 672 .fp16 = 16000 673 }, 674 675 // 6:1 downscaling ratio: 1000/6 = 166.666 676 .max_downscale_factor = { 677 .argb8888 = 167, 678 .nv12 = 167, 679 .fp16 = 167 680 }, 681 64, 682 64 683 }; 684 685 static const struct dc_debug_options debug_defaults_drv = { 686 .disable_dmcu = true, 687 .force_abm_enable = false, 688 .timing_trace = false, 689 .clock_trace = true, 690 .disable_pplib_clock_request = false, 691 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 692 .force_single_disp_pipe_split = false, 693 .disable_dcc = DCC_ENABLE, 694 .vsr_support = true, 695 .performance_trace = false, 696 .max_downscale_src_width = 7680,/*upto 8K*/ 697 .disable_pplib_wm_range = false, 698 .scl_reset_length10 = true, 699 .sanity_checks = false, 700 .underflow_assert_delay_us = 0xFFFFFFFF, 701 .dwb_fi_phase = -1, // -1 = disable, 702 .dmub_command_table = true, 703 .enable_mem_low_power = { 704 .bits = { 705 .vga = false, 706 .i2c = false, 707 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 708 .dscl = false, 709 .cm = false, 710 .mpc = false, 711 .optc = true, 712 } 713 }, 714 .use_max_lb = true, 715 .force_disable_subvp = false, 716 .exit_idle_opt_for_cursor_updates = true, 717 .enable_single_display_2to1_odm_policy = true, 718 719 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 720 .enable_double_buffered_dsc_pg_support = true, 721 .enable_dp_dig_pixel_rate_div_policy = 1, 722 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 723 .alloc_extra_way_for_cursor = true, 724 .min_prefetch_in_strobe_ns = 60000, // 60us 725 .disable_unbounded_requesting = false, 726 .override_dispclk_programming = true, 727 .disable_fpo_optimizations = false, 728 .fpo_vactive_margin_us = 2000, // 2000us 729 .disable_fpo_vactive = false, 730 .disable_boot_optimizations = false, 731 .disable_subvp_high_refresh = false, 732 .disable_dp_plus_plus_wa = true, 733 .fpo_vactive_min_active_margin_us = 200, 734 .fpo_vactive_max_blank_us = 1000, 735 }; 736 737 static struct dce_aux *dcn32_aux_engine_create( 738 struct dc_context *ctx, 739 uint32_t inst) 740 { 741 struct aux_engine_dce110 *aux_engine = 742 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 743 744 if (!aux_engine) 745 return NULL; 746 747 #undef REG_STRUCT 748 #define REG_STRUCT aux_engine_regs 749 aux_engine_regs_init(0), 750 aux_engine_regs_init(1), 751 aux_engine_regs_init(2), 752 aux_engine_regs_init(3), 753 aux_engine_regs_init(4); 754 755 dce110_aux_engine_construct(aux_engine, ctx, inst, 756 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 757 &aux_engine_regs[inst], 758 &aux_mask, 759 &aux_shift, 760 ctx->dc->caps.extended_aux_timeout_support); 761 762 return &aux_engine->base; 763 } 764 #define i2c_inst_regs_init(id)\ 765 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 766 767 static struct dce_i2c_registers i2c_hw_regs[5]; 768 769 static const struct dce_i2c_shift i2c_shifts = { 770 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 771 }; 772 773 static const struct dce_i2c_mask i2c_masks = { 774 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 775 }; 776 777 static struct dce_i2c_hw *dcn32_i2c_hw_create( 778 struct dc_context *ctx, 779 uint32_t inst) 780 { 781 struct dce_i2c_hw *dce_i2c_hw = 782 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 783 784 if (!dce_i2c_hw) 785 return NULL; 786 787 #undef REG_STRUCT 788 #define REG_STRUCT i2c_hw_regs 789 i2c_inst_regs_init(1), 790 i2c_inst_regs_init(2), 791 i2c_inst_regs_init(3), 792 i2c_inst_regs_init(4), 793 i2c_inst_regs_init(5); 794 795 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 796 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 797 798 return dce_i2c_hw; 799 } 800 801 static struct clock_source *dcn32_clock_source_create( 802 struct dc_context *ctx, 803 struct dc_bios *bios, 804 enum clock_source_id id, 805 const struct dce110_clk_src_regs *regs, 806 bool dp_clk_src) 807 { 808 struct dce110_clk_src *clk_src = 809 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 810 811 if (!clk_src) 812 return NULL; 813 814 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 815 regs, &cs_shift, &cs_mask)) { 816 clk_src->base.dp_clk_src = dp_clk_src; 817 return &clk_src->base; 818 } 819 820 kfree(clk_src); 821 BREAK_TO_DEBUGGER(); 822 return NULL; 823 } 824 825 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 826 { 827 int i; 828 829 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 830 GFP_KERNEL); 831 832 if (!hubbub2) 833 return NULL; 834 835 #undef REG_STRUCT 836 #define REG_STRUCT hubbub_reg 837 hubbub_reg_init(); 838 839 #undef REG_STRUCT 840 #define REG_STRUCT vmid_regs 841 vmid_regs_init(0), 842 vmid_regs_init(1), 843 vmid_regs_init(2), 844 vmid_regs_init(3), 845 vmid_regs_init(4), 846 vmid_regs_init(5), 847 vmid_regs_init(6), 848 vmid_regs_init(7), 849 vmid_regs_init(8), 850 vmid_regs_init(9), 851 vmid_regs_init(10), 852 vmid_regs_init(11), 853 vmid_regs_init(12), 854 vmid_regs_init(13), 855 vmid_regs_init(14), 856 vmid_regs_init(15); 857 858 hubbub32_construct(hubbub2, ctx, 859 &hubbub_reg, 860 &hubbub_shift, 861 &hubbub_mask, 862 ctx->dc->dml.ip.det_buffer_size_kbytes, 863 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 864 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 865 866 867 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 868 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 869 870 vmid->ctx = ctx; 871 872 vmid->regs = &vmid_regs[i]; 873 vmid->shifts = &vmid_shifts; 874 vmid->masks = &vmid_masks; 875 } 876 877 return &hubbub2->base; 878 } 879 880 static struct hubp *dcn32_hubp_create( 881 struct dc_context *ctx, 882 uint32_t inst) 883 { 884 struct dcn20_hubp *hubp2 = 885 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 886 887 if (!hubp2) 888 return NULL; 889 890 #undef REG_STRUCT 891 #define REG_STRUCT hubp_regs 892 hubp_regs_init(0), 893 hubp_regs_init(1), 894 hubp_regs_init(2), 895 hubp_regs_init(3); 896 897 if (hubp32_construct(hubp2, ctx, inst, 898 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 899 return &hubp2->base; 900 901 BREAK_TO_DEBUGGER(); 902 kfree(hubp2); 903 return NULL; 904 } 905 906 static void dcn32_dpp_destroy(struct dpp **dpp) 907 { 908 kfree(TO_DCN30_DPP(*dpp)); 909 *dpp = NULL; 910 } 911 912 static struct dpp *dcn32_dpp_create( 913 struct dc_context *ctx, 914 uint32_t inst) 915 { 916 struct dcn3_dpp *dpp3 = 917 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 918 919 if (!dpp3) 920 return NULL; 921 922 #undef REG_STRUCT 923 #define REG_STRUCT dpp_regs 924 dpp_regs_init(0), 925 dpp_regs_init(1), 926 dpp_regs_init(2), 927 dpp_regs_init(3); 928 929 if (dpp32_construct(dpp3, ctx, inst, 930 &dpp_regs[inst], &tf_shift, &tf_mask)) 931 return &dpp3->base; 932 933 BREAK_TO_DEBUGGER(); 934 kfree(dpp3); 935 return NULL; 936 } 937 938 static struct mpc *dcn32_mpc_create( 939 struct dc_context *ctx, 940 int num_mpcc, 941 int num_rmu) 942 { 943 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 944 GFP_KERNEL); 945 946 if (!mpc30) 947 return NULL; 948 949 #undef REG_STRUCT 950 #define REG_STRUCT mpc_regs 951 dcn_mpc_regs_init(); 952 953 dcn32_mpc_construct(mpc30, ctx, 954 &mpc_regs, 955 &mpc_shift, 956 &mpc_mask, 957 num_mpcc, 958 num_rmu); 959 960 return &mpc30->base; 961 } 962 963 static struct output_pixel_processor *dcn32_opp_create( 964 struct dc_context *ctx, uint32_t inst) 965 { 966 struct dcn20_opp *opp2 = 967 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 968 969 if (!opp2) { 970 BREAK_TO_DEBUGGER(); 971 return NULL; 972 } 973 974 #undef REG_STRUCT 975 #define REG_STRUCT opp_regs 976 opp_regs_init(0), 977 opp_regs_init(1), 978 opp_regs_init(2), 979 opp_regs_init(3); 980 981 dcn20_opp_construct(opp2, ctx, inst, 982 &opp_regs[inst], &opp_shift, &opp_mask); 983 return &opp2->base; 984 } 985 986 987 static struct timing_generator *dcn32_timing_generator_create( 988 struct dc_context *ctx, 989 uint32_t instance) 990 { 991 struct optc *tgn10 = 992 kzalloc(sizeof(struct optc), GFP_KERNEL); 993 994 if (!tgn10) 995 return NULL; 996 997 #undef REG_STRUCT 998 #define REG_STRUCT optc_regs 999 optc_regs_init(0), 1000 optc_regs_init(1), 1001 optc_regs_init(2), 1002 optc_regs_init(3); 1003 1004 tgn10->base.inst = instance; 1005 tgn10->base.ctx = ctx; 1006 1007 tgn10->tg_regs = &optc_regs[instance]; 1008 tgn10->tg_shift = &optc_shift; 1009 tgn10->tg_mask = &optc_mask; 1010 1011 dcn32_timing_generator_init(tgn10); 1012 1013 return &tgn10->base; 1014 } 1015 1016 static const struct encoder_feature_support link_enc_feature = { 1017 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1018 .max_hdmi_pixel_clock = 600000, 1019 .hdmi_ycbcr420_supported = true, 1020 .dp_ycbcr420_supported = true, 1021 .fec_supported = true, 1022 .flags.bits.IS_HBR2_CAPABLE = true, 1023 .flags.bits.IS_HBR3_CAPABLE = true, 1024 .flags.bits.IS_TPS3_CAPABLE = true, 1025 .flags.bits.IS_TPS4_CAPABLE = true 1026 }; 1027 1028 static struct link_encoder *dcn32_link_encoder_create( 1029 struct dc_context *ctx, 1030 const struct encoder_init_data *enc_init_data) 1031 { 1032 struct dcn20_link_encoder *enc20 = 1033 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1034 1035 if (!enc20) 1036 return NULL; 1037 1038 #undef REG_STRUCT 1039 #define REG_STRUCT link_enc_aux_regs 1040 aux_regs_init(0), 1041 aux_regs_init(1), 1042 aux_regs_init(2), 1043 aux_regs_init(3), 1044 aux_regs_init(4); 1045 1046 #undef REG_STRUCT 1047 #define REG_STRUCT link_enc_hpd_regs 1048 hpd_regs_init(0), 1049 hpd_regs_init(1), 1050 hpd_regs_init(2), 1051 hpd_regs_init(3), 1052 hpd_regs_init(4); 1053 1054 #undef REG_STRUCT 1055 #define REG_STRUCT link_enc_regs 1056 link_regs_init(0, A), 1057 link_regs_init(1, B), 1058 link_regs_init(2, C), 1059 link_regs_init(3, D), 1060 link_regs_init(4, E); 1061 1062 dcn32_link_encoder_construct(enc20, 1063 enc_init_data, 1064 &link_enc_feature, 1065 &link_enc_regs[enc_init_data->transmitter], 1066 &link_enc_aux_regs[enc_init_data->channel - 1], 1067 &link_enc_hpd_regs[enc_init_data->hpd_source], 1068 &le_shift, 1069 &le_mask); 1070 1071 return &enc20->enc10.base; 1072 } 1073 1074 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1075 { 1076 struct dcn31_panel_cntl *panel_cntl = 1077 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1078 1079 if (!panel_cntl) 1080 return NULL; 1081 1082 dcn31_panel_cntl_construct(panel_cntl, init_data); 1083 1084 return &panel_cntl->base; 1085 } 1086 1087 static void read_dce_straps( 1088 struct dc_context *ctx, 1089 struct resource_straps *straps) 1090 { 1091 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1092 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1093 1094 } 1095 1096 static struct audio *dcn32_create_audio( 1097 struct dc_context *ctx, unsigned int inst) 1098 { 1099 1100 #undef REG_STRUCT 1101 #define REG_STRUCT audio_regs 1102 audio_regs_init(0), 1103 audio_regs_init(1), 1104 audio_regs_init(2), 1105 audio_regs_init(3), 1106 audio_regs_init(4); 1107 1108 return dce_audio_create(ctx, inst, 1109 &audio_regs[inst], &audio_shift, &audio_mask); 1110 } 1111 1112 static struct vpg *dcn32_vpg_create( 1113 struct dc_context *ctx, 1114 uint32_t inst) 1115 { 1116 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1117 1118 if (!vpg3) 1119 return NULL; 1120 1121 #undef REG_STRUCT 1122 #define REG_STRUCT vpg_regs 1123 vpg_regs_init(0), 1124 vpg_regs_init(1), 1125 vpg_regs_init(2), 1126 vpg_regs_init(3), 1127 vpg_regs_init(4), 1128 vpg_regs_init(5), 1129 vpg_regs_init(6), 1130 vpg_regs_init(7), 1131 vpg_regs_init(8), 1132 vpg_regs_init(9); 1133 1134 vpg3_construct(vpg3, ctx, inst, 1135 &vpg_regs[inst], 1136 &vpg_shift, 1137 &vpg_mask); 1138 1139 return &vpg3->base; 1140 } 1141 1142 static struct afmt *dcn32_afmt_create( 1143 struct dc_context *ctx, 1144 uint32_t inst) 1145 { 1146 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1147 1148 if (!afmt3) 1149 return NULL; 1150 1151 #undef REG_STRUCT 1152 #define REG_STRUCT afmt_regs 1153 afmt_regs_init(0), 1154 afmt_regs_init(1), 1155 afmt_regs_init(2), 1156 afmt_regs_init(3), 1157 afmt_regs_init(4), 1158 afmt_regs_init(5); 1159 1160 afmt3_construct(afmt3, ctx, inst, 1161 &afmt_regs[inst], 1162 &afmt_shift, 1163 &afmt_mask); 1164 1165 return &afmt3->base; 1166 } 1167 1168 static struct apg *dcn31_apg_create( 1169 struct dc_context *ctx, 1170 uint32_t inst) 1171 { 1172 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1173 1174 if (!apg31) 1175 return NULL; 1176 1177 #undef REG_STRUCT 1178 #define REG_STRUCT apg_regs 1179 apg_regs_init(0), 1180 apg_regs_init(1), 1181 apg_regs_init(2), 1182 apg_regs_init(3); 1183 1184 apg31_construct(apg31, ctx, inst, 1185 &apg_regs[inst], 1186 &apg_shift, 1187 &apg_mask); 1188 1189 return &apg31->base; 1190 } 1191 1192 static struct stream_encoder *dcn32_stream_encoder_create( 1193 enum engine_id eng_id, 1194 struct dc_context *ctx) 1195 { 1196 struct dcn10_stream_encoder *enc1; 1197 struct vpg *vpg; 1198 struct afmt *afmt; 1199 int vpg_inst; 1200 int afmt_inst; 1201 1202 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1203 if (eng_id <= ENGINE_ID_DIGF) { 1204 vpg_inst = eng_id; 1205 afmt_inst = eng_id; 1206 } else 1207 return NULL; 1208 1209 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1210 vpg = dcn32_vpg_create(ctx, vpg_inst); 1211 afmt = dcn32_afmt_create(ctx, afmt_inst); 1212 1213 if (!enc1 || !vpg || !afmt) { 1214 kfree(enc1); 1215 kfree(vpg); 1216 kfree(afmt); 1217 return NULL; 1218 } 1219 1220 #undef REG_STRUCT 1221 #define REG_STRUCT stream_enc_regs 1222 stream_enc_regs_init(0), 1223 stream_enc_regs_init(1), 1224 stream_enc_regs_init(2), 1225 stream_enc_regs_init(3), 1226 stream_enc_regs_init(4); 1227 1228 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1229 eng_id, vpg, afmt, 1230 &stream_enc_regs[eng_id], 1231 &se_shift, &se_mask); 1232 1233 return &enc1->base; 1234 } 1235 1236 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1237 enum engine_id eng_id, 1238 struct dc_context *ctx) 1239 { 1240 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1241 struct vpg *vpg; 1242 struct apg *apg; 1243 uint32_t hpo_dp_inst; 1244 uint32_t vpg_inst; 1245 uint32_t apg_inst; 1246 1247 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1248 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1249 1250 /* Mapping of VPG register blocks to HPO DP block instance: 1251 * VPG[6] -> HPO_DP[0] 1252 * VPG[7] -> HPO_DP[1] 1253 * VPG[8] -> HPO_DP[2] 1254 * VPG[9] -> HPO_DP[3] 1255 */ 1256 vpg_inst = hpo_dp_inst + 6; 1257 1258 /* Mapping of APG register blocks to HPO DP block instance: 1259 * APG[0] -> HPO_DP[0] 1260 * APG[1] -> HPO_DP[1] 1261 * APG[2] -> HPO_DP[2] 1262 * APG[3] -> HPO_DP[3] 1263 */ 1264 apg_inst = hpo_dp_inst; 1265 1266 /* allocate HPO stream encoder and create VPG sub-block */ 1267 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1268 vpg = dcn32_vpg_create(ctx, vpg_inst); 1269 apg = dcn31_apg_create(ctx, apg_inst); 1270 1271 if (!hpo_dp_enc31 || !vpg || !apg) { 1272 kfree(hpo_dp_enc31); 1273 kfree(vpg); 1274 kfree(apg); 1275 return NULL; 1276 } 1277 1278 #undef REG_STRUCT 1279 #define REG_STRUCT hpo_dp_stream_enc_regs 1280 hpo_dp_stream_encoder_reg_init(0), 1281 hpo_dp_stream_encoder_reg_init(1), 1282 hpo_dp_stream_encoder_reg_init(2), 1283 hpo_dp_stream_encoder_reg_init(3); 1284 1285 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1286 hpo_dp_inst, eng_id, vpg, apg, 1287 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1288 &hpo_dp_se_shift, &hpo_dp_se_mask); 1289 1290 return &hpo_dp_enc31->base; 1291 } 1292 1293 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1294 uint8_t inst, 1295 struct dc_context *ctx) 1296 { 1297 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1298 1299 /* allocate HPO link encoder */ 1300 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1301 1302 #undef REG_STRUCT 1303 #define REG_STRUCT hpo_dp_link_enc_regs 1304 hpo_dp_link_encoder_reg_init(0), 1305 hpo_dp_link_encoder_reg_init(1); 1306 1307 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1308 &hpo_dp_link_enc_regs[inst], 1309 &hpo_dp_le_shift, &hpo_dp_le_mask); 1310 1311 return &hpo_dp_enc31->base; 1312 } 1313 1314 static struct dce_hwseq *dcn32_hwseq_create( 1315 struct dc_context *ctx) 1316 { 1317 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1318 1319 #undef REG_STRUCT 1320 #define REG_STRUCT hwseq_reg 1321 hwseq_reg_init(); 1322 1323 if (hws) { 1324 hws->ctx = ctx; 1325 hws->regs = &hwseq_reg; 1326 hws->shifts = &hwseq_shift; 1327 hws->masks = &hwseq_mask; 1328 } 1329 return hws; 1330 } 1331 static const struct resource_create_funcs res_create_funcs = { 1332 .read_dce_straps = read_dce_straps, 1333 .create_audio = dcn32_create_audio, 1334 .create_stream_encoder = dcn32_stream_encoder_create, 1335 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1336 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1337 .create_hwseq = dcn32_hwseq_create, 1338 }; 1339 1340 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1341 { 1342 unsigned int i; 1343 1344 for (i = 0; i < pool->base.stream_enc_count; i++) { 1345 if (pool->base.stream_enc[i] != NULL) { 1346 if (pool->base.stream_enc[i]->vpg != NULL) { 1347 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1348 pool->base.stream_enc[i]->vpg = NULL; 1349 } 1350 if (pool->base.stream_enc[i]->afmt != NULL) { 1351 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1352 pool->base.stream_enc[i]->afmt = NULL; 1353 } 1354 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1355 pool->base.stream_enc[i] = NULL; 1356 } 1357 } 1358 1359 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1360 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1361 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1362 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1363 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1364 } 1365 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1366 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1367 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1368 } 1369 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1370 pool->base.hpo_dp_stream_enc[i] = NULL; 1371 } 1372 } 1373 1374 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1375 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1376 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1377 pool->base.hpo_dp_link_enc[i] = NULL; 1378 } 1379 } 1380 1381 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1382 if (pool->base.dscs[i] != NULL) 1383 dcn20_dsc_destroy(&pool->base.dscs[i]); 1384 } 1385 1386 if (pool->base.mpc != NULL) { 1387 kfree(TO_DCN20_MPC(pool->base.mpc)); 1388 pool->base.mpc = NULL; 1389 } 1390 if (pool->base.hubbub != NULL) { 1391 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1392 pool->base.hubbub = NULL; 1393 } 1394 for (i = 0; i < pool->base.pipe_count; i++) { 1395 if (pool->base.dpps[i] != NULL) 1396 dcn32_dpp_destroy(&pool->base.dpps[i]); 1397 1398 if (pool->base.ipps[i] != NULL) 1399 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1400 1401 if (pool->base.hubps[i] != NULL) { 1402 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1403 pool->base.hubps[i] = NULL; 1404 } 1405 1406 if (pool->base.irqs != NULL) { 1407 dal_irq_service_destroy(&pool->base.irqs); 1408 } 1409 } 1410 1411 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1412 if (pool->base.engines[i] != NULL) 1413 dce110_engine_destroy(&pool->base.engines[i]); 1414 if (pool->base.hw_i2cs[i] != NULL) { 1415 kfree(pool->base.hw_i2cs[i]); 1416 pool->base.hw_i2cs[i] = NULL; 1417 } 1418 if (pool->base.sw_i2cs[i] != NULL) { 1419 kfree(pool->base.sw_i2cs[i]); 1420 pool->base.sw_i2cs[i] = NULL; 1421 } 1422 } 1423 1424 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1425 if (pool->base.opps[i] != NULL) 1426 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1427 } 1428 1429 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1430 if (pool->base.timing_generators[i] != NULL) { 1431 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1432 pool->base.timing_generators[i] = NULL; 1433 } 1434 } 1435 1436 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1437 if (pool->base.dwbc[i] != NULL) { 1438 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1439 pool->base.dwbc[i] = NULL; 1440 } 1441 if (pool->base.mcif_wb[i] != NULL) { 1442 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1443 pool->base.mcif_wb[i] = NULL; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.audio_count; i++) { 1448 if (pool->base.audios[i]) 1449 dce_aud_destroy(&pool->base.audios[i]); 1450 } 1451 1452 for (i = 0; i < pool->base.clk_src_count; i++) { 1453 if (pool->base.clock_sources[i] != NULL) { 1454 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1455 pool->base.clock_sources[i] = NULL; 1456 } 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1460 if (pool->base.mpc_lut[i] != NULL) { 1461 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1462 pool->base.mpc_lut[i] = NULL; 1463 } 1464 if (pool->base.mpc_shaper[i] != NULL) { 1465 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1466 pool->base.mpc_shaper[i] = NULL; 1467 } 1468 } 1469 1470 if (pool->base.dp_clock_source != NULL) { 1471 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1472 pool->base.dp_clock_source = NULL; 1473 } 1474 1475 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1476 if (pool->base.multiple_abms[i] != NULL) 1477 dce_abm_destroy(&pool->base.multiple_abms[i]); 1478 } 1479 1480 if (pool->base.psr != NULL) 1481 dmub_psr_destroy(&pool->base.psr); 1482 1483 if (pool->base.dccg != NULL) 1484 dcn_dccg_destroy(&pool->base.dccg); 1485 1486 if (pool->base.oem_device != NULL) { 1487 struct dc *dc = pool->base.oem_device->ctx->dc; 1488 1489 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1490 } 1491 } 1492 1493 1494 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1495 { 1496 int i; 1497 uint32_t dwb_count = pool->res_cap->num_dwb; 1498 1499 for (i = 0; i < dwb_count; i++) { 1500 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1501 GFP_KERNEL); 1502 1503 if (!dwbc30) { 1504 dm_error("DC: failed to create dwbc30!\n"); 1505 return false; 1506 } 1507 1508 #undef REG_STRUCT 1509 #define REG_STRUCT dwbc30_regs 1510 dwbc_regs_dcn3_init(0); 1511 1512 dcn30_dwbc_construct(dwbc30, ctx, 1513 &dwbc30_regs[i], 1514 &dwbc30_shift, 1515 &dwbc30_mask, 1516 i); 1517 1518 pool->dwbc[i] = &dwbc30->base; 1519 } 1520 return true; 1521 } 1522 1523 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1524 { 1525 int i; 1526 uint32_t dwb_count = pool->res_cap->num_dwb; 1527 1528 for (i = 0; i < dwb_count; i++) { 1529 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1530 GFP_KERNEL); 1531 1532 if (!mcif_wb30) { 1533 dm_error("DC: failed to create mcif_wb30!\n"); 1534 return false; 1535 } 1536 1537 #undef REG_STRUCT 1538 #define REG_STRUCT mcif_wb30_regs 1539 mcif_wb_regs_dcn3_init(0); 1540 1541 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1542 &mcif_wb30_regs[i], 1543 &mcif_wb30_shift, 1544 &mcif_wb30_mask, 1545 i); 1546 1547 pool->mcif_wb[i] = &mcif_wb30->base; 1548 } 1549 return true; 1550 } 1551 1552 static struct display_stream_compressor *dcn32_dsc_create( 1553 struct dc_context *ctx, uint32_t inst) 1554 { 1555 struct dcn20_dsc *dsc = 1556 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1557 1558 if (!dsc) { 1559 BREAK_TO_DEBUGGER(); 1560 return NULL; 1561 } 1562 1563 #undef REG_STRUCT 1564 #define REG_STRUCT dsc_regs 1565 dsc_regsDCN20_init(0), 1566 dsc_regsDCN20_init(1), 1567 dsc_regsDCN20_init(2), 1568 dsc_regsDCN20_init(3); 1569 1570 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1571 1572 dsc->max_image_width = 6016; 1573 1574 return &dsc->base; 1575 } 1576 1577 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1578 { 1579 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1580 1581 dcn32_resource_destruct(dcn32_pool); 1582 kfree(dcn32_pool); 1583 *pool = NULL; 1584 } 1585 1586 bool dcn32_acquire_post_bldn_3dlut( 1587 struct resource_context *res_ctx, 1588 const struct resource_pool *pool, 1589 int mpcc_id, 1590 struct dc_3dlut **lut, 1591 struct dc_transfer_func **shaper) 1592 { 1593 bool ret = false; 1594 1595 ASSERT(*lut == NULL && *shaper == NULL); 1596 *lut = NULL; 1597 *shaper = NULL; 1598 1599 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1600 *lut = pool->mpc_lut[mpcc_id]; 1601 *shaper = pool->mpc_shaper[mpcc_id]; 1602 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1603 ret = true; 1604 } 1605 return ret; 1606 } 1607 1608 bool dcn32_release_post_bldn_3dlut( 1609 struct resource_context *res_ctx, 1610 const struct resource_pool *pool, 1611 struct dc_3dlut **lut, 1612 struct dc_transfer_func **shaper) 1613 { 1614 int i; 1615 bool ret = false; 1616 1617 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1618 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1619 res_ctx->is_mpc_3dlut_acquired[i] = false; 1620 pool->mpc_lut[i]->state.raw = 0; 1621 *lut = NULL; 1622 *shaper = NULL; 1623 ret = true; 1624 break; 1625 } 1626 } 1627 return ret; 1628 } 1629 1630 static void dcn32_enable_phantom_plane(struct dc *dc, 1631 struct dc_state *context, 1632 struct dc_stream_state *phantom_stream, 1633 unsigned int dc_pipe_idx) 1634 { 1635 struct dc_plane_state *phantom_plane = NULL; 1636 struct dc_plane_state *prev_phantom_plane = NULL; 1637 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1638 1639 while (curr_pipe) { 1640 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1641 phantom_plane = prev_phantom_plane; 1642 else 1643 phantom_plane = dc_create_plane_state(dc); 1644 1645 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1646 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1647 sizeof(phantom_plane->scaling_quality)); 1648 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1649 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1650 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1651 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1652 sizeof(phantom_plane->plane_size)); 1653 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1654 sizeof(phantom_plane->tiling_info)); 1655 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1656 phantom_plane->format = curr_pipe->plane_state->format; 1657 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1658 phantom_plane->visible = curr_pipe->plane_state->visible; 1659 1660 /* Shadow pipe has small viewport. */ 1661 phantom_plane->clip_rect.y = 0; 1662 phantom_plane->clip_rect.height = phantom_stream->src.height; 1663 1664 phantom_plane->is_phantom = true; 1665 1666 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1667 1668 curr_pipe = curr_pipe->bottom_pipe; 1669 prev_phantom_plane = phantom_plane; 1670 } 1671 } 1672 1673 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1674 struct dc_state *context, 1675 display_e2e_pipe_params_st *pipes, 1676 unsigned int pipe_cnt, 1677 unsigned int dc_pipe_idx) 1678 { 1679 struct dc_stream_state *phantom_stream = NULL; 1680 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1681 1682 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1683 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1684 phantom_stream->dpms_off = true; 1685 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1686 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1687 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1688 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1689 1690 /* stream has limited viewport and small timing */ 1691 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1692 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1693 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1694 DC_FP_START(); 1695 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1696 DC_FP_END(); 1697 1698 dc_add_stream_to_ctx(dc, context, phantom_stream); 1699 return phantom_stream; 1700 } 1701 1702 void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) 1703 { 1704 int i; 1705 struct dc_plane_state *phantom_plane = NULL; 1706 struct dc_stream_state *phantom_stream = NULL; 1707 1708 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1709 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1710 1711 if (!pipe->top_pipe && !pipe->prev_odm_pipe && 1712 pipe->plane_state && pipe->stream && 1713 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1714 phantom_plane = pipe->plane_state; 1715 phantom_stream = pipe->stream; 1716 1717 dc_plane_state_retain(phantom_plane); 1718 dc_stream_retain(phantom_stream); 1719 } 1720 } 1721 } 1722 1723 // return true if removed piped from ctx, false otherwise 1724 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update) 1725 { 1726 int i; 1727 bool removed_pipe = false; 1728 struct dc_plane_state *phantom_plane = NULL; 1729 struct dc_stream_state *phantom_stream = NULL; 1730 1731 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1732 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1733 // build scaling params for phantom pipes 1734 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1735 phantom_plane = pipe->plane_state; 1736 phantom_stream = pipe->stream; 1737 1738 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1739 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1740 1741 /* Ref count is incremented on allocation and also when added to the context. 1742 * Therefore we must call release for the the phantom plane and stream once 1743 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1744 */ 1745 dc_plane_state_release(phantom_plane); 1746 dc_stream_release(phantom_stream); 1747 1748 removed_pipe = true; 1749 } 1750 1751 /* For non-full updates, a shallow copy of the current state 1752 * is created. In this case we don't want to erase the current 1753 * state (there can be 2 HIRQL threads, one in flip, and one in 1754 * checkMPO) that can cause a race condition. 1755 * 1756 * This is just a workaround, needs a proper fix. 1757 */ 1758 if (!fast_update) { 1759 // Clear all phantom stream info 1760 if (pipe->stream) { 1761 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1762 pipe->stream->mall_stream_config.paired_stream = NULL; 1763 } 1764 1765 if (pipe->plane_state) { 1766 pipe->plane_state->is_phantom = false; 1767 } 1768 } 1769 } 1770 return removed_pipe; 1771 } 1772 1773 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1774 * require a phantom pipe / stream 1775 */ 1776 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1777 display_e2e_pipe_params_st *pipes, 1778 unsigned int pipe_cnt, 1779 unsigned int index) 1780 { 1781 struct dc_stream_state *phantom_stream = NULL; 1782 unsigned int i; 1783 1784 // The index of the DC pipe passed into this function is guarenteed to 1785 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1786 // already have phantom pipe assigned, etc.) by previous checks. 1787 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1788 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1789 1790 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1791 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1792 1793 // Build scaling params for phantom pipes which were newly added. 1794 // We determine which phantom pipes were added by comparing with 1795 // the phantom stream. 1796 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1797 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1798 pipe->stream->use_dynamic_meta = false; 1799 pipe->plane_state->flip_immediate = false; 1800 if (!resource_build_scaling_params(pipe)) { 1801 // Log / remove phantom pipes since failed to build scaling params 1802 } 1803 } 1804 } 1805 } 1806 1807 bool dcn32_validate_bandwidth(struct dc *dc, 1808 struct dc_state *context, 1809 bool fast_validate) 1810 { 1811 bool out = false; 1812 1813 BW_VAL_TRACE_SETUP(); 1814 1815 int vlevel = 0; 1816 int pipe_cnt = 0; 1817 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1818 struct mall_temp_config mall_temp_config; 1819 1820 /* To handle Freesync properly, setting FreeSync DML parameters 1821 * to its default state for the first stage of validation 1822 */ 1823 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1824 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1825 1826 DC_LOGGER_INIT(dc->ctx->logger); 1827 1828 /* For fast validation, there are situations where a shallow copy of 1829 * of the dc->current_state is created for the validation. In this case 1830 * we want to save and restore the mall config because we always 1831 * teardown subvp at the beginning of validation (and don't attempt 1832 * to add it back if it's fast validation). If we don't restore the 1833 * subvp config in cases of fast validation + shallow copy of the 1834 * dc->current_state, the dc->current_state will have a partially 1835 * removed subvp state when we did not intend to remove it. 1836 */ 1837 if (fast_validate) { 1838 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1839 dcn32_save_mall_state(dc, context, &mall_temp_config); 1840 } 1841 1842 BW_VAL_TRACE_COUNT(); 1843 1844 DC_FP_START(); 1845 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1846 DC_FP_END(); 1847 1848 if (fast_validate) 1849 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1850 1851 if (pipe_cnt == 0) 1852 goto validate_out; 1853 1854 if (!out) 1855 goto validate_fail; 1856 1857 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1858 1859 if (fast_validate) { 1860 BW_VAL_TRACE_SKIP(fast); 1861 goto validate_out; 1862 } 1863 1864 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1865 1866 dcn32_override_min_req_memclk(dc, context); 1867 1868 BW_VAL_TRACE_END_WATERMARKS(); 1869 1870 goto validate_out; 1871 1872 validate_fail: 1873 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1874 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1875 1876 BW_VAL_TRACE_SKIP(fail); 1877 out = false; 1878 1879 validate_out: 1880 kfree(pipes); 1881 1882 BW_VAL_TRACE_FINISH(); 1883 1884 return out; 1885 } 1886 1887 int dcn32_populate_dml_pipes_from_context( 1888 struct dc *dc, struct dc_state *context, 1889 display_e2e_pipe_params_st *pipes, 1890 bool fast_validate) 1891 { 1892 int i, pipe_cnt; 1893 struct resource_context *res_ctx = &context->res_ctx; 1894 struct pipe_ctx *pipe; 1895 bool subvp_in_use = false; 1896 struct dc_crtc_timing *timing; 1897 bool vsr_odm_support = false; 1898 1899 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1900 1901 /* Determine whether we will apply ODM 2to1 policy: 1902 * Applies to single display and where the number of planes is less than 3. 1903 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1904 * 1905 * Apply pipe split policy first so we can predict the pipe split correctly 1906 * (dcn32_predict_pipe_split). 1907 */ 1908 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1909 if (!res_ctx->pipe_ctx[i].stream) 1910 continue; 1911 pipe = &res_ctx->pipe_ctx[i]; 1912 timing = &pipe->stream->timing; 1913 1914 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1915 vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 && 1916 res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width); 1917 if (context->stream_count == 1 && 1918 context->stream_status[0].plane_count == 1 && 1919 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1920 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1921 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1922 dc->debug.enable_single_display_2to1_odm_policy && 1923 !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr 1924 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1925 } 1926 pipe_cnt++; 1927 } 1928 1929 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1930 1931 if (!res_ctx->pipe_ctx[i].stream) 1932 continue; 1933 pipe = &res_ctx->pipe_ctx[i]; 1934 timing = &pipe->stream->timing; 1935 1936 pipes[pipe_cnt].pipe.src.gpuvm = true; 1937 DC_FP_START(); 1938 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1939 DC_FP_END(); 1940 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1941 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1942 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1943 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1944 1945 /* Only populate DML input with subvp info for full updates. 1946 * This is just a workaround -- needs a proper fix. 1947 */ 1948 if (!fast_validate) { 1949 switch (pipe->stream->mall_stream_config.type) { 1950 case SUBVP_MAIN: 1951 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1952 subvp_in_use = true; 1953 break; 1954 case SUBVP_PHANTOM: 1955 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1956 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1957 // Disallow unbounded req for SubVP according to DCHUB programming guide 1958 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1959 break; 1960 case SUBVP_NONE: 1961 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1962 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1963 break; 1964 default: 1965 break; 1966 } 1967 } 1968 1969 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1970 if (pipes[pipe_cnt].dout.dsc_enable) { 1971 switch (timing->display_color_depth) { 1972 case COLOR_DEPTH_888: 1973 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1974 break; 1975 case COLOR_DEPTH_101010: 1976 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1977 break; 1978 case COLOR_DEPTH_121212: 1979 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1980 break; 1981 default: 1982 ASSERT(0); 1983 break; 1984 } 1985 } 1986 1987 DC_FP_START(); 1988 dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 1989 DC_FP_END(); 1990 1991 pipe_cnt++; 1992 } 1993 1994 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 1995 * the DET available for each pipe). Use the DET override input to maintain our driver 1996 * policy. 1997 */ 1998 dcn32_set_det_allocations(dc, context, pipes); 1999 2000 // In general cases we want to keep the dram clock change requirement 2001 // (prefer configs that support MCLK switch). Only override to false 2002 // for SubVP 2003 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) 2004 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2005 else 2006 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2007 2008 return pipe_cnt; 2009 } 2010 2011 static struct dc_cap_funcs cap_funcs = { 2012 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2013 }; 2014 2015 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2016 display_e2e_pipe_params_st *pipes, 2017 int pipe_cnt, 2018 int vlevel) 2019 { 2020 DC_FP_START(); 2021 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2022 DC_FP_END(); 2023 } 2024 2025 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2026 { 2027 DC_FP_START(); 2028 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2029 DC_FP_END(); 2030 } 2031 2032 static struct resource_funcs dcn32_res_pool_funcs = { 2033 .destroy = dcn32_destroy_resource_pool, 2034 .link_enc_create = dcn32_link_encoder_create, 2035 .link_enc_create_minimal = NULL, 2036 .panel_cntl_create = dcn32_panel_cntl_create, 2037 .validate_bandwidth = dcn32_validate_bandwidth, 2038 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2039 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2040 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2041 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2042 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2043 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2044 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2045 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2046 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2047 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2048 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2049 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2050 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2051 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2052 .add_phantom_pipes = dcn32_add_phantom_pipes, 2053 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2054 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 2055 .save_mall_state = dcn32_save_mall_state, 2056 .restore_mall_state = dcn32_restore_mall_state, 2057 }; 2058 2059 static uint32_t read_pipe_fuses(struct dc_context *ctx) 2060 { 2061 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2062 /* DCN32 support max 4 pipes */ 2063 value = value & 0xf; 2064 return value; 2065 } 2066 2067 2068 static bool dcn32_resource_construct( 2069 uint8_t num_virtual_links, 2070 struct dc *dc, 2071 struct dcn32_resource_pool *pool) 2072 { 2073 int i, j; 2074 struct dc_context *ctx = dc->ctx; 2075 struct irq_service_init_data init_data; 2076 struct ddc_service_init_data ddc_init_data = {0}; 2077 uint32_t pipe_fuses = 0; 2078 uint32_t num_pipes = 4; 2079 2080 #undef REG_STRUCT 2081 #define REG_STRUCT bios_regs 2082 bios_regs_init(); 2083 2084 #undef REG_STRUCT 2085 #define REG_STRUCT clk_src_regs 2086 clk_src_regs_init(0, A), 2087 clk_src_regs_init(1, B), 2088 clk_src_regs_init(2, C), 2089 clk_src_regs_init(3, D), 2090 clk_src_regs_init(4, E); 2091 2092 #undef REG_STRUCT 2093 #define REG_STRUCT abm_regs 2094 abm_regs_init(0), 2095 abm_regs_init(1), 2096 abm_regs_init(2), 2097 abm_regs_init(3); 2098 2099 #undef REG_STRUCT 2100 #define REG_STRUCT dccg_regs 2101 dccg_regs_init(); 2102 2103 DC_FP_START(); 2104 2105 ctx->dc_bios->regs = &bios_regs; 2106 2107 pool->base.res_cap = &res_cap_dcn32; 2108 /* max number of pipes for ASIC before checking for pipe fuses */ 2109 num_pipes = pool->base.res_cap->num_timing_generator; 2110 pipe_fuses = read_pipe_fuses(ctx); 2111 2112 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2113 if (pipe_fuses & 1 << i) 2114 num_pipes--; 2115 2116 if (pipe_fuses & 1) 2117 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2118 2119 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2120 ASSERT(0); //Entire DCN is harvested! 2121 2122 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2123 * value will be changed, update max_num_dpp and max_num_otg for dml. 2124 */ 2125 dcn3_2_ip.max_num_dpp = num_pipes; 2126 dcn3_2_ip.max_num_otg = num_pipes; 2127 2128 pool->base.funcs = &dcn32_res_pool_funcs; 2129 2130 /************************************************* 2131 * Resource + asic cap harcoding * 2132 *************************************************/ 2133 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2134 pool->base.timing_generator_count = num_pipes; 2135 pool->base.pipe_count = num_pipes; 2136 pool->base.mpcc_count = num_pipes; 2137 dc->caps.max_downscale_ratio = 600; 2138 dc->caps.i2c_speed_in_khz = 100; 2139 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2140 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2141 dc->caps.max_cursor_size = 64; 2142 dc->caps.min_horizontal_blanking_period = 80; 2143 dc->caps.dmdata_alloc_size = 2048; 2144 dc->caps.mall_size_per_mem_channel = 4; 2145 dc->caps.mall_size_total = 0; 2146 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2147 2148 dc->caps.cache_line_size = 64; 2149 dc->caps.cache_num_ways = 16; 2150 2151 /* Calculate the available MALL space */ 2152 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2153 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2154 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2155 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2156 2157 dc->caps.subvp_fw_processing_delay_us = 15; 2158 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2159 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2160 dc->caps.subvp_swath_height_margin_lines = 16; 2161 dc->caps.subvp_pstate_allow_width_us = 20; 2162 dc->caps.subvp_vertical_int_margin_us = 30; 2163 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2164 2165 dc->caps.max_slave_planes = 2; 2166 dc->caps.max_slave_yuv_planes = 2; 2167 dc->caps.max_slave_rgb_planes = 2; 2168 dc->caps.post_blend_color_processing = true; 2169 dc->caps.force_dp_tps4_for_cp2520 = true; 2170 if (dc->config.forceHBR2CP2520) 2171 dc->caps.force_dp_tps4_for_cp2520 = false; 2172 dc->caps.dp_hpo = true; 2173 dc->caps.dp_hdmi21_pcon_support = true; 2174 dc->caps.edp_dsc_support = true; 2175 dc->caps.extended_aux_timeout_support = true; 2176 dc->caps.dmcub_support = true; 2177 dc->caps.seamless_odm = true; 2178 dc->caps.max_v_total = (1 << 15) - 1; 2179 2180 /* Color pipeline capabilities */ 2181 dc->caps.color.dpp.dcn_arch = 1; 2182 dc->caps.color.dpp.input_lut_shared = 0; 2183 dc->caps.color.dpp.icsc = 1; 2184 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2185 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2186 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2187 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2188 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2189 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2190 dc->caps.color.dpp.post_csc = 1; 2191 dc->caps.color.dpp.gamma_corr = 1; 2192 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2193 2194 dc->caps.color.dpp.hw_3d_lut = 1; 2195 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2196 // no OGAM ROM on DCN2 and later ASICs 2197 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2198 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2199 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2200 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2201 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2202 dc->caps.color.dpp.ocsc = 0; 2203 2204 dc->caps.color.mpc.gamut_remap = 1; 2205 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2206 dc->caps.color.mpc.ogam_ram = 1; 2207 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2208 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2209 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2210 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2211 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2212 dc->caps.color.mpc.ocsc = 1; 2213 2214 /* Use pipe context based otg sync logic */ 2215 dc->config.use_pipe_ctx_sync_logic = true; 2216 2217 /* read VBIOS LTTPR caps */ 2218 { 2219 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2220 enum bp_result bp_query_result; 2221 uint8_t is_vbios_lttpr_enable = 0; 2222 2223 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2224 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2225 } 2226 2227 /* interop bit is implicit */ 2228 { 2229 dc->caps.vbios_lttpr_aware = true; 2230 } 2231 } 2232 2233 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2234 dc->debug = debug_defaults_drv; 2235 2236 // Init the vm_helper 2237 if (dc->vm_helper) 2238 vm_helper_init(dc->vm_helper, 16); 2239 2240 /************************************************* 2241 * Create resources * 2242 *************************************************/ 2243 2244 /* Clock Sources for Pixel Clock*/ 2245 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2246 dcn32_clock_source_create(ctx, ctx->dc_bios, 2247 CLOCK_SOURCE_COMBO_PHY_PLL0, 2248 &clk_src_regs[0], false); 2249 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2250 dcn32_clock_source_create(ctx, ctx->dc_bios, 2251 CLOCK_SOURCE_COMBO_PHY_PLL1, 2252 &clk_src_regs[1], false); 2253 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2254 dcn32_clock_source_create(ctx, ctx->dc_bios, 2255 CLOCK_SOURCE_COMBO_PHY_PLL2, 2256 &clk_src_regs[2], false); 2257 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2258 dcn32_clock_source_create(ctx, ctx->dc_bios, 2259 CLOCK_SOURCE_COMBO_PHY_PLL3, 2260 &clk_src_regs[3], false); 2261 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2262 dcn32_clock_source_create(ctx, ctx->dc_bios, 2263 CLOCK_SOURCE_COMBO_PHY_PLL4, 2264 &clk_src_regs[4], false); 2265 2266 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2267 2268 /* todo: not reuse phy_pll registers */ 2269 pool->base.dp_clock_source = 2270 dcn32_clock_source_create(ctx, ctx->dc_bios, 2271 CLOCK_SOURCE_ID_DP_DTO, 2272 &clk_src_regs[0], true); 2273 2274 for (i = 0; i < pool->base.clk_src_count; i++) { 2275 if (pool->base.clock_sources[i] == NULL) { 2276 dm_error("DC: failed to create clock sources!\n"); 2277 BREAK_TO_DEBUGGER(); 2278 goto create_fail; 2279 } 2280 } 2281 2282 /* DCCG */ 2283 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2284 if (pool->base.dccg == NULL) { 2285 dm_error("DC: failed to create dccg!\n"); 2286 BREAK_TO_DEBUGGER(); 2287 goto create_fail; 2288 } 2289 2290 /* DML */ 2291 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2292 2293 /* IRQ Service */ 2294 init_data.ctx = dc->ctx; 2295 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2296 if (!pool->base.irqs) 2297 goto create_fail; 2298 2299 /* HUBBUB */ 2300 pool->base.hubbub = dcn32_hubbub_create(ctx); 2301 if (pool->base.hubbub == NULL) { 2302 BREAK_TO_DEBUGGER(); 2303 dm_error("DC: failed to create hubbub!\n"); 2304 goto create_fail; 2305 } 2306 2307 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2308 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2309 2310 /* if pipe is disabled, skip instance of HW pipe, 2311 * i.e, skip ASIC register instance 2312 */ 2313 if (pipe_fuses & 1 << i) 2314 continue; 2315 2316 /* HUBPs */ 2317 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2318 if (pool->base.hubps[j] == NULL) { 2319 BREAK_TO_DEBUGGER(); 2320 dm_error( 2321 "DC: failed to create hubps!\n"); 2322 goto create_fail; 2323 } 2324 2325 /* DPPs */ 2326 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2327 if (pool->base.dpps[j] == NULL) { 2328 BREAK_TO_DEBUGGER(); 2329 dm_error( 2330 "DC: failed to create dpps!\n"); 2331 goto create_fail; 2332 } 2333 2334 /* OPPs */ 2335 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2336 if (pool->base.opps[j] == NULL) { 2337 BREAK_TO_DEBUGGER(); 2338 dm_error( 2339 "DC: failed to create output pixel processor!\n"); 2340 goto create_fail; 2341 } 2342 2343 /* TGs */ 2344 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2345 ctx, i); 2346 if (pool->base.timing_generators[j] == NULL) { 2347 BREAK_TO_DEBUGGER(); 2348 dm_error("DC: failed to create tg!\n"); 2349 goto create_fail; 2350 } 2351 2352 /* ABMs */ 2353 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2354 &abm_regs[i], 2355 &abm_shift, 2356 &abm_mask); 2357 if (pool->base.multiple_abms[j] == NULL) { 2358 dm_error("DC: failed to create abm for pipe %d!\n", i); 2359 BREAK_TO_DEBUGGER(); 2360 goto create_fail; 2361 } 2362 2363 /* index for resource pool arrays for next valid pipe */ 2364 j++; 2365 } 2366 2367 /* PSR */ 2368 pool->base.psr = dmub_psr_create(ctx); 2369 if (pool->base.psr == NULL) { 2370 dm_error("DC: failed to create psr obj!\n"); 2371 BREAK_TO_DEBUGGER(); 2372 goto create_fail; 2373 } 2374 2375 /* MPCCs */ 2376 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2377 if (pool->base.mpc == NULL) { 2378 BREAK_TO_DEBUGGER(); 2379 dm_error("DC: failed to create mpc!\n"); 2380 goto create_fail; 2381 } 2382 2383 /* DSCs */ 2384 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2385 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2386 if (pool->base.dscs[i] == NULL) { 2387 BREAK_TO_DEBUGGER(); 2388 dm_error("DC: failed to create display stream compressor %d!\n", i); 2389 goto create_fail; 2390 } 2391 } 2392 2393 /* DWB */ 2394 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2395 BREAK_TO_DEBUGGER(); 2396 dm_error("DC: failed to create dwbc!\n"); 2397 goto create_fail; 2398 } 2399 2400 /* MMHUBBUB */ 2401 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2402 BREAK_TO_DEBUGGER(); 2403 dm_error("DC: failed to create mcif_wb!\n"); 2404 goto create_fail; 2405 } 2406 2407 /* AUX and I2C */ 2408 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2409 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2410 if (pool->base.engines[i] == NULL) { 2411 BREAK_TO_DEBUGGER(); 2412 dm_error( 2413 "DC:failed to create aux engine!!\n"); 2414 goto create_fail; 2415 } 2416 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2417 if (pool->base.hw_i2cs[i] == NULL) { 2418 BREAK_TO_DEBUGGER(); 2419 dm_error( 2420 "DC:failed to create hw i2c!!\n"); 2421 goto create_fail; 2422 } 2423 pool->base.sw_i2cs[i] = NULL; 2424 } 2425 2426 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2427 if (!resource_construct(num_virtual_links, dc, &pool->base, 2428 &res_create_funcs)) 2429 goto create_fail; 2430 2431 /* HW Sequencer init functions and Plane caps */ 2432 dcn32_hw_sequencer_init_functions(dc); 2433 2434 dc->caps.max_planes = pool->base.pipe_count; 2435 2436 for (i = 0; i < dc->caps.max_planes; ++i) 2437 dc->caps.planes[i] = plane_cap; 2438 2439 dc->cap_funcs = cap_funcs; 2440 2441 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2442 ddc_init_data.ctx = dc->ctx; 2443 ddc_init_data.link = NULL; 2444 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2445 ddc_init_data.id.enum_id = 0; 2446 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2447 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2448 } else { 2449 pool->base.oem_device = NULL; 2450 } 2451 2452 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2453 dc->config.sdpif_request_limit_words_per_umc = 16; 2454 2455 DC_FP_END(); 2456 2457 return true; 2458 2459 create_fail: 2460 2461 DC_FP_END(); 2462 2463 dcn32_resource_destruct(pool); 2464 2465 return false; 2466 } 2467 2468 struct resource_pool *dcn32_create_resource_pool( 2469 const struct dc_init_data *init_data, 2470 struct dc *dc) 2471 { 2472 struct dcn32_resource_pool *pool = 2473 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2474 2475 if (!pool) 2476 return NULL; 2477 2478 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2479 return &pool->base; 2480 2481 BREAK_TO_DEBUGGER(); 2482 kfree(pool); 2483 return NULL; 2484 } 2485 2486 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2487 struct resource_context *res_ctx, 2488 const struct resource_pool *pool, 2489 const struct pipe_ctx *primary_pipe) 2490 { 2491 int i; 2492 struct pipe_ctx *secondary_pipe = NULL; 2493 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2494 int primary_index, preferred_pipe_idx; 2495 struct pipe_ctx *old_primary_pipe = NULL; 2496 2497 /* 2498 * Modified from find_idle_secondary_pipe 2499 * With windowed MPO and ODM, we want to avoid the case where we want a 2500 * free pipe for the left side but the free pipe is being used on the 2501 * right side. 2502 * Add check on current_state if the primary_pipe is the left side, 2503 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2504 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2505 * - If so, then don't use this pipe 2506 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2507 * - in this case, the primary pipe has already gotten a free pipe for the 2508 * MPO window in the left 2509 * - when it tries to get a free pipe for the MPO window on the right, 2510 * it will see that it is already assigned to the right side 2511 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2512 * free pipe, since it will be for the right side. So add an 2513 * additional condition, that skipping the free pipe on the right only 2514 * applies if the primary pipe has no bottom pipe currently assigned 2515 */ 2516 if (primary_pipe) { 2517 primary_index = primary_pipe->pipe_idx; 2518 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2519 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2520 && (!primary_pipe->bottom_pipe)) 2521 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2522 2523 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2524 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2525 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2526 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2527 secondary_pipe->pipe_idx = preferred_pipe_idx; 2528 } 2529 } 2530 2531 /* 2532 * search backwards for the second pipe to keep pipe 2533 * assignment more consistent 2534 */ 2535 if (!secondary_pipe) 2536 for (i = pool->pipe_count - 1; i >= 0; i--) { 2537 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2538 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2539 secondary_pipe = &res_ctx->pipe_ctx[i]; 2540 secondary_pipe->pipe_idx = i; 2541 break; 2542 } 2543 } 2544 2545 return secondary_pipe; 2546 } 2547 2548 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2549 struct dc_state *state, 2550 const struct resource_pool *pool, 2551 struct dc_stream_state *stream, 2552 struct pipe_ctx *head_pipe) 2553 { 2554 struct resource_context *res_ctx = &state->res_ctx; 2555 struct pipe_ctx *idle_pipe, *pipe; 2556 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2557 int head_index; 2558 2559 if (!head_pipe) 2560 ASSERT(0); 2561 2562 /* 2563 * Modified from dcn20_acquire_idle_pipe_for_layer 2564 * Check if head_pipe in old_context already has bottom_pipe allocated. 2565 * - If so, check if that pipe is available in the current context. 2566 * -- If so, reuse pipe from old_context 2567 */ 2568 head_index = head_pipe->pipe_idx; 2569 pipe = &old_ctx->pipe_ctx[head_index]; 2570 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2571 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2572 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2573 } else { 2574 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2575 if (!idle_pipe) 2576 return NULL; 2577 } 2578 2579 idle_pipe->stream = head_pipe->stream; 2580 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2581 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2582 2583 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2584 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2585 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2586 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2587 2588 return idle_pipe; 2589 } 2590 2591 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2592 { 2593 /* 2594 * DCN32 and DCN321 SKUs may have different sizes for MALL 2595 * but we may not be able to access all the MALL space. 2596 * If the num_chans is power of 2, then we can access all 2597 * of the available MALL space. Otherwise, we can only 2598 * access: 2599 * 2600 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2601 * ((2^floor(log2(num_chans)))/num_chans) 2602 * 2603 * Calculating the MALL sizes for all available SKUs, we 2604 * have come up with the follow simplified check. 2605 * - we have max_chans which provides the max MALL size. 2606 * Each chans supports 4MB of MALL so: 2607 * 2608 * total_cache_size_in_bytes = max_chans * 4 MB 2609 * 2610 * - we have avail_chans which shows the number of channels 2611 * we can use if we can't access the entire MALL space. 2612 * It is generally half of max_chans 2613 * - so we use the following checks: 2614 * 2615 * if (num_chans == max_chans), return max_chans 2616 * if (num_chans < max_chans), return avail_chans 2617 * 2618 * - exception is GC_11_0_0 where we can't access max_chans, 2619 * so we define max_avail_chans as the maximum available 2620 * MALL space 2621 * 2622 */ 2623 int gc_11_0_0_max_chans = 48; 2624 int gc_11_0_0_max_avail_chans = 32; 2625 int gc_11_0_0_avail_chans = 16; 2626 int gc_11_0_3_max_chans = 16; 2627 int gc_11_0_3_avail_chans = 8; 2628 int gc_11_0_2_max_chans = 8; 2629 int gc_11_0_2_avail_chans = 4; 2630 2631 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2632 return (num_chans == gc_11_0_0_max_chans) ? 2633 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2634 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2635 return (num_chans == gc_11_0_2_max_chans) ? 2636 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2637 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2638 return (num_chans == gc_11_0_3_max_chans) ? 2639 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2640 } 2641 } 2642