1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dcn31/dcn31_apg.h" 61 #include "dcn31/dcn31_dio_link_encoder.h" 62 #include "dcn32/dcn32_dio_link_encoder.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn32/dcn32_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "link.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn32/dcn32_mmhubbub.h" 76 77 #include "dcn/dcn_3_2_0_offset.h" 78 #include "dcn/dcn_3_2_0_sh_mask.h" 79 #include "nbio/nbio_4_3_0_offset.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/display_mode_vba_30.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dml/dcn32/dcn32_fpu.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 enum dcn32_clk_src_array_id { 95 DCN32_CLK_SRC_PLL0, 96 DCN32_CLK_SRC_PLL1, 97 DCN32_CLK_SRC_PLL2, 98 DCN32_CLK_SRC_PLL3, 99 DCN32_CLK_SRC_PLL4, 100 DCN32_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 109 110 #define BASE(seg) BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 114 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 117 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name = value 120 121 #define SRI(reg_name, block, id)\ 122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 reg ## block ## id ## _ ## reg_name 124 125 #define SRI_ARR(reg_name, block, id)\ 126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SR_ARR_I2C(reg_name, id) \ 130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 131 132 #define SRI_ARR_I2C(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI2(reg_name, block, id)\ 141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 142 reg ## reg_name 143 #define SRI2_ARR(reg_name, block, id)\ 144 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRIR(var_name, reg_name, block, id)\ 148 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRII(reg_name, block, id)\ 152 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII_ARR_2(reg_name, block, id, inst)\ 156 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_MPC_RMU(reg_name, block, id)\ 160 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_DWB(reg_name, temp_name, block, id)\ 164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## temp_name 166 167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .per_pixel_alpha = true, 661 662 .pixel_format_support = { 663 .argb8888 = true, 664 .nv12 = true, 665 .fp16 = true, 666 .p010 = true, 667 .ayuv = false, 668 }, 669 670 .max_upscale_factor = { 671 .argb8888 = 16000, 672 .nv12 = 16000, 673 .fp16 = 16000 674 }, 675 676 // 6:1 downscaling ratio: 1000/6 = 166.666 677 .max_downscale_factor = { 678 .argb8888 = 167, 679 .nv12 = 167, 680 .fp16 = 167 681 }, 682 64, 683 64 684 }; 685 686 static const struct dc_debug_options debug_defaults_drv = { 687 .disable_dmcu = true, 688 .force_abm_enable = false, 689 .timing_trace = false, 690 .clock_trace = true, 691 .disable_pplib_clock_request = false, 692 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 693 .force_single_disp_pipe_split = false, 694 .disable_dcc = DCC_ENABLE, 695 .vsr_support = true, 696 .performance_trace = false, 697 .max_downscale_src_width = 7680,/*upto 8K*/ 698 .disable_pplib_wm_range = false, 699 .scl_reset_length10 = true, 700 .sanity_checks = false, 701 .underflow_assert_delay_us = 0xFFFFFFFF, 702 .dwb_fi_phase = -1, // -1 = disable, 703 .dmub_command_table = true, 704 .enable_mem_low_power = { 705 .bits = { 706 .vga = false, 707 .i2c = false, 708 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 709 .dscl = false, 710 .cm = false, 711 .mpc = false, 712 .optc = true, 713 } 714 }, 715 .use_max_lb = true, 716 .force_disable_subvp = false, 717 .exit_idle_opt_for_cursor_updates = true, 718 .enable_single_display_2to1_odm_policy = true, 719 720 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 721 .enable_double_buffered_dsc_pg_support = true, 722 .enable_dp_dig_pixel_rate_div_policy = 1, 723 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 724 .alloc_extra_way_for_cursor = true, 725 .min_prefetch_in_strobe_ns = 60000, // 60us 726 .disable_unbounded_requesting = false, 727 .override_dispclk_programming = true, 728 .disable_fpo_optimizations = false, 729 .fpo_vactive_margin_us = 2000, // 2000us 730 .disable_fpo_vactive = true, 731 .disable_boot_optimizations = false, 732 }; 733 734 static const struct dc_debug_options debug_defaults_diags = { 735 .disable_dmcu = true, 736 .force_abm_enable = false, 737 .timing_trace = true, 738 .clock_trace = true, 739 .disable_dpp_power_gate = true, 740 .disable_hubp_power_gate = true, 741 .disable_dsc_power_gate = true, 742 .disable_clock_gate = true, 743 .disable_pplib_clock_request = true, 744 .disable_pplib_wm_range = true, 745 .disable_stutter = false, 746 .scl_reset_length10 = true, 747 .dwb_fi_phase = -1, // -1 = disable 748 .dmub_command_table = true, 749 .enable_tri_buf = true, 750 .use_max_lb = true, 751 .force_disable_subvp = true 752 }; 753 754 static struct dce_aux *dcn32_aux_engine_create( 755 struct dc_context *ctx, 756 uint32_t inst) 757 { 758 struct aux_engine_dce110 *aux_engine = 759 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 760 761 if (!aux_engine) 762 return NULL; 763 764 #undef REG_STRUCT 765 #define REG_STRUCT aux_engine_regs 766 aux_engine_regs_init(0), 767 aux_engine_regs_init(1), 768 aux_engine_regs_init(2), 769 aux_engine_regs_init(3), 770 aux_engine_regs_init(4); 771 772 dce110_aux_engine_construct(aux_engine, ctx, inst, 773 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 774 &aux_engine_regs[inst], 775 &aux_mask, 776 &aux_shift, 777 ctx->dc->caps.extended_aux_timeout_support); 778 779 return &aux_engine->base; 780 } 781 #define i2c_inst_regs_init(id)\ 782 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 783 784 static struct dce_i2c_registers i2c_hw_regs[5]; 785 786 static const struct dce_i2c_shift i2c_shifts = { 787 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 788 }; 789 790 static const struct dce_i2c_mask i2c_masks = { 791 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 792 }; 793 794 static struct dce_i2c_hw *dcn32_i2c_hw_create( 795 struct dc_context *ctx, 796 uint32_t inst) 797 { 798 struct dce_i2c_hw *dce_i2c_hw = 799 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 800 801 if (!dce_i2c_hw) 802 return NULL; 803 804 #undef REG_STRUCT 805 #define REG_STRUCT i2c_hw_regs 806 i2c_inst_regs_init(1), 807 i2c_inst_regs_init(2), 808 i2c_inst_regs_init(3), 809 i2c_inst_regs_init(4), 810 i2c_inst_regs_init(5); 811 812 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 813 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 814 815 return dce_i2c_hw; 816 } 817 818 static struct clock_source *dcn32_clock_source_create( 819 struct dc_context *ctx, 820 struct dc_bios *bios, 821 enum clock_source_id id, 822 const struct dce110_clk_src_regs *regs, 823 bool dp_clk_src) 824 { 825 struct dce110_clk_src *clk_src = 826 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 827 828 if (!clk_src) 829 return NULL; 830 831 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 832 regs, &cs_shift, &cs_mask)) { 833 clk_src->base.dp_clk_src = dp_clk_src; 834 return &clk_src->base; 835 } 836 837 kfree(clk_src); 838 BREAK_TO_DEBUGGER(); 839 return NULL; 840 } 841 842 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 843 { 844 int i; 845 846 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 847 GFP_KERNEL); 848 849 if (!hubbub2) 850 return NULL; 851 852 #undef REG_STRUCT 853 #define REG_STRUCT hubbub_reg 854 hubbub_reg_init(); 855 856 #undef REG_STRUCT 857 #define REG_STRUCT vmid_regs 858 vmid_regs_init(0), 859 vmid_regs_init(1), 860 vmid_regs_init(2), 861 vmid_regs_init(3), 862 vmid_regs_init(4), 863 vmid_regs_init(5), 864 vmid_regs_init(6), 865 vmid_regs_init(7), 866 vmid_regs_init(8), 867 vmid_regs_init(9), 868 vmid_regs_init(10), 869 vmid_regs_init(11), 870 vmid_regs_init(12), 871 vmid_regs_init(13), 872 vmid_regs_init(14), 873 vmid_regs_init(15); 874 875 hubbub32_construct(hubbub2, ctx, 876 &hubbub_reg, 877 &hubbub_shift, 878 &hubbub_mask, 879 ctx->dc->dml.ip.det_buffer_size_kbytes, 880 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 881 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 882 883 884 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 885 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 886 887 vmid->ctx = ctx; 888 889 vmid->regs = &vmid_regs[i]; 890 vmid->shifts = &vmid_shifts; 891 vmid->masks = &vmid_masks; 892 } 893 894 return &hubbub2->base; 895 } 896 897 static struct hubp *dcn32_hubp_create( 898 struct dc_context *ctx, 899 uint32_t inst) 900 { 901 struct dcn20_hubp *hubp2 = 902 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 903 904 if (!hubp2) 905 return NULL; 906 907 #undef REG_STRUCT 908 #define REG_STRUCT hubp_regs 909 hubp_regs_init(0), 910 hubp_regs_init(1), 911 hubp_regs_init(2), 912 hubp_regs_init(3); 913 914 if (hubp32_construct(hubp2, ctx, inst, 915 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 916 return &hubp2->base; 917 918 BREAK_TO_DEBUGGER(); 919 kfree(hubp2); 920 return NULL; 921 } 922 923 static void dcn32_dpp_destroy(struct dpp **dpp) 924 { 925 kfree(TO_DCN30_DPP(*dpp)); 926 *dpp = NULL; 927 } 928 929 static struct dpp *dcn32_dpp_create( 930 struct dc_context *ctx, 931 uint32_t inst) 932 { 933 struct dcn3_dpp *dpp3 = 934 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 935 936 if (!dpp3) 937 return NULL; 938 939 #undef REG_STRUCT 940 #define REG_STRUCT dpp_regs 941 dpp_regs_init(0), 942 dpp_regs_init(1), 943 dpp_regs_init(2), 944 dpp_regs_init(3); 945 946 if (dpp32_construct(dpp3, ctx, inst, 947 &dpp_regs[inst], &tf_shift, &tf_mask)) 948 return &dpp3->base; 949 950 BREAK_TO_DEBUGGER(); 951 kfree(dpp3); 952 return NULL; 953 } 954 955 static struct mpc *dcn32_mpc_create( 956 struct dc_context *ctx, 957 int num_mpcc, 958 int num_rmu) 959 { 960 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 961 GFP_KERNEL); 962 963 if (!mpc30) 964 return NULL; 965 966 #undef REG_STRUCT 967 #define REG_STRUCT mpc_regs 968 dcn_mpc_regs_init(); 969 970 dcn32_mpc_construct(mpc30, ctx, 971 &mpc_regs, 972 &mpc_shift, 973 &mpc_mask, 974 num_mpcc, 975 num_rmu); 976 977 return &mpc30->base; 978 } 979 980 static struct output_pixel_processor *dcn32_opp_create( 981 struct dc_context *ctx, uint32_t inst) 982 { 983 struct dcn20_opp *opp2 = 984 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 985 986 if (!opp2) { 987 BREAK_TO_DEBUGGER(); 988 return NULL; 989 } 990 991 #undef REG_STRUCT 992 #define REG_STRUCT opp_regs 993 opp_regs_init(0), 994 opp_regs_init(1), 995 opp_regs_init(2), 996 opp_regs_init(3); 997 998 dcn20_opp_construct(opp2, ctx, inst, 999 &opp_regs[inst], &opp_shift, &opp_mask); 1000 return &opp2->base; 1001 } 1002 1003 1004 static struct timing_generator *dcn32_timing_generator_create( 1005 struct dc_context *ctx, 1006 uint32_t instance) 1007 { 1008 struct optc *tgn10 = 1009 kzalloc(sizeof(struct optc), GFP_KERNEL); 1010 1011 if (!tgn10) 1012 return NULL; 1013 1014 #undef REG_STRUCT 1015 #define REG_STRUCT optc_regs 1016 optc_regs_init(0), 1017 optc_regs_init(1), 1018 optc_regs_init(2), 1019 optc_regs_init(3); 1020 1021 tgn10->base.inst = instance; 1022 tgn10->base.ctx = ctx; 1023 1024 tgn10->tg_regs = &optc_regs[instance]; 1025 tgn10->tg_shift = &optc_shift; 1026 tgn10->tg_mask = &optc_mask; 1027 1028 dcn32_timing_generator_init(tgn10); 1029 1030 return &tgn10->base; 1031 } 1032 1033 static const struct encoder_feature_support link_enc_feature = { 1034 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1035 .max_hdmi_pixel_clock = 600000, 1036 .hdmi_ycbcr420_supported = true, 1037 .dp_ycbcr420_supported = true, 1038 .fec_supported = true, 1039 .flags.bits.IS_HBR2_CAPABLE = true, 1040 .flags.bits.IS_HBR3_CAPABLE = true, 1041 .flags.bits.IS_TPS3_CAPABLE = true, 1042 .flags.bits.IS_TPS4_CAPABLE = true 1043 }; 1044 1045 static struct link_encoder *dcn32_link_encoder_create( 1046 struct dc_context *ctx, 1047 const struct encoder_init_data *enc_init_data) 1048 { 1049 struct dcn20_link_encoder *enc20 = 1050 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1051 1052 if (!enc20) 1053 return NULL; 1054 1055 #undef REG_STRUCT 1056 #define REG_STRUCT link_enc_aux_regs 1057 aux_regs_init(0), 1058 aux_regs_init(1), 1059 aux_regs_init(2), 1060 aux_regs_init(3), 1061 aux_regs_init(4); 1062 1063 #undef REG_STRUCT 1064 #define REG_STRUCT link_enc_hpd_regs 1065 hpd_regs_init(0), 1066 hpd_regs_init(1), 1067 hpd_regs_init(2), 1068 hpd_regs_init(3), 1069 hpd_regs_init(4); 1070 1071 #undef REG_STRUCT 1072 #define REG_STRUCT link_enc_regs 1073 link_regs_init(0, A), 1074 link_regs_init(1, B), 1075 link_regs_init(2, C), 1076 link_regs_init(3, D), 1077 link_regs_init(4, E); 1078 1079 dcn32_link_encoder_construct(enc20, 1080 enc_init_data, 1081 &link_enc_feature, 1082 &link_enc_regs[enc_init_data->transmitter], 1083 &link_enc_aux_regs[enc_init_data->channel - 1], 1084 &link_enc_hpd_regs[enc_init_data->hpd_source], 1085 &le_shift, 1086 &le_mask); 1087 1088 return &enc20->enc10.base; 1089 } 1090 1091 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1092 { 1093 struct dcn31_panel_cntl *panel_cntl = 1094 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1095 1096 if (!panel_cntl) 1097 return NULL; 1098 1099 dcn31_panel_cntl_construct(panel_cntl, init_data); 1100 1101 return &panel_cntl->base; 1102 } 1103 1104 static void read_dce_straps( 1105 struct dc_context *ctx, 1106 struct resource_straps *straps) 1107 { 1108 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1109 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1110 1111 } 1112 1113 static struct audio *dcn32_create_audio( 1114 struct dc_context *ctx, unsigned int inst) 1115 { 1116 1117 #undef REG_STRUCT 1118 #define REG_STRUCT audio_regs 1119 audio_regs_init(0), 1120 audio_regs_init(1), 1121 audio_regs_init(2), 1122 audio_regs_init(3), 1123 audio_regs_init(4); 1124 1125 return dce_audio_create(ctx, inst, 1126 &audio_regs[inst], &audio_shift, &audio_mask); 1127 } 1128 1129 static struct vpg *dcn32_vpg_create( 1130 struct dc_context *ctx, 1131 uint32_t inst) 1132 { 1133 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1134 1135 if (!vpg3) 1136 return NULL; 1137 1138 #undef REG_STRUCT 1139 #define REG_STRUCT vpg_regs 1140 vpg_regs_init(0), 1141 vpg_regs_init(1), 1142 vpg_regs_init(2), 1143 vpg_regs_init(3), 1144 vpg_regs_init(4), 1145 vpg_regs_init(5), 1146 vpg_regs_init(6), 1147 vpg_regs_init(7), 1148 vpg_regs_init(8), 1149 vpg_regs_init(9); 1150 1151 vpg3_construct(vpg3, ctx, inst, 1152 &vpg_regs[inst], 1153 &vpg_shift, 1154 &vpg_mask); 1155 1156 return &vpg3->base; 1157 } 1158 1159 static struct afmt *dcn32_afmt_create( 1160 struct dc_context *ctx, 1161 uint32_t inst) 1162 { 1163 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1164 1165 if (!afmt3) 1166 return NULL; 1167 1168 #undef REG_STRUCT 1169 #define REG_STRUCT afmt_regs 1170 afmt_regs_init(0), 1171 afmt_regs_init(1), 1172 afmt_regs_init(2), 1173 afmt_regs_init(3), 1174 afmt_regs_init(4), 1175 afmt_regs_init(5); 1176 1177 afmt3_construct(afmt3, ctx, inst, 1178 &afmt_regs[inst], 1179 &afmt_shift, 1180 &afmt_mask); 1181 1182 return &afmt3->base; 1183 } 1184 1185 static struct apg *dcn31_apg_create( 1186 struct dc_context *ctx, 1187 uint32_t inst) 1188 { 1189 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1190 1191 if (!apg31) 1192 return NULL; 1193 1194 #undef REG_STRUCT 1195 #define REG_STRUCT apg_regs 1196 apg_regs_init(0), 1197 apg_regs_init(1), 1198 apg_regs_init(2), 1199 apg_regs_init(3); 1200 1201 apg31_construct(apg31, ctx, inst, 1202 &apg_regs[inst], 1203 &apg_shift, 1204 &apg_mask); 1205 1206 return &apg31->base; 1207 } 1208 1209 static struct stream_encoder *dcn32_stream_encoder_create( 1210 enum engine_id eng_id, 1211 struct dc_context *ctx) 1212 { 1213 struct dcn10_stream_encoder *enc1; 1214 struct vpg *vpg; 1215 struct afmt *afmt; 1216 int vpg_inst; 1217 int afmt_inst; 1218 1219 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1220 if (eng_id <= ENGINE_ID_DIGF) { 1221 vpg_inst = eng_id; 1222 afmt_inst = eng_id; 1223 } else 1224 return NULL; 1225 1226 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1227 vpg = dcn32_vpg_create(ctx, vpg_inst); 1228 afmt = dcn32_afmt_create(ctx, afmt_inst); 1229 1230 if (!enc1 || !vpg || !afmt) { 1231 kfree(enc1); 1232 kfree(vpg); 1233 kfree(afmt); 1234 return NULL; 1235 } 1236 1237 #undef REG_STRUCT 1238 #define REG_STRUCT stream_enc_regs 1239 stream_enc_regs_init(0), 1240 stream_enc_regs_init(1), 1241 stream_enc_regs_init(2), 1242 stream_enc_regs_init(3), 1243 stream_enc_regs_init(4); 1244 1245 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1246 eng_id, vpg, afmt, 1247 &stream_enc_regs[eng_id], 1248 &se_shift, &se_mask); 1249 1250 return &enc1->base; 1251 } 1252 1253 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1254 enum engine_id eng_id, 1255 struct dc_context *ctx) 1256 { 1257 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1258 struct vpg *vpg; 1259 struct apg *apg; 1260 uint32_t hpo_dp_inst; 1261 uint32_t vpg_inst; 1262 uint32_t apg_inst; 1263 1264 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1265 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1266 1267 /* Mapping of VPG register blocks to HPO DP block instance: 1268 * VPG[6] -> HPO_DP[0] 1269 * VPG[7] -> HPO_DP[1] 1270 * VPG[8] -> HPO_DP[2] 1271 * VPG[9] -> HPO_DP[3] 1272 */ 1273 vpg_inst = hpo_dp_inst + 6; 1274 1275 /* Mapping of APG register blocks to HPO DP block instance: 1276 * APG[0] -> HPO_DP[0] 1277 * APG[1] -> HPO_DP[1] 1278 * APG[2] -> HPO_DP[2] 1279 * APG[3] -> HPO_DP[3] 1280 */ 1281 apg_inst = hpo_dp_inst; 1282 1283 /* allocate HPO stream encoder and create VPG sub-block */ 1284 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1285 vpg = dcn32_vpg_create(ctx, vpg_inst); 1286 apg = dcn31_apg_create(ctx, apg_inst); 1287 1288 if (!hpo_dp_enc31 || !vpg || !apg) { 1289 kfree(hpo_dp_enc31); 1290 kfree(vpg); 1291 kfree(apg); 1292 return NULL; 1293 } 1294 1295 #undef REG_STRUCT 1296 #define REG_STRUCT hpo_dp_stream_enc_regs 1297 hpo_dp_stream_encoder_reg_init(0), 1298 hpo_dp_stream_encoder_reg_init(1), 1299 hpo_dp_stream_encoder_reg_init(2), 1300 hpo_dp_stream_encoder_reg_init(3); 1301 1302 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1303 hpo_dp_inst, eng_id, vpg, apg, 1304 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1305 &hpo_dp_se_shift, &hpo_dp_se_mask); 1306 1307 return &hpo_dp_enc31->base; 1308 } 1309 1310 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1311 uint8_t inst, 1312 struct dc_context *ctx) 1313 { 1314 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1315 1316 /* allocate HPO link encoder */ 1317 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1318 1319 #undef REG_STRUCT 1320 #define REG_STRUCT hpo_dp_link_enc_regs 1321 hpo_dp_link_encoder_reg_init(0), 1322 hpo_dp_link_encoder_reg_init(1); 1323 1324 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1325 &hpo_dp_link_enc_regs[inst], 1326 &hpo_dp_le_shift, &hpo_dp_le_mask); 1327 1328 return &hpo_dp_enc31->base; 1329 } 1330 1331 static struct dce_hwseq *dcn32_hwseq_create( 1332 struct dc_context *ctx) 1333 { 1334 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1335 1336 #undef REG_STRUCT 1337 #define REG_STRUCT hwseq_reg 1338 hwseq_reg_init(); 1339 1340 if (hws) { 1341 hws->ctx = ctx; 1342 hws->regs = &hwseq_reg; 1343 hws->shifts = &hwseq_shift; 1344 hws->masks = &hwseq_mask; 1345 } 1346 return hws; 1347 } 1348 static const struct resource_create_funcs res_create_funcs = { 1349 .read_dce_straps = read_dce_straps, 1350 .create_audio = dcn32_create_audio, 1351 .create_stream_encoder = dcn32_stream_encoder_create, 1352 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1353 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1354 .create_hwseq = dcn32_hwseq_create, 1355 }; 1356 1357 static const struct resource_create_funcs res_create_maximus_funcs = { 1358 .read_dce_straps = NULL, 1359 .create_audio = NULL, 1360 .create_stream_encoder = NULL, 1361 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1362 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1363 .create_hwseq = dcn32_hwseq_create, 1364 }; 1365 1366 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1367 { 1368 unsigned int i; 1369 1370 for (i = 0; i < pool->base.stream_enc_count; i++) { 1371 if (pool->base.stream_enc[i] != NULL) { 1372 if (pool->base.stream_enc[i]->vpg != NULL) { 1373 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1374 pool->base.stream_enc[i]->vpg = NULL; 1375 } 1376 if (pool->base.stream_enc[i]->afmt != NULL) { 1377 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1378 pool->base.stream_enc[i]->afmt = NULL; 1379 } 1380 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1381 pool->base.stream_enc[i] = NULL; 1382 } 1383 } 1384 1385 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1386 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1387 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1388 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1389 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1390 } 1391 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1392 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1393 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1394 } 1395 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1396 pool->base.hpo_dp_stream_enc[i] = NULL; 1397 } 1398 } 1399 1400 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1401 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1402 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1403 pool->base.hpo_dp_link_enc[i] = NULL; 1404 } 1405 } 1406 1407 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1408 if (pool->base.dscs[i] != NULL) 1409 dcn20_dsc_destroy(&pool->base.dscs[i]); 1410 } 1411 1412 if (pool->base.mpc != NULL) { 1413 kfree(TO_DCN20_MPC(pool->base.mpc)); 1414 pool->base.mpc = NULL; 1415 } 1416 if (pool->base.hubbub != NULL) { 1417 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1418 pool->base.hubbub = NULL; 1419 } 1420 for (i = 0; i < pool->base.pipe_count; i++) { 1421 if (pool->base.dpps[i] != NULL) 1422 dcn32_dpp_destroy(&pool->base.dpps[i]); 1423 1424 if (pool->base.ipps[i] != NULL) 1425 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1426 1427 if (pool->base.hubps[i] != NULL) { 1428 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1429 pool->base.hubps[i] = NULL; 1430 } 1431 1432 if (pool->base.irqs != NULL) { 1433 dal_irq_service_destroy(&pool->base.irqs); 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1438 if (pool->base.engines[i] != NULL) 1439 dce110_engine_destroy(&pool->base.engines[i]); 1440 if (pool->base.hw_i2cs[i] != NULL) { 1441 kfree(pool->base.hw_i2cs[i]); 1442 pool->base.hw_i2cs[i] = NULL; 1443 } 1444 if (pool->base.sw_i2cs[i] != NULL) { 1445 kfree(pool->base.sw_i2cs[i]); 1446 pool->base.sw_i2cs[i] = NULL; 1447 } 1448 } 1449 1450 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1451 if (pool->base.opps[i] != NULL) 1452 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1453 } 1454 1455 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1456 if (pool->base.timing_generators[i] != NULL) { 1457 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1458 pool->base.timing_generators[i] = NULL; 1459 } 1460 } 1461 1462 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1463 if (pool->base.dwbc[i] != NULL) { 1464 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1465 pool->base.dwbc[i] = NULL; 1466 } 1467 if (pool->base.mcif_wb[i] != NULL) { 1468 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1469 pool->base.mcif_wb[i] = NULL; 1470 } 1471 } 1472 1473 for (i = 0; i < pool->base.audio_count; i++) { 1474 if (pool->base.audios[i]) 1475 dce_aud_destroy(&pool->base.audios[i]); 1476 } 1477 1478 for (i = 0; i < pool->base.clk_src_count; i++) { 1479 if (pool->base.clock_sources[i] != NULL) { 1480 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1481 pool->base.clock_sources[i] = NULL; 1482 } 1483 } 1484 1485 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1486 if (pool->base.mpc_lut[i] != NULL) { 1487 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1488 pool->base.mpc_lut[i] = NULL; 1489 } 1490 if (pool->base.mpc_shaper[i] != NULL) { 1491 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1492 pool->base.mpc_shaper[i] = NULL; 1493 } 1494 } 1495 1496 if (pool->base.dp_clock_source != NULL) { 1497 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1498 pool->base.dp_clock_source = NULL; 1499 } 1500 1501 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1502 if (pool->base.multiple_abms[i] != NULL) 1503 dce_abm_destroy(&pool->base.multiple_abms[i]); 1504 } 1505 1506 if (pool->base.psr != NULL) 1507 dmub_psr_destroy(&pool->base.psr); 1508 1509 if (pool->base.dccg != NULL) 1510 dcn_dccg_destroy(&pool->base.dccg); 1511 1512 if (pool->base.oem_device != NULL) { 1513 struct dc *dc = pool->base.oem_device->ctx->dc; 1514 1515 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1516 } 1517 } 1518 1519 1520 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1521 { 1522 int i; 1523 uint32_t dwb_count = pool->res_cap->num_dwb; 1524 1525 for (i = 0; i < dwb_count; i++) { 1526 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1527 GFP_KERNEL); 1528 1529 if (!dwbc30) { 1530 dm_error("DC: failed to create dwbc30!\n"); 1531 return false; 1532 } 1533 1534 #undef REG_STRUCT 1535 #define REG_STRUCT dwbc30_regs 1536 dwbc_regs_dcn3_init(0); 1537 1538 dcn30_dwbc_construct(dwbc30, ctx, 1539 &dwbc30_regs[i], 1540 &dwbc30_shift, 1541 &dwbc30_mask, 1542 i); 1543 1544 pool->dwbc[i] = &dwbc30->base; 1545 } 1546 return true; 1547 } 1548 1549 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1550 { 1551 int i; 1552 uint32_t dwb_count = pool->res_cap->num_dwb; 1553 1554 for (i = 0; i < dwb_count; i++) { 1555 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1556 GFP_KERNEL); 1557 1558 if (!mcif_wb30) { 1559 dm_error("DC: failed to create mcif_wb30!\n"); 1560 return false; 1561 } 1562 1563 #undef REG_STRUCT 1564 #define REG_STRUCT mcif_wb30_regs 1565 mcif_wb_regs_dcn3_init(0); 1566 1567 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1568 &mcif_wb30_regs[i], 1569 &mcif_wb30_shift, 1570 &mcif_wb30_mask, 1571 i); 1572 1573 pool->mcif_wb[i] = &mcif_wb30->base; 1574 } 1575 return true; 1576 } 1577 1578 static struct display_stream_compressor *dcn32_dsc_create( 1579 struct dc_context *ctx, uint32_t inst) 1580 { 1581 struct dcn20_dsc *dsc = 1582 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1583 1584 if (!dsc) { 1585 BREAK_TO_DEBUGGER(); 1586 return NULL; 1587 } 1588 1589 #undef REG_STRUCT 1590 #define REG_STRUCT dsc_regs 1591 dsc_regsDCN20_init(0), 1592 dsc_regsDCN20_init(1), 1593 dsc_regsDCN20_init(2), 1594 dsc_regsDCN20_init(3); 1595 1596 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1597 1598 dsc->max_image_width = 6016; 1599 1600 return &dsc->base; 1601 } 1602 1603 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1604 { 1605 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1606 1607 dcn32_resource_destruct(dcn32_pool); 1608 kfree(dcn32_pool); 1609 *pool = NULL; 1610 } 1611 1612 bool dcn32_acquire_post_bldn_3dlut( 1613 struct resource_context *res_ctx, 1614 const struct resource_pool *pool, 1615 int mpcc_id, 1616 struct dc_3dlut **lut, 1617 struct dc_transfer_func **shaper) 1618 { 1619 bool ret = false; 1620 1621 ASSERT(*lut == NULL && *shaper == NULL); 1622 *lut = NULL; 1623 *shaper = NULL; 1624 1625 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1626 *lut = pool->mpc_lut[mpcc_id]; 1627 *shaper = pool->mpc_shaper[mpcc_id]; 1628 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1629 ret = true; 1630 } 1631 return ret; 1632 } 1633 1634 bool dcn32_release_post_bldn_3dlut( 1635 struct resource_context *res_ctx, 1636 const struct resource_pool *pool, 1637 struct dc_3dlut **lut, 1638 struct dc_transfer_func **shaper) 1639 { 1640 int i; 1641 bool ret = false; 1642 1643 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1644 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1645 res_ctx->is_mpc_3dlut_acquired[i] = false; 1646 pool->mpc_lut[i]->state.raw = 0; 1647 *lut = NULL; 1648 *shaper = NULL; 1649 ret = true; 1650 break; 1651 } 1652 } 1653 return ret; 1654 } 1655 1656 static void dcn32_enable_phantom_plane(struct dc *dc, 1657 struct dc_state *context, 1658 struct dc_stream_state *phantom_stream, 1659 unsigned int dc_pipe_idx) 1660 { 1661 struct dc_plane_state *phantom_plane = NULL; 1662 struct dc_plane_state *prev_phantom_plane = NULL; 1663 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1664 1665 while (curr_pipe) { 1666 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1667 phantom_plane = prev_phantom_plane; 1668 else 1669 phantom_plane = dc_create_plane_state(dc); 1670 1671 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1672 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1673 sizeof(phantom_plane->scaling_quality)); 1674 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1675 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1676 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1677 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1678 sizeof(phantom_plane->plane_size)); 1679 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1680 sizeof(phantom_plane->tiling_info)); 1681 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1682 phantom_plane->format = curr_pipe->plane_state->format; 1683 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1684 phantom_plane->visible = curr_pipe->plane_state->visible; 1685 1686 /* Shadow pipe has small viewport. */ 1687 phantom_plane->clip_rect.y = 0; 1688 phantom_plane->clip_rect.height = phantom_stream->src.height; 1689 1690 phantom_plane->is_phantom = true; 1691 1692 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1693 1694 curr_pipe = curr_pipe->bottom_pipe; 1695 prev_phantom_plane = phantom_plane; 1696 } 1697 } 1698 1699 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1700 struct dc_state *context, 1701 display_e2e_pipe_params_st *pipes, 1702 unsigned int pipe_cnt, 1703 unsigned int dc_pipe_idx) 1704 { 1705 struct dc_stream_state *phantom_stream = NULL; 1706 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1707 1708 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1709 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1710 phantom_stream->dpms_off = true; 1711 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1712 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1713 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1714 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1715 1716 /* stream has limited viewport and small timing */ 1717 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1718 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1719 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1720 DC_FP_START(); 1721 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1722 DC_FP_END(); 1723 1724 dc_add_stream_to_ctx(dc, context, phantom_stream); 1725 return phantom_stream; 1726 } 1727 1728 void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) 1729 { 1730 int i; 1731 struct dc_plane_state *phantom_plane = NULL; 1732 struct dc_stream_state *phantom_stream = NULL; 1733 1734 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1735 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1736 1737 if (!pipe->top_pipe && !pipe->prev_odm_pipe && 1738 pipe->plane_state && pipe->stream && 1739 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1740 phantom_plane = pipe->plane_state; 1741 phantom_stream = pipe->stream; 1742 1743 dc_plane_state_retain(phantom_plane); 1744 dc_stream_retain(phantom_stream); 1745 } 1746 } 1747 } 1748 1749 // return true if removed piped from ctx, false otherwise 1750 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update) 1751 { 1752 int i; 1753 bool removed_pipe = false; 1754 struct dc_plane_state *phantom_plane = NULL; 1755 struct dc_stream_state *phantom_stream = NULL; 1756 1757 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1758 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1759 // build scaling params for phantom pipes 1760 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1761 phantom_plane = pipe->plane_state; 1762 phantom_stream = pipe->stream; 1763 1764 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1765 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1766 1767 /* Ref count is incremented on allocation and also when added to the context. 1768 * Therefore we must call release for the the phantom plane and stream once 1769 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1770 */ 1771 dc_plane_state_release(phantom_plane); 1772 dc_stream_release(phantom_stream); 1773 1774 removed_pipe = true; 1775 } 1776 1777 /* For non-full updates, a shallow copy of the current state 1778 * is created. In this case we don't want to erase the current 1779 * state (there can be 2 HIRQL threads, one in flip, and one in 1780 * checkMPO) that can cause a race condition. 1781 * 1782 * This is just a workaround, needs a proper fix. 1783 */ 1784 if (!fast_update) { 1785 // Clear all phantom stream info 1786 if (pipe->stream) { 1787 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1788 pipe->stream->mall_stream_config.paired_stream = NULL; 1789 } 1790 1791 if (pipe->plane_state) { 1792 pipe->plane_state->is_phantom = false; 1793 } 1794 } 1795 } 1796 return removed_pipe; 1797 } 1798 1799 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1800 * require a phantom pipe / stream 1801 */ 1802 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1803 display_e2e_pipe_params_st *pipes, 1804 unsigned int pipe_cnt, 1805 unsigned int index) 1806 { 1807 struct dc_stream_state *phantom_stream = NULL; 1808 unsigned int i; 1809 1810 // The index of the DC pipe passed into this function is guarenteed to 1811 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1812 // already have phantom pipe assigned, etc.) by previous checks. 1813 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1814 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1815 1816 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1817 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1818 1819 // Build scaling params for phantom pipes which were newly added. 1820 // We determine which phantom pipes were added by comparing with 1821 // the phantom stream. 1822 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1823 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1824 pipe->stream->use_dynamic_meta = false; 1825 pipe->plane_state->flip_immediate = false; 1826 if (!resource_build_scaling_params(pipe)) { 1827 // Log / remove phantom pipes since failed to build scaling params 1828 } 1829 } 1830 } 1831 } 1832 1833 bool dcn32_validate_bandwidth(struct dc *dc, 1834 struct dc_state *context, 1835 bool fast_validate) 1836 { 1837 bool out = false; 1838 1839 BW_VAL_TRACE_SETUP(); 1840 1841 int vlevel = 0; 1842 int pipe_cnt = 0; 1843 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1844 struct mall_temp_config mall_temp_config; 1845 1846 /* To handle Freesync properly, setting FreeSync DML parameters 1847 * to its default state for the first stage of validation 1848 */ 1849 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1850 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1851 1852 DC_LOGGER_INIT(dc->ctx->logger); 1853 1854 /* For fast validation, there are situations where a shallow copy of 1855 * of the dc->current_state is created for the validation. In this case 1856 * we want to save and restore the mall config because we always 1857 * teardown subvp at the beginning of validation (and don't attempt 1858 * to add it back if it's fast validation). If we don't restore the 1859 * subvp config in cases of fast validation + shallow copy of the 1860 * dc->current_state, the dc->current_state will have a partially 1861 * removed subvp state when we did not intend to remove it. 1862 */ 1863 if (fast_validate) { 1864 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1865 dcn32_save_mall_state(dc, context, &mall_temp_config); 1866 } 1867 1868 BW_VAL_TRACE_COUNT(); 1869 1870 DC_FP_START(); 1871 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1872 DC_FP_END(); 1873 1874 if (fast_validate) 1875 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1876 1877 if (pipe_cnt == 0) 1878 goto validate_out; 1879 1880 if (!out) 1881 goto validate_fail; 1882 1883 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1884 1885 if (fast_validate) { 1886 BW_VAL_TRACE_SKIP(fast); 1887 goto validate_out; 1888 } 1889 1890 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1891 1892 BW_VAL_TRACE_END_WATERMARKS(); 1893 1894 goto validate_out; 1895 1896 validate_fail: 1897 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1898 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1899 1900 BW_VAL_TRACE_SKIP(fail); 1901 out = false; 1902 1903 validate_out: 1904 kfree(pipes); 1905 1906 BW_VAL_TRACE_FINISH(); 1907 1908 return out; 1909 } 1910 1911 int dcn32_populate_dml_pipes_from_context( 1912 struct dc *dc, struct dc_state *context, 1913 display_e2e_pipe_params_st *pipes, 1914 bool fast_validate) 1915 { 1916 int i, pipe_cnt; 1917 struct resource_context *res_ctx = &context->res_ctx; 1918 struct pipe_ctx *pipe; 1919 bool subvp_in_use = false; 1920 struct dc_crtc_timing *timing; 1921 bool vsr_odm_support = false; 1922 1923 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1924 1925 /* Determine whether we will apply ODM 2to1 policy: 1926 * Applies to single display and where the number of planes is less than 3. 1927 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1928 * 1929 * Apply pipe split policy first so we can predict the pipe split correctly 1930 * (dcn32_predict_pipe_split). 1931 */ 1932 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1933 if (!res_ctx->pipe_ctx[i].stream) 1934 continue; 1935 pipe = &res_ctx->pipe_ctx[i]; 1936 timing = &pipe->stream->timing; 1937 1938 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1939 vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 && 1940 res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width); 1941 if (context->stream_count == 1 && 1942 context->stream_status[0].plane_count == 1 && 1943 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1944 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1945 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1946 dc->debug.enable_single_display_2to1_odm_policy && 1947 !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr 1948 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1949 } 1950 pipe_cnt++; 1951 } 1952 1953 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1954 1955 if (!res_ctx->pipe_ctx[i].stream) 1956 continue; 1957 pipe = &res_ctx->pipe_ctx[i]; 1958 timing = &pipe->stream->timing; 1959 1960 pipes[pipe_cnt].pipe.src.gpuvm = true; 1961 DC_FP_START(); 1962 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1963 DC_FP_END(); 1964 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1965 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1966 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1967 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1968 1969 /* Only populate DML input with subvp info for full updates. 1970 * This is just a workaround -- needs a proper fix. 1971 */ 1972 if (!fast_validate) { 1973 switch (pipe->stream->mall_stream_config.type) { 1974 case SUBVP_MAIN: 1975 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1976 subvp_in_use = true; 1977 break; 1978 case SUBVP_PHANTOM: 1979 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1980 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1981 // Disallow unbounded req for SubVP according to DCHUB programming guide 1982 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1983 break; 1984 case SUBVP_NONE: 1985 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1986 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1987 break; 1988 default: 1989 break; 1990 } 1991 } 1992 1993 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1994 if (pipes[pipe_cnt].dout.dsc_enable) { 1995 switch (timing->display_color_depth) { 1996 case COLOR_DEPTH_888: 1997 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1998 break; 1999 case COLOR_DEPTH_101010: 2000 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 2001 break; 2002 case COLOR_DEPTH_121212: 2003 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2004 break; 2005 default: 2006 ASSERT(0); 2007 break; 2008 } 2009 } 2010 2011 DC_FP_START(); 2012 dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 2013 DC_FP_END(); 2014 2015 pipe_cnt++; 2016 } 2017 2018 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2019 * the DET available for each pipe). Use the DET override input to maintain our driver 2020 * policy. 2021 */ 2022 dcn32_set_det_allocations(dc, context, pipes); 2023 2024 // In general cases we want to keep the dram clock change requirement 2025 // (prefer configs that support MCLK switch). Only override to false 2026 // for SubVP 2027 if (subvp_in_use) 2028 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2029 else 2030 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2031 2032 return pipe_cnt; 2033 } 2034 2035 static struct dc_cap_funcs cap_funcs = { 2036 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2037 }; 2038 2039 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2040 display_e2e_pipe_params_st *pipes, 2041 int pipe_cnt, 2042 int vlevel) 2043 { 2044 DC_FP_START(); 2045 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2046 DC_FP_END(); 2047 } 2048 2049 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2050 { 2051 DC_FP_START(); 2052 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2053 DC_FP_END(); 2054 } 2055 2056 static struct resource_funcs dcn32_res_pool_funcs = { 2057 .destroy = dcn32_destroy_resource_pool, 2058 .link_enc_create = dcn32_link_encoder_create, 2059 .link_enc_create_minimal = NULL, 2060 .panel_cntl_create = dcn32_panel_cntl_create, 2061 .validate_bandwidth = dcn32_validate_bandwidth, 2062 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2063 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2064 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2065 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2066 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2067 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2068 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2069 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2070 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2071 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2072 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2073 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2074 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2075 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2076 .add_phantom_pipes = dcn32_add_phantom_pipes, 2077 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2078 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 2079 .save_mall_state = dcn32_save_mall_state, 2080 .restore_mall_state = dcn32_restore_mall_state, 2081 }; 2082 2083 2084 static bool dcn32_resource_construct( 2085 uint8_t num_virtual_links, 2086 struct dc *dc, 2087 struct dcn32_resource_pool *pool) 2088 { 2089 int i, j; 2090 struct dc_context *ctx = dc->ctx; 2091 struct irq_service_init_data init_data; 2092 struct ddc_service_init_data ddc_init_data = {0}; 2093 uint32_t pipe_fuses = 0; 2094 uint32_t num_pipes = 4; 2095 2096 #undef REG_STRUCT 2097 #define REG_STRUCT bios_regs 2098 bios_regs_init(); 2099 2100 #undef REG_STRUCT 2101 #define REG_STRUCT clk_src_regs 2102 clk_src_regs_init(0, A), 2103 clk_src_regs_init(1, B), 2104 clk_src_regs_init(2, C), 2105 clk_src_regs_init(3, D), 2106 clk_src_regs_init(4, E); 2107 #undef REG_STRUCT 2108 #define REG_STRUCT abm_regs 2109 abm_regs_init(0), 2110 abm_regs_init(1), 2111 abm_regs_init(2), 2112 abm_regs_init(3); 2113 2114 #undef REG_STRUCT 2115 #define REG_STRUCT dccg_regs 2116 dccg_regs_init(); 2117 2118 DC_FP_START(); 2119 2120 ctx->dc_bios->regs = &bios_regs; 2121 2122 pool->base.res_cap = &res_cap_dcn32; 2123 /* max number of pipes for ASIC before checking for pipe fuses */ 2124 num_pipes = pool->base.res_cap->num_timing_generator; 2125 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2126 2127 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2128 if (pipe_fuses & 1 << i) 2129 num_pipes--; 2130 2131 if (pipe_fuses & 1) 2132 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2133 2134 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2135 ASSERT(0); //Entire DCN is harvested! 2136 2137 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2138 * value will be changed, update max_num_dpp and max_num_otg for dml. 2139 */ 2140 dcn3_2_ip.max_num_dpp = num_pipes; 2141 dcn3_2_ip.max_num_otg = num_pipes; 2142 2143 pool->base.funcs = &dcn32_res_pool_funcs; 2144 2145 /************************************************* 2146 * Resource + asic cap harcoding * 2147 *************************************************/ 2148 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2149 pool->base.timing_generator_count = num_pipes; 2150 pool->base.pipe_count = num_pipes; 2151 pool->base.mpcc_count = num_pipes; 2152 dc->caps.max_downscale_ratio = 600; 2153 dc->caps.i2c_speed_in_khz = 100; 2154 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2155 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2156 dc->caps.max_cursor_size = 64; 2157 dc->caps.min_horizontal_blanking_period = 80; 2158 dc->caps.dmdata_alloc_size = 2048; 2159 dc->caps.mall_size_per_mem_channel = 4; 2160 dc->caps.mall_size_total = 0; 2161 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2162 2163 dc->caps.cache_line_size = 64; 2164 dc->caps.cache_num_ways = 16; 2165 2166 /* Calculate the available MALL space */ 2167 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2168 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2169 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2170 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2171 2172 dc->caps.subvp_fw_processing_delay_us = 15; 2173 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2174 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2175 dc->caps.subvp_swath_height_margin_lines = 16; 2176 dc->caps.subvp_pstate_allow_width_us = 20; 2177 dc->caps.subvp_vertical_int_margin_us = 30; 2178 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2179 2180 dc->caps.max_slave_planes = 2; 2181 dc->caps.max_slave_yuv_planes = 2; 2182 dc->caps.max_slave_rgb_planes = 2; 2183 dc->caps.post_blend_color_processing = true; 2184 dc->caps.force_dp_tps4_for_cp2520 = true; 2185 if (dc->config.forceHBR2CP2520) 2186 dc->caps.force_dp_tps4_for_cp2520 = false; 2187 dc->caps.dp_hpo = true; 2188 dc->caps.dp_hdmi21_pcon_support = true; 2189 dc->caps.edp_dsc_support = true; 2190 dc->caps.extended_aux_timeout_support = true; 2191 dc->caps.dmcub_support = true; 2192 dc->caps.seamless_odm = true; 2193 2194 /* Color pipeline capabilities */ 2195 dc->caps.color.dpp.dcn_arch = 1; 2196 dc->caps.color.dpp.input_lut_shared = 0; 2197 dc->caps.color.dpp.icsc = 1; 2198 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2199 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2200 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2201 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2202 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2203 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2204 dc->caps.color.dpp.post_csc = 1; 2205 dc->caps.color.dpp.gamma_corr = 1; 2206 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2207 2208 dc->caps.color.dpp.hw_3d_lut = 1; 2209 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2210 // no OGAM ROM on DCN2 and later ASICs 2211 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2212 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2213 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2214 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2215 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2216 dc->caps.color.dpp.ocsc = 0; 2217 2218 dc->caps.color.mpc.gamut_remap = 1; 2219 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2220 dc->caps.color.mpc.ogam_ram = 1; 2221 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2222 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2223 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2224 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2225 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2226 dc->caps.color.mpc.ocsc = 1; 2227 2228 /* Use pipe context based otg sync logic */ 2229 dc->config.use_pipe_ctx_sync_logic = true; 2230 2231 /* read VBIOS LTTPR caps */ 2232 { 2233 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2234 enum bp_result bp_query_result; 2235 uint8_t is_vbios_lttpr_enable = 0; 2236 2237 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2238 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2239 } 2240 2241 /* interop bit is implicit */ 2242 { 2243 dc->caps.vbios_lttpr_aware = true; 2244 } 2245 } 2246 2247 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2248 dc->debug = debug_defaults_drv; 2249 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2250 dc->debug = debug_defaults_diags; 2251 } else 2252 dc->debug = debug_defaults_diags; 2253 // Init the vm_helper 2254 if (dc->vm_helper) 2255 vm_helper_init(dc->vm_helper, 16); 2256 2257 /************************************************* 2258 * Create resources * 2259 *************************************************/ 2260 2261 /* Clock Sources for Pixel Clock*/ 2262 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2263 dcn32_clock_source_create(ctx, ctx->dc_bios, 2264 CLOCK_SOURCE_COMBO_PHY_PLL0, 2265 &clk_src_regs[0], false); 2266 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2267 dcn32_clock_source_create(ctx, ctx->dc_bios, 2268 CLOCK_SOURCE_COMBO_PHY_PLL1, 2269 &clk_src_regs[1], false); 2270 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2271 dcn32_clock_source_create(ctx, ctx->dc_bios, 2272 CLOCK_SOURCE_COMBO_PHY_PLL2, 2273 &clk_src_regs[2], false); 2274 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2275 dcn32_clock_source_create(ctx, ctx->dc_bios, 2276 CLOCK_SOURCE_COMBO_PHY_PLL3, 2277 &clk_src_regs[3], false); 2278 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2279 dcn32_clock_source_create(ctx, ctx->dc_bios, 2280 CLOCK_SOURCE_COMBO_PHY_PLL4, 2281 &clk_src_regs[4], false); 2282 2283 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2284 2285 /* todo: not reuse phy_pll registers */ 2286 pool->base.dp_clock_source = 2287 dcn32_clock_source_create(ctx, ctx->dc_bios, 2288 CLOCK_SOURCE_ID_DP_DTO, 2289 &clk_src_regs[0], true); 2290 2291 for (i = 0; i < pool->base.clk_src_count; i++) { 2292 if (pool->base.clock_sources[i] == NULL) { 2293 dm_error("DC: failed to create clock sources!\n"); 2294 BREAK_TO_DEBUGGER(); 2295 goto create_fail; 2296 } 2297 } 2298 2299 /* DCCG */ 2300 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2301 if (pool->base.dccg == NULL) { 2302 dm_error("DC: failed to create dccg!\n"); 2303 BREAK_TO_DEBUGGER(); 2304 goto create_fail; 2305 } 2306 2307 /* DML */ 2308 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2309 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2310 2311 /* IRQ Service */ 2312 init_data.ctx = dc->ctx; 2313 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2314 if (!pool->base.irqs) 2315 goto create_fail; 2316 2317 /* HUBBUB */ 2318 pool->base.hubbub = dcn32_hubbub_create(ctx); 2319 if (pool->base.hubbub == NULL) { 2320 BREAK_TO_DEBUGGER(); 2321 dm_error("DC: failed to create hubbub!\n"); 2322 goto create_fail; 2323 } 2324 2325 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2326 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2327 2328 /* if pipe is disabled, skip instance of HW pipe, 2329 * i.e, skip ASIC register instance 2330 */ 2331 if (pipe_fuses & 1 << i) 2332 continue; 2333 2334 /* HUBPs */ 2335 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2336 if (pool->base.hubps[j] == NULL) { 2337 BREAK_TO_DEBUGGER(); 2338 dm_error( 2339 "DC: failed to create hubps!\n"); 2340 goto create_fail; 2341 } 2342 2343 /* DPPs */ 2344 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2345 if (pool->base.dpps[j] == NULL) { 2346 BREAK_TO_DEBUGGER(); 2347 dm_error( 2348 "DC: failed to create dpps!\n"); 2349 goto create_fail; 2350 } 2351 2352 /* OPPs */ 2353 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2354 if (pool->base.opps[j] == NULL) { 2355 BREAK_TO_DEBUGGER(); 2356 dm_error( 2357 "DC: failed to create output pixel processor!\n"); 2358 goto create_fail; 2359 } 2360 2361 /* TGs */ 2362 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2363 ctx, i); 2364 if (pool->base.timing_generators[j] == NULL) { 2365 BREAK_TO_DEBUGGER(); 2366 dm_error("DC: failed to create tg!\n"); 2367 goto create_fail; 2368 } 2369 2370 /* ABMs */ 2371 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2372 &abm_regs[i], 2373 &abm_shift, 2374 &abm_mask); 2375 if (pool->base.multiple_abms[j] == NULL) { 2376 dm_error("DC: failed to create abm for pipe %d!\n", i); 2377 BREAK_TO_DEBUGGER(); 2378 goto create_fail; 2379 } 2380 2381 /* index for resource pool arrays for next valid pipe */ 2382 j++; 2383 } 2384 2385 /* PSR */ 2386 pool->base.psr = dmub_psr_create(ctx); 2387 if (pool->base.psr == NULL) { 2388 dm_error("DC: failed to create psr obj!\n"); 2389 BREAK_TO_DEBUGGER(); 2390 goto create_fail; 2391 } 2392 2393 /* MPCCs */ 2394 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2395 if (pool->base.mpc == NULL) { 2396 BREAK_TO_DEBUGGER(); 2397 dm_error("DC: failed to create mpc!\n"); 2398 goto create_fail; 2399 } 2400 2401 /* DSCs */ 2402 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2403 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2404 if (pool->base.dscs[i] == NULL) { 2405 BREAK_TO_DEBUGGER(); 2406 dm_error("DC: failed to create display stream compressor %d!\n", i); 2407 goto create_fail; 2408 } 2409 } 2410 2411 /* DWB */ 2412 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2413 BREAK_TO_DEBUGGER(); 2414 dm_error("DC: failed to create dwbc!\n"); 2415 goto create_fail; 2416 } 2417 2418 /* MMHUBBUB */ 2419 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2420 BREAK_TO_DEBUGGER(); 2421 dm_error("DC: failed to create mcif_wb!\n"); 2422 goto create_fail; 2423 } 2424 2425 /* AUX and I2C */ 2426 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2427 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2428 if (pool->base.engines[i] == NULL) { 2429 BREAK_TO_DEBUGGER(); 2430 dm_error( 2431 "DC:failed to create aux engine!!\n"); 2432 goto create_fail; 2433 } 2434 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2435 if (pool->base.hw_i2cs[i] == NULL) { 2436 BREAK_TO_DEBUGGER(); 2437 dm_error( 2438 "DC:failed to create hw i2c!!\n"); 2439 goto create_fail; 2440 } 2441 pool->base.sw_i2cs[i] = NULL; 2442 } 2443 2444 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2445 if (!resource_construct(num_virtual_links, dc, &pool->base, 2446 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2447 &res_create_funcs : &res_create_maximus_funcs))) 2448 goto create_fail; 2449 2450 /* HW Sequencer init functions and Plane caps */ 2451 dcn32_hw_sequencer_init_functions(dc); 2452 2453 dc->caps.max_planes = pool->base.pipe_count; 2454 2455 for (i = 0; i < dc->caps.max_planes; ++i) 2456 dc->caps.planes[i] = plane_cap; 2457 2458 dc->cap_funcs = cap_funcs; 2459 2460 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2461 ddc_init_data.ctx = dc->ctx; 2462 ddc_init_data.link = NULL; 2463 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2464 ddc_init_data.id.enum_id = 0; 2465 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2466 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2467 } else { 2468 pool->base.oem_device = NULL; 2469 } 2470 2471 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2472 dc->config.sdpif_request_limit_words_per_umc = 16; 2473 2474 DC_FP_END(); 2475 2476 return true; 2477 2478 create_fail: 2479 2480 DC_FP_END(); 2481 2482 dcn32_resource_destruct(pool); 2483 2484 return false; 2485 } 2486 2487 struct resource_pool *dcn32_create_resource_pool( 2488 const struct dc_init_data *init_data, 2489 struct dc *dc) 2490 { 2491 struct dcn32_resource_pool *pool = 2492 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2493 2494 if (!pool) 2495 return NULL; 2496 2497 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2498 return &pool->base; 2499 2500 BREAK_TO_DEBUGGER(); 2501 kfree(pool); 2502 return NULL; 2503 } 2504 2505 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2506 struct resource_context *res_ctx, 2507 const struct resource_pool *pool, 2508 const struct pipe_ctx *primary_pipe) 2509 { 2510 int i; 2511 struct pipe_ctx *secondary_pipe = NULL; 2512 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2513 int primary_index, preferred_pipe_idx; 2514 struct pipe_ctx *old_primary_pipe = NULL; 2515 2516 /* 2517 * Modified from find_idle_secondary_pipe 2518 * With windowed MPO and ODM, we want to avoid the case where we want a 2519 * free pipe for the left side but the free pipe is being used on the 2520 * right side. 2521 * Add check on current_state if the primary_pipe is the left side, 2522 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2523 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2524 * - If so, then don't use this pipe 2525 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2526 * - in this case, the primary pipe has already gotten a free pipe for the 2527 * MPO window in the left 2528 * - when it tries to get a free pipe for the MPO window on the right, 2529 * it will see that it is already assigned to the right side 2530 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2531 * free pipe, since it will be for the right side. So add an 2532 * additional condition, that skipping the free pipe on the right only 2533 * applies if the primary pipe has no bottom pipe currently assigned 2534 */ 2535 if (primary_pipe) { 2536 primary_index = primary_pipe->pipe_idx; 2537 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2538 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2539 && (!primary_pipe->bottom_pipe)) 2540 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2541 2542 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2543 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2544 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2545 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2546 secondary_pipe->pipe_idx = preferred_pipe_idx; 2547 } 2548 } 2549 2550 /* 2551 * search backwards for the second pipe to keep pipe 2552 * assignment more consistent 2553 */ 2554 if (!secondary_pipe) 2555 for (i = pool->pipe_count - 1; i >= 0; i--) { 2556 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2557 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2558 secondary_pipe = &res_ctx->pipe_ctx[i]; 2559 secondary_pipe->pipe_idx = i; 2560 break; 2561 } 2562 } 2563 2564 return secondary_pipe; 2565 } 2566 2567 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2568 struct dc_state *state, 2569 const struct resource_pool *pool, 2570 struct dc_stream_state *stream, 2571 struct pipe_ctx *head_pipe) 2572 { 2573 struct resource_context *res_ctx = &state->res_ctx; 2574 struct pipe_ctx *idle_pipe, *pipe; 2575 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2576 int head_index; 2577 2578 if (!head_pipe) 2579 ASSERT(0); 2580 2581 /* 2582 * Modified from dcn20_acquire_idle_pipe_for_layer 2583 * Check if head_pipe in old_context already has bottom_pipe allocated. 2584 * - If so, check if that pipe is available in the current context. 2585 * -- If so, reuse pipe from old_context 2586 */ 2587 head_index = head_pipe->pipe_idx; 2588 pipe = &old_ctx->pipe_ctx[head_index]; 2589 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2590 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2591 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2592 } else { 2593 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2594 if (!idle_pipe) 2595 return NULL; 2596 } 2597 2598 idle_pipe->stream = head_pipe->stream; 2599 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2600 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2601 2602 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2603 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2604 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2605 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2606 2607 return idle_pipe; 2608 } 2609 2610 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2611 { 2612 /* 2613 * DCN32 and DCN321 SKUs may have different sizes for MALL 2614 * but we may not be able to access all the MALL space. 2615 * If the num_chans is power of 2, then we can access all 2616 * of the available MALL space. Otherwise, we can only 2617 * access: 2618 * 2619 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2620 * ((2^floor(log2(num_chans)))/num_chans) 2621 * 2622 * Calculating the MALL sizes for all available SKUs, we 2623 * have come up with the follow simplified check. 2624 * - we have max_chans which provides the max MALL size. 2625 * Each chans supports 4MB of MALL so: 2626 * 2627 * total_cache_size_in_bytes = max_chans * 4 MB 2628 * 2629 * - we have avail_chans which shows the number of channels 2630 * we can use if we can't access the entire MALL space. 2631 * It is generally half of max_chans 2632 * - so we use the following checks: 2633 * 2634 * if (num_chans == max_chans), return max_chans 2635 * if (num_chans < max_chans), return avail_chans 2636 * 2637 * - exception is GC_11_0_0 where we can't access max_chans, 2638 * so we define max_avail_chans as the maximum available 2639 * MALL space 2640 * 2641 */ 2642 int gc_11_0_0_max_chans = 48; 2643 int gc_11_0_0_max_avail_chans = 32; 2644 int gc_11_0_0_avail_chans = 16; 2645 int gc_11_0_3_max_chans = 16; 2646 int gc_11_0_3_avail_chans = 8; 2647 int gc_11_0_2_max_chans = 8; 2648 int gc_11_0_2_avail_chans = 4; 2649 2650 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2651 return (num_chans == gc_11_0_0_max_chans) ? 2652 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2653 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2654 return (num_chans == gc_11_0_2_max_chans) ? 2655 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2656 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2657 return (num_chans == gc_11_0_3_max_chans) ? 2658 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2659 } 2660 } 2661