1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dc_link_dp.h" 61 #include "dcn31/dcn31_apg.h" 62 #include "dcn31/dcn31_dio_link_encoder.h" 63 #include "dcn32/dcn32_dio_link_encoder.h" 64 #include "dce/dce_clock_source.h" 65 #include "dce/dce_audio.h" 66 #include "dce/dce_hwseq.h" 67 #include "clk_mgr.h" 68 #include "virtual/virtual_stream_encoder.h" 69 #include "dml/display_mode_vba.h" 70 #include "dcn32/dcn32_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dc_link_ddc.h" 73 #include "dcn31/dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn32/dcn32_mmhubbub.h" 77 78 #include "dcn/dcn_3_2_0_offset.h" 79 #include "dcn/dcn_3_2_0_sh_mask.h" 80 #include "nbio/nbio_4_3_0_offset.h" 81 82 #include "reg_helper.h" 83 #include "dce/dmub_abm.h" 84 #include "dce/dmub_psr.h" 85 #include "dce/dce_aux.h" 86 #include "dce/dce_i2c.h" 87 88 #include "dml/dcn30/display_mode_vba_30.h" 89 #include "vm_helper.h" 90 #include "dcn20/dcn20_vmid.h" 91 #include "dml/dcn32/dcn32_fpu.h" 92 93 #define DC_LOGGER_INIT(logger) 94 95 enum dcn32_clk_src_array_id { 96 DCN32_CLK_SRC_PLL0, 97 DCN32_CLK_SRC_PLL1, 98 DCN32_CLK_SRC_PLL2, 99 DCN32_CLK_SRC_PLL3, 100 DCN32_CLK_SRC_PLL4, 101 DCN32_CLK_SRC_TOTAL 102 }; 103 104 /* begin ********************* 105 * macros to expend register list macro defined in HW object header file 106 */ 107 108 /* DCN */ 109 /* TODO awful hack. fixup dcn20_dwb.h */ 110 #undef BASE_INNER 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id) \ 119 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 120 121 #define SR_ARR_INIT(reg_name, id, value) \ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 722 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 723 .enable_double_buffered_dsc_pg_support = true, 724 .enable_dp_dig_pixel_rate_div_policy = 1, 725 .allow_sw_cursor_fallback = false, 726 .alloc_extra_way_for_cursor = true, 727 }; 728 729 static const struct dc_debug_options debug_defaults_diags = { 730 .disable_dmcu = true, 731 .force_abm_enable = false, 732 .timing_trace = true, 733 .clock_trace = true, 734 .disable_dpp_power_gate = true, 735 .disable_hubp_power_gate = true, 736 .disable_dsc_power_gate = true, 737 .disable_clock_gate = true, 738 .disable_pplib_clock_request = true, 739 .disable_pplib_wm_range = true, 740 .disable_stutter = false, 741 .scl_reset_length10 = true, 742 .dwb_fi_phase = -1, // -1 = disable 743 .dmub_command_table = true, 744 .enable_tri_buf = true, 745 .use_max_lb = true, 746 .force_disable_subvp = true 747 }; 748 749 static struct dce_aux *dcn32_aux_engine_create( 750 struct dc_context *ctx, 751 uint32_t inst) 752 { 753 struct aux_engine_dce110 *aux_engine = 754 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 755 756 if (!aux_engine) 757 return NULL; 758 759 #undef REG_STRUCT 760 #define REG_STRUCT aux_engine_regs 761 aux_engine_regs_init(0), 762 aux_engine_regs_init(1), 763 aux_engine_regs_init(2), 764 aux_engine_regs_init(3), 765 aux_engine_regs_init(4); 766 767 dce110_aux_engine_construct(aux_engine, ctx, inst, 768 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 769 &aux_engine_regs[inst], 770 &aux_mask, 771 &aux_shift, 772 ctx->dc->caps.extended_aux_timeout_support); 773 774 return &aux_engine->base; 775 } 776 #define i2c_inst_regs_init(id)\ 777 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 778 779 static struct dce_i2c_registers i2c_hw_regs[5]; 780 781 static const struct dce_i2c_shift i2c_shifts = { 782 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 783 }; 784 785 static const struct dce_i2c_mask i2c_masks = { 786 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 787 }; 788 789 static struct dce_i2c_hw *dcn32_i2c_hw_create( 790 struct dc_context *ctx, 791 uint32_t inst) 792 { 793 struct dce_i2c_hw *dce_i2c_hw = 794 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 795 796 if (!dce_i2c_hw) 797 return NULL; 798 799 #undef REG_STRUCT 800 #define REG_STRUCT i2c_hw_regs 801 i2c_inst_regs_init(1), 802 i2c_inst_regs_init(2), 803 i2c_inst_regs_init(3), 804 i2c_inst_regs_init(4), 805 i2c_inst_regs_init(5); 806 807 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 808 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 809 810 return dce_i2c_hw; 811 } 812 813 static struct clock_source *dcn32_clock_source_create( 814 struct dc_context *ctx, 815 struct dc_bios *bios, 816 enum clock_source_id id, 817 const struct dce110_clk_src_regs *regs, 818 bool dp_clk_src) 819 { 820 struct dce110_clk_src *clk_src = 821 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 822 823 if (!clk_src) 824 return NULL; 825 826 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 827 regs, &cs_shift, &cs_mask)) { 828 clk_src->base.dp_clk_src = dp_clk_src; 829 return &clk_src->base; 830 } 831 832 BREAK_TO_DEBUGGER(); 833 return NULL; 834 } 835 836 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 837 { 838 int i; 839 840 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 841 GFP_KERNEL); 842 843 if (!hubbub2) 844 return NULL; 845 846 #undef REG_STRUCT 847 #define REG_STRUCT hubbub_reg 848 hubbub_reg_init(); 849 850 #undef REG_STRUCT 851 #define REG_STRUCT vmid_regs 852 vmid_regs_init(0), 853 vmid_regs_init(1), 854 vmid_regs_init(2), 855 vmid_regs_init(3), 856 vmid_regs_init(4), 857 vmid_regs_init(5), 858 vmid_regs_init(6), 859 vmid_regs_init(7), 860 vmid_regs_init(8), 861 vmid_regs_init(9), 862 vmid_regs_init(10), 863 vmid_regs_init(11), 864 vmid_regs_init(12), 865 vmid_regs_init(13), 866 vmid_regs_init(14), 867 vmid_regs_init(15); 868 869 hubbub32_construct(hubbub2, ctx, 870 &hubbub_reg, 871 &hubbub_shift, 872 &hubbub_mask, 873 ctx->dc->dml.ip.det_buffer_size_kbytes, 874 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 875 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 876 877 878 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 879 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 880 881 vmid->ctx = ctx; 882 883 vmid->regs = &vmid_regs[i]; 884 vmid->shifts = &vmid_shifts; 885 vmid->masks = &vmid_masks; 886 } 887 888 return &hubbub2->base; 889 } 890 891 static struct hubp *dcn32_hubp_create( 892 struct dc_context *ctx, 893 uint32_t inst) 894 { 895 struct dcn20_hubp *hubp2 = 896 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 897 898 if (!hubp2) 899 return NULL; 900 901 #undef REG_STRUCT 902 #define REG_STRUCT hubp_regs 903 hubp_regs_init(0), 904 hubp_regs_init(1), 905 hubp_regs_init(2), 906 hubp_regs_init(3); 907 908 if (hubp32_construct(hubp2, ctx, inst, 909 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 910 return &hubp2->base; 911 912 BREAK_TO_DEBUGGER(); 913 kfree(hubp2); 914 return NULL; 915 } 916 917 static void dcn32_dpp_destroy(struct dpp **dpp) 918 { 919 kfree(TO_DCN30_DPP(*dpp)); 920 *dpp = NULL; 921 } 922 923 static struct dpp *dcn32_dpp_create( 924 struct dc_context *ctx, 925 uint32_t inst) 926 { 927 struct dcn3_dpp *dpp3 = 928 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 929 930 if (!dpp3) 931 return NULL; 932 933 #undef REG_STRUCT 934 #define REG_STRUCT dpp_regs 935 dpp_regs_init(0), 936 dpp_regs_init(1), 937 dpp_regs_init(2), 938 dpp_regs_init(3); 939 940 if (dpp32_construct(dpp3, ctx, inst, 941 &dpp_regs[inst], &tf_shift, &tf_mask)) 942 return &dpp3->base; 943 944 BREAK_TO_DEBUGGER(); 945 kfree(dpp3); 946 return NULL; 947 } 948 949 static struct mpc *dcn32_mpc_create( 950 struct dc_context *ctx, 951 int num_mpcc, 952 int num_rmu) 953 { 954 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 955 GFP_KERNEL); 956 957 if (!mpc30) 958 return NULL; 959 960 #undef REG_STRUCT 961 #define REG_STRUCT mpc_regs 962 dcn_mpc_regs_init(); 963 964 dcn32_mpc_construct(mpc30, ctx, 965 &mpc_regs, 966 &mpc_shift, 967 &mpc_mask, 968 num_mpcc, 969 num_rmu); 970 971 return &mpc30->base; 972 } 973 974 static struct output_pixel_processor *dcn32_opp_create( 975 struct dc_context *ctx, uint32_t inst) 976 { 977 struct dcn20_opp *opp2 = 978 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 979 980 if (!opp2) { 981 BREAK_TO_DEBUGGER(); 982 return NULL; 983 } 984 985 #undef REG_STRUCT 986 #define REG_STRUCT opp_regs 987 opp_regs_init(0), 988 opp_regs_init(1), 989 opp_regs_init(2), 990 opp_regs_init(3); 991 992 dcn20_opp_construct(opp2, ctx, inst, 993 &opp_regs[inst], &opp_shift, &opp_mask); 994 return &opp2->base; 995 } 996 997 998 static struct timing_generator *dcn32_timing_generator_create( 999 struct dc_context *ctx, 1000 uint32_t instance) 1001 { 1002 struct optc *tgn10 = 1003 kzalloc(sizeof(struct optc), GFP_KERNEL); 1004 1005 if (!tgn10) 1006 return NULL; 1007 1008 #undef REG_STRUCT 1009 #define REG_STRUCT optc_regs 1010 optc_regs_init(0), 1011 optc_regs_init(1), 1012 optc_regs_init(2), 1013 optc_regs_init(3); 1014 1015 tgn10->base.inst = instance; 1016 tgn10->base.ctx = ctx; 1017 1018 tgn10->tg_regs = &optc_regs[instance]; 1019 tgn10->tg_shift = &optc_shift; 1020 tgn10->tg_mask = &optc_mask; 1021 1022 dcn32_timing_generator_init(tgn10); 1023 1024 return &tgn10->base; 1025 } 1026 1027 static const struct encoder_feature_support link_enc_feature = { 1028 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1029 .max_hdmi_pixel_clock = 600000, 1030 .hdmi_ycbcr420_supported = true, 1031 .dp_ycbcr420_supported = true, 1032 .fec_supported = true, 1033 .flags.bits.IS_HBR2_CAPABLE = true, 1034 .flags.bits.IS_HBR3_CAPABLE = true, 1035 .flags.bits.IS_TPS3_CAPABLE = true, 1036 .flags.bits.IS_TPS4_CAPABLE = true 1037 }; 1038 1039 static struct link_encoder *dcn32_link_encoder_create( 1040 struct dc_context *ctx, 1041 const struct encoder_init_data *enc_init_data) 1042 { 1043 struct dcn20_link_encoder *enc20 = 1044 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1045 1046 if (!enc20) 1047 return NULL; 1048 1049 #undef REG_STRUCT 1050 #define REG_STRUCT link_enc_aux_regs 1051 aux_regs_init(0), 1052 aux_regs_init(1), 1053 aux_regs_init(2), 1054 aux_regs_init(3), 1055 aux_regs_init(4); 1056 1057 #undef REG_STRUCT 1058 #define REG_STRUCT link_enc_hpd_regs 1059 hpd_regs_init(0), 1060 hpd_regs_init(1), 1061 hpd_regs_init(2), 1062 hpd_regs_init(3), 1063 hpd_regs_init(4); 1064 1065 #undef REG_STRUCT 1066 #define REG_STRUCT link_enc_regs 1067 link_regs_init(0, A), 1068 link_regs_init(1, B), 1069 link_regs_init(2, C), 1070 link_regs_init(3, D), 1071 link_regs_init(4, E); 1072 1073 dcn32_link_encoder_construct(enc20, 1074 enc_init_data, 1075 &link_enc_feature, 1076 &link_enc_regs[enc_init_data->transmitter], 1077 &link_enc_aux_regs[enc_init_data->channel - 1], 1078 &link_enc_hpd_regs[enc_init_data->hpd_source], 1079 &le_shift, 1080 &le_mask); 1081 1082 return &enc20->enc10.base; 1083 } 1084 1085 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1086 { 1087 struct dcn31_panel_cntl *panel_cntl = 1088 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1089 1090 if (!panel_cntl) 1091 return NULL; 1092 1093 dcn31_panel_cntl_construct(panel_cntl, init_data); 1094 1095 return &panel_cntl->base; 1096 } 1097 1098 static void read_dce_straps( 1099 struct dc_context *ctx, 1100 struct resource_straps *straps) 1101 { 1102 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1103 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1104 1105 } 1106 1107 static struct audio *dcn32_create_audio( 1108 struct dc_context *ctx, unsigned int inst) 1109 { 1110 1111 #undef REG_STRUCT 1112 #define REG_STRUCT audio_regs 1113 audio_regs_init(0), 1114 audio_regs_init(1), 1115 audio_regs_init(2), 1116 audio_regs_init(3), 1117 audio_regs_init(4); 1118 1119 return dce_audio_create(ctx, inst, 1120 &audio_regs[inst], &audio_shift, &audio_mask); 1121 } 1122 1123 static struct vpg *dcn32_vpg_create( 1124 struct dc_context *ctx, 1125 uint32_t inst) 1126 { 1127 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1128 1129 if (!vpg3) 1130 return NULL; 1131 1132 #undef REG_STRUCT 1133 #define REG_STRUCT vpg_regs 1134 vpg_regs_init(0), 1135 vpg_regs_init(1), 1136 vpg_regs_init(2), 1137 vpg_regs_init(3), 1138 vpg_regs_init(4), 1139 vpg_regs_init(5), 1140 vpg_regs_init(6), 1141 vpg_regs_init(7), 1142 vpg_regs_init(8), 1143 vpg_regs_init(9); 1144 1145 vpg3_construct(vpg3, ctx, inst, 1146 &vpg_regs[inst], 1147 &vpg_shift, 1148 &vpg_mask); 1149 1150 return &vpg3->base; 1151 } 1152 1153 static struct afmt *dcn32_afmt_create( 1154 struct dc_context *ctx, 1155 uint32_t inst) 1156 { 1157 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1158 1159 if (!afmt3) 1160 return NULL; 1161 1162 #undef REG_STRUCT 1163 #define REG_STRUCT afmt_regs 1164 afmt_regs_init(0), 1165 afmt_regs_init(1), 1166 afmt_regs_init(2), 1167 afmt_regs_init(3), 1168 afmt_regs_init(4), 1169 afmt_regs_init(5); 1170 1171 afmt3_construct(afmt3, ctx, inst, 1172 &afmt_regs[inst], 1173 &afmt_shift, 1174 &afmt_mask); 1175 1176 return &afmt3->base; 1177 } 1178 1179 static struct apg *dcn31_apg_create( 1180 struct dc_context *ctx, 1181 uint32_t inst) 1182 { 1183 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1184 1185 if (!apg31) 1186 return NULL; 1187 1188 #undef REG_STRUCT 1189 #define REG_STRUCT apg_regs 1190 apg_regs_init(0), 1191 apg_regs_init(1), 1192 apg_regs_init(2), 1193 apg_regs_init(3); 1194 1195 apg31_construct(apg31, ctx, inst, 1196 &apg_regs[inst], 1197 &apg_shift, 1198 &apg_mask); 1199 1200 return &apg31->base; 1201 } 1202 1203 static struct stream_encoder *dcn32_stream_encoder_create( 1204 enum engine_id eng_id, 1205 struct dc_context *ctx) 1206 { 1207 struct dcn10_stream_encoder *enc1; 1208 struct vpg *vpg; 1209 struct afmt *afmt; 1210 int vpg_inst; 1211 int afmt_inst; 1212 1213 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1214 if (eng_id <= ENGINE_ID_DIGF) { 1215 vpg_inst = eng_id; 1216 afmt_inst = eng_id; 1217 } else 1218 return NULL; 1219 1220 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1221 vpg = dcn32_vpg_create(ctx, vpg_inst); 1222 afmt = dcn32_afmt_create(ctx, afmt_inst); 1223 1224 if (!enc1 || !vpg || !afmt) { 1225 kfree(enc1); 1226 kfree(vpg); 1227 kfree(afmt); 1228 return NULL; 1229 } 1230 1231 #undef REG_STRUCT 1232 #define REG_STRUCT stream_enc_regs 1233 stream_enc_regs_init(0), 1234 stream_enc_regs_init(1), 1235 stream_enc_regs_init(2), 1236 stream_enc_regs_init(3), 1237 stream_enc_regs_init(4); 1238 1239 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1240 eng_id, vpg, afmt, 1241 &stream_enc_regs[eng_id], 1242 &se_shift, &se_mask); 1243 1244 return &enc1->base; 1245 } 1246 1247 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1248 enum engine_id eng_id, 1249 struct dc_context *ctx) 1250 { 1251 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1252 struct vpg *vpg; 1253 struct apg *apg; 1254 uint32_t hpo_dp_inst; 1255 uint32_t vpg_inst; 1256 uint32_t apg_inst; 1257 1258 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1259 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1260 1261 /* Mapping of VPG register blocks to HPO DP block instance: 1262 * VPG[6] -> HPO_DP[0] 1263 * VPG[7] -> HPO_DP[1] 1264 * VPG[8] -> HPO_DP[2] 1265 * VPG[9] -> HPO_DP[3] 1266 */ 1267 vpg_inst = hpo_dp_inst + 6; 1268 1269 /* Mapping of APG register blocks to HPO DP block instance: 1270 * APG[0] -> HPO_DP[0] 1271 * APG[1] -> HPO_DP[1] 1272 * APG[2] -> HPO_DP[2] 1273 * APG[3] -> HPO_DP[3] 1274 */ 1275 apg_inst = hpo_dp_inst; 1276 1277 /* allocate HPO stream encoder and create VPG sub-block */ 1278 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1279 vpg = dcn32_vpg_create(ctx, vpg_inst); 1280 apg = dcn31_apg_create(ctx, apg_inst); 1281 1282 if (!hpo_dp_enc31 || !vpg || !apg) { 1283 kfree(hpo_dp_enc31); 1284 kfree(vpg); 1285 kfree(apg); 1286 return NULL; 1287 } 1288 1289 #undef REG_STRUCT 1290 #define REG_STRUCT hpo_dp_stream_enc_regs 1291 hpo_dp_stream_encoder_reg_init(0), 1292 hpo_dp_stream_encoder_reg_init(1), 1293 hpo_dp_stream_encoder_reg_init(2), 1294 hpo_dp_stream_encoder_reg_init(3); 1295 1296 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1297 hpo_dp_inst, eng_id, vpg, apg, 1298 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1299 &hpo_dp_se_shift, &hpo_dp_se_mask); 1300 1301 return &hpo_dp_enc31->base; 1302 } 1303 1304 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1305 uint8_t inst, 1306 struct dc_context *ctx) 1307 { 1308 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1309 1310 /* allocate HPO link encoder */ 1311 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1312 1313 #undef REG_STRUCT 1314 #define REG_STRUCT hpo_dp_link_enc_regs 1315 hpo_dp_link_encoder_reg_init(0), 1316 hpo_dp_link_encoder_reg_init(1); 1317 1318 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1319 &hpo_dp_link_enc_regs[inst], 1320 &hpo_dp_le_shift, &hpo_dp_le_mask); 1321 1322 return &hpo_dp_enc31->base; 1323 } 1324 1325 static struct dce_hwseq *dcn32_hwseq_create( 1326 struct dc_context *ctx) 1327 { 1328 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1329 1330 #undef REG_STRUCT 1331 #define REG_STRUCT hwseq_reg 1332 hwseq_reg_init(); 1333 1334 if (hws) { 1335 hws->ctx = ctx; 1336 hws->regs = &hwseq_reg; 1337 hws->shifts = &hwseq_shift; 1338 hws->masks = &hwseq_mask; 1339 } 1340 return hws; 1341 } 1342 static const struct resource_create_funcs res_create_funcs = { 1343 .read_dce_straps = read_dce_straps, 1344 .create_audio = dcn32_create_audio, 1345 .create_stream_encoder = dcn32_stream_encoder_create, 1346 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1347 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1348 .create_hwseq = dcn32_hwseq_create, 1349 }; 1350 1351 static const struct resource_create_funcs res_create_maximus_funcs = { 1352 .read_dce_straps = NULL, 1353 .create_audio = NULL, 1354 .create_stream_encoder = NULL, 1355 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1356 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1357 .create_hwseq = dcn32_hwseq_create, 1358 }; 1359 1360 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1361 { 1362 unsigned int i; 1363 1364 for (i = 0; i < pool->base.stream_enc_count; i++) { 1365 if (pool->base.stream_enc[i] != NULL) { 1366 if (pool->base.stream_enc[i]->vpg != NULL) { 1367 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1368 pool->base.stream_enc[i]->vpg = NULL; 1369 } 1370 if (pool->base.stream_enc[i]->afmt != NULL) { 1371 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1372 pool->base.stream_enc[i]->afmt = NULL; 1373 } 1374 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1375 pool->base.stream_enc[i] = NULL; 1376 } 1377 } 1378 1379 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1380 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1381 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1382 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1383 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1384 } 1385 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1386 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1387 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1388 } 1389 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1390 pool->base.hpo_dp_stream_enc[i] = NULL; 1391 } 1392 } 1393 1394 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1395 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1396 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1397 pool->base.hpo_dp_link_enc[i] = NULL; 1398 } 1399 } 1400 1401 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1402 if (pool->base.dscs[i] != NULL) 1403 dcn20_dsc_destroy(&pool->base.dscs[i]); 1404 } 1405 1406 if (pool->base.mpc != NULL) { 1407 kfree(TO_DCN20_MPC(pool->base.mpc)); 1408 pool->base.mpc = NULL; 1409 } 1410 if (pool->base.hubbub != NULL) { 1411 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1412 pool->base.hubbub = NULL; 1413 } 1414 for (i = 0; i < pool->base.pipe_count; i++) { 1415 if (pool->base.dpps[i] != NULL) 1416 dcn32_dpp_destroy(&pool->base.dpps[i]); 1417 1418 if (pool->base.ipps[i] != NULL) 1419 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1420 1421 if (pool->base.hubps[i] != NULL) { 1422 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1423 pool->base.hubps[i] = NULL; 1424 } 1425 1426 if (pool->base.irqs != NULL) { 1427 dal_irq_service_destroy(&pool->base.irqs); 1428 } 1429 } 1430 1431 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1432 if (pool->base.engines[i] != NULL) 1433 dce110_engine_destroy(&pool->base.engines[i]); 1434 if (pool->base.hw_i2cs[i] != NULL) { 1435 kfree(pool->base.hw_i2cs[i]); 1436 pool->base.hw_i2cs[i] = NULL; 1437 } 1438 if (pool->base.sw_i2cs[i] != NULL) { 1439 kfree(pool->base.sw_i2cs[i]); 1440 pool->base.sw_i2cs[i] = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1445 if (pool->base.opps[i] != NULL) 1446 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1447 } 1448 1449 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1450 if (pool->base.timing_generators[i] != NULL) { 1451 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1452 pool->base.timing_generators[i] = NULL; 1453 } 1454 } 1455 1456 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1457 if (pool->base.dwbc[i] != NULL) { 1458 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1459 pool->base.dwbc[i] = NULL; 1460 } 1461 if (pool->base.mcif_wb[i] != NULL) { 1462 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1463 pool->base.mcif_wb[i] = NULL; 1464 } 1465 } 1466 1467 for (i = 0; i < pool->base.audio_count; i++) { 1468 if (pool->base.audios[i]) 1469 dce_aud_destroy(&pool->base.audios[i]); 1470 } 1471 1472 for (i = 0; i < pool->base.clk_src_count; i++) { 1473 if (pool->base.clock_sources[i] != NULL) { 1474 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1475 pool->base.clock_sources[i] = NULL; 1476 } 1477 } 1478 1479 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1480 if (pool->base.mpc_lut[i] != NULL) { 1481 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1482 pool->base.mpc_lut[i] = NULL; 1483 } 1484 if (pool->base.mpc_shaper[i] != NULL) { 1485 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1486 pool->base.mpc_shaper[i] = NULL; 1487 } 1488 } 1489 1490 if (pool->base.dp_clock_source != NULL) { 1491 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1492 pool->base.dp_clock_source = NULL; 1493 } 1494 1495 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1496 if (pool->base.multiple_abms[i] != NULL) 1497 dce_abm_destroy(&pool->base.multiple_abms[i]); 1498 } 1499 1500 if (pool->base.psr != NULL) 1501 dmub_psr_destroy(&pool->base.psr); 1502 1503 if (pool->base.dccg != NULL) 1504 dcn_dccg_destroy(&pool->base.dccg); 1505 1506 if (pool->base.oem_device != NULL) 1507 dal_ddc_service_destroy(&pool->base.oem_device); 1508 } 1509 1510 1511 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1512 { 1513 int i; 1514 uint32_t dwb_count = pool->res_cap->num_dwb; 1515 1516 for (i = 0; i < dwb_count; i++) { 1517 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1518 GFP_KERNEL); 1519 1520 if (!dwbc30) { 1521 dm_error("DC: failed to create dwbc30!\n"); 1522 return false; 1523 } 1524 1525 #undef REG_STRUCT 1526 #define REG_STRUCT dwbc30_regs 1527 dwbc_regs_dcn3_init(0); 1528 1529 dcn30_dwbc_construct(dwbc30, ctx, 1530 &dwbc30_regs[i], 1531 &dwbc30_shift, 1532 &dwbc30_mask, 1533 i); 1534 1535 pool->dwbc[i] = &dwbc30->base; 1536 } 1537 return true; 1538 } 1539 1540 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1541 { 1542 int i; 1543 uint32_t dwb_count = pool->res_cap->num_dwb; 1544 1545 for (i = 0; i < dwb_count; i++) { 1546 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1547 GFP_KERNEL); 1548 1549 if (!mcif_wb30) { 1550 dm_error("DC: failed to create mcif_wb30!\n"); 1551 return false; 1552 } 1553 1554 #undef REG_STRUCT 1555 #define REG_STRUCT mcif_wb30_regs 1556 mcif_wb_regs_dcn3_init(0); 1557 1558 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1559 &mcif_wb30_regs[i], 1560 &mcif_wb30_shift, 1561 &mcif_wb30_mask, 1562 i); 1563 1564 pool->mcif_wb[i] = &mcif_wb30->base; 1565 } 1566 return true; 1567 } 1568 1569 static struct display_stream_compressor *dcn32_dsc_create( 1570 struct dc_context *ctx, uint32_t inst) 1571 { 1572 struct dcn20_dsc *dsc = 1573 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1574 1575 if (!dsc) { 1576 BREAK_TO_DEBUGGER(); 1577 return NULL; 1578 } 1579 1580 #undef REG_STRUCT 1581 #define REG_STRUCT dsc_regs 1582 dsc_regsDCN20_init(0), 1583 dsc_regsDCN20_init(1), 1584 dsc_regsDCN20_init(2), 1585 dsc_regsDCN20_init(3); 1586 1587 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1588 1589 dsc->max_image_width = 6016; 1590 1591 return &dsc->base; 1592 } 1593 1594 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1595 { 1596 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1597 1598 dcn32_resource_destruct(dcn32_pool); 1599 kfree(dcn32_pool); 1600 *pool = NULL; 1601 } 1602 1603 bool dcn32_acquire_post_bldn_3dlut( 1604 struct resource_context *res_ctx, 1605 const struct resource_pool *pool, 1606 int mpcc_id, 1607 struct dc_3dlut **lut, 1608 struct dc_transfer_func **shaper) 1609 { 1610 bool ret = false; 1611 union dc_3dlut_state *state; 1612 1613 ASSERT(*lut == NULL && *shaper == NULL); 1614 *lut = NULL; 1615 *shaper = NULL; 1616 1617 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1618 *lut = pool->mpc_lut[mpcc_id]; 1619 *shaper = pool->mpc_shaper[mpcc_id]; 1620 state = &pool->mpc_lut[mpcc_id]->state; 1621 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1622 ret = true; 1623 } 1624 return ret; 1625 } 1626 1627 bool dcn32_release_post_bldn_3dlut( 1628 struct resource_context *res_ctx, 1629 const struct resource_pool *pool, 1630 struct dc_3dlut **lut, 1631 struct dc_transfer_func **shaper) 1632 { 1633 int i; 1634 bool ret = false; 1635 1636 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1637 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1638 res_ctx->is_mpc_3dlut_acquired[i] = false; 1639 pool->mpc_lut[i]->state.raw = 0; 1640 *lut = NULL; 1641 *shaper = NULL; 1642 ret = true; 1643 break; 1644 } 1645 } 1646 return ret; 1647 } 1648 1649 static void dcn32_enable_phantom_plane(struct dc *dc, 1650 struct dc_state *context, 1651 struct dc_stream_state *phantom_stream, 1652 unsigned int dc_pipe_idx) 1653 { 1654 struct dc_plane_state *phantom_plane = NULL; 1655 struct dc_plane_state *prev_phantom_plane = NULL; 1656 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1657 1658 while (curr_pipe) { 1659 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1660 phantom_plane = prev_phantom_plane; 1661 else 1662 phantom_plane = dc_create_plane_state(dc); 1663 1664 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1665 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1666 sizeof(phantom_plane->scaling_quality)); 1667 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1668 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1669 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1670 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1671 sizeof(phantom_plane->plane_size)); 1672 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1673 sizeof(phantom_plane->tiling_info)); 1674 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1675 phantom_plane->format = curr_pipe->plane_state->format; 1676 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1677 phantom_plane->visible = curr_pipe->plane_state->visible; 1678 1679 /* Shadow pipe has small viewport. */ 1680 phantom_plane->clip_rect.y = 0; 1681 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; 1682 1683 phantom_plane->is_phantom = true; 1684 1685 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1686 1687 curr_pipe = curr_pipe->bottom_pipe; 1688 prev_phantom_plane = phantom_plane; 1689 } 1690 } 1691 1692 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1693 struct dc_state *context, 1694 display_e2e_pipe_params_st *pipes, 1695 unsigned int pipe_cnt, 1696 unsigned int dc_pipe_idx) 1697 { 1698 struct dc_stream_state *phantom_stream = NULL; 1699 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1700 1701 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1702 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1703 phantom_stream->dpms_off = true; 1704 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1705 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1706 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1707 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1708 1709 /* stream has limited viewport and small timing */ 1710 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1711 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1712 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1713 DC_FP_START(); 1714 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1715 DC_FP_END(); 1716 1717 dc_add_stream_to_ctx(dc, context, phantom_stream); 1718 return phantom_stream; 1719 } 1720 1721 // return true if removed piped from ctx, false otherwise 1722 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) 1723 { 1724 int i; 1725 bool removed_pipe = false; 1726 struct dc_plane_state *phantom_plane = NULL; 1727 struct dc_stream_state *phantom_stream = NULL; 1728 1729 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1730 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1731 // build scaling params for phantom pipes 1732 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1733 phantom_plane = pipe->plane_state; 1734 phantom_stream = pipe->stream; 1735 1736 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1737 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1738 1739 /* Ref count is incremented on allocation and also when added to the context. 1740 * Therefore we must call release for the the phantom plane and stream once 1741 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1742 */ 1743 dc_plane_state_release(phantom_plane); 1744 dc_stream_release(phantom_stream); 1745 1746 removed_pipe = true; 1747 } 1748 1749 // Clear all phantom stream info 1750 if (pipe->stream) { 1751 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1752 pipe->stream->mall_stream_config.paired_stream = NULL; 1753 } 1754 1755 if (pipe->plane_state) { 1756 pipe->plane_state->is_phantom = false; 1757 } 1758 } 1759 return removed_pipe; 1760 } 1761 1762 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1763 * require a phantom pipe / stream 1764 */ 1765 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1766 display_e2e_pipe_params_st *pipes, 1767 unsigned int pipe_cnt, 1768 unsigned int index) 1769 { 1770 struct dc_stream_state *phantom_stream = NULL; 1771 unsigned int i; 1772 1773 // The index of the DC pipe passed into this function is guarenteed to 1774 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1775 // already have phantom pipe assigned, etc.) by previous checks. 1776 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1777 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1778 1779 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1780 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1781 1782 // Build scaling params for phantom pipes which were newly added. 1783 // We determine which phantom pipes were added by comparing with 1784 // the phantom stream. 1785 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1786 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1787 pipe->stream->use_dynamic_meta = false; 1788 pipe->plane_state->flip_immediate = false; 1789 if (!resource_build_scaling_params(pipe)) { 1790 // Log / remove phantom pipes since failed to build scaling params 1791 } 1792 } 1793 } 1794 } 1795 1796 bool dcn32_validate_bandwidth(struct dc *dc, 1797 struct dc_state *context, 1798 bool fast_validate) 1799 { 1800 bool out = false; 1801 1802 BW_VAL_TRACE_SETUP(); 1803 1804 int vlevel = 0; 1805 int pipe_cnt = 0; 1806 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1807 struct mall_temp_config mall_temp_config; 1808 1809 /* To handle Freesync properly, setting FreeSync DML parameters 1810 * to its default state for the first stage of validation 1811 */ 1812 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1813 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1814 1815 DC_LOGGER_INIT(dc->ctx->logger); 1816 1817 /* For fast validation, there are situations where a shallow copy of 1818 * of the dc->current_state is created for the validation. In this case 1819 * we want to save and restore the mall config because we always 1820 * teardown subvp at the beginning of validation (and don't attempt 1821 * to add it back if it's fast validation). If we don't restore the 1822 * subvp config in cases of fast validation + shallow copy of the 1823 * dc->current_state, the dc->current_state will have a partially 1824 * removed subvp state when we did not intend to remove it. 1825 */ 1826 if (fast_validate) { 1827 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1828 dcn32_save_mall_state(dc, context, &mall_temp_config); 1829 } 1830 1831 BW_VAL_TRACE_COUNT(); 1832 1833 DC_FP_START(); 1834 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1835 DC_FP_END(); 1836 1837 if (fast_validate) 1838 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1839 1840 if (pipe_cnt == 0) 1841 goto validate_out; 1842 1843 if (!out) 1844 goto validate_fail; 1845 1846 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1847 1848 if (fast_validate) { 1849 BW_VAL_TRACE_SKIP(fast); 1850 goto validate_out; 1851 } 1852 1853 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1854 1855 BW_VAL_TRACE_END_WATERMARKS(); 1856 1857 goto validate_out; 1858 1859 validate_fail: 1860 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1861 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1862 1863 BW_VAL_TRACE_SKIP(fail); 1864 out = false; 1865 1866 validate_out: 1867 kfree(pipes); 1868 1869 BW_VAL_TRACE_FINISH(); 1870 1871 return out; 1872 } 1873 1874 int dcn32_populate_dml_pipes_from_context( 1875 struct dc *dc, struct dc_state *context, 1876 display_e2e_pipe_params_st *pipes, 1877 bool fast_validate) 1878 { 1879 int i, pipe_cnt; 1880 struct resource_context *res_ctx = &context->res_ctx; 1881 struct pipe_ctx *pipe; 1882 bool subvp_in_use = false; 1883 uint8_t is_pipe_split_expected[MAX_PIPES] = {0}; 1884 struct dc_crtc_timing *timing; 1885 1886 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1887 1888 /* Determine whether we will apply ODM 2to1 policy: 1889 * Applies to single display and where the number of planes is less than 3. 1890 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1891 * 1892 * Apply pipe split policy first so we can predict the pipe split correctly 1893 * (dcn32_predict_pipe_split). 1894 */ 1895 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1896 if (!res_ctx->pipe_ctx[i].stream) 1897 continue; 1898 pipe = &res_ctx->pipe_ctx[i]; 1899 timing = &pipe->stream->timing; 1900 1901 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1902 if (context->stream_count == 1 && 1903 context->stream_status[0].plane_count <= 1 && 1904 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1905 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1906 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1907 dc->debug.enable_single_display_2to1_odm_policy) { 1908 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1909 } 1910 pipe_cnt++; 1911 } 1912 1913 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1914 1915 if (!res_ctx->pipe_ctx[i].stream) 1916 continue; 1917 pipe = &res_ctx->pipe_ctx[i]; 1918 timing = &pipe->stream->timing; 1919 1920 pipes[pipe_cnt].pipe.src.gpuvm = true; 1921 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1922 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1923 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1924 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1925 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1926 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1927 1928 switch (pipe->stream->mall_stream_config.type) { 1929 case SUBVP_MAIN: 1930 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1931 subvp_in_use = true; 1932 break; 1933 case SUBVP_PHANTOM: 1934 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1935 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1936 // Disallow unbounded req for SubVP according to DCHUB programming guide 1937 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1938 break; 1939 case SUBVP_NONE: 1940 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1941 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1942 break; 1943 default: 1944 break; 1945 } 1946 1947 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1948 if (pipes[pipe_cnt].dout.dsc_enable) { 1949 switch (timing->display_color_depth) { 1950 case COLOR_DEPTH_888: 1951 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1952 break; 1953 case COLOR_DEPTH_101010: 1954 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1955 break; 1956 case COLOR_DEPTH_121212: 1957 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1958 break; 1959 default: 1960 ASSERT(0); 1961 break; 1962 } 1963 } 1964 1965 DC_FP_START(); 1966 is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 1967 DC_FP_END(); 1968 1969 pipe_cnt++; 1970 } 1971 1972 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 1973 * the DET available for each pipe). Use the DET override input to maintain our driver 1974 * policy. 1975 */ 1976 dcn32_set_det_allocations(dc, context, pipes); 1977 1978 // In general cases we want to keep the dram clock change requirement 1979 // (prefer configs that support MCLK switch). Only override to false 1980 // for SubVP 1981 if (subvp_in_use) 1982 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 1983 else 1984 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1985 1986 return pipe_cnt; 1987 } 1988 1989 static struct dc_cap_funcs cap_funcs = { 1990 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1991 }; 1992 1993 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 1994 display_e2e_pipe_params_st *pipes, 1995 int pipe_cnt, 1996 int vlevel) 1997 { 1998 DC_FP_START(); 1999 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2000 DC_FP_END(); 2001 } 2002 2003 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2004 { 2005 DC_FP_START(); 2006 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2007 DC_FP_END(); 2008 } 2009 2010 static struct resource_funcs dcn32_res_pool_funcs = { 2011 .destroy = dcn32_destroy_resource_pool, 2012 .link_enc_create = dcn32_link_encoder_create, 2013 .link_enc_create_minimal = NULL, 2014 .panel_cntl_create = dcn32_panel_cntl_create, 2015 .validate_bandwidth = dcn32_validate_bandwidth, 2016 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2017 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2018 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2019 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2020 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2021 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2022 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2023 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2024 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2025 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2026 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2027 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2028 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2029 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2030 .add_phantom_pipes = dcn32_add_phantom_pipes, 2031 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2032 }; 2033 2034 2035 static bool dcn32_resource_construct( 2036 uint8_t num_virtual_links, 2037 struct dc *dc, 2038 struct dcn32_resource_pool *pool) 2039 { 2040 int i, j; 2041 struct dc_context *ctx = dc->ctx; 2042 struct irq_service_init_data init_data; 2043 struct ddc_service_init_data ddc_init_data = {0}; 2044 uint32_t pipe_fuses = 0; 2045 uint32_t num_pipes = 4; 2046 2047 #undef REG_STRUCT 2048 #define REG_STRUCT bios_regs 2049 bios_regs_init(); 2050 2051 #undef REG_STRUCT 2052 #define REG_STRUCT clk_src_regs 2053 clk_src_regs_init(0, A), 2054 clk_src_regs_init(1, B), 2055 clk_src_regs_init(2, C), 2056 clk_src_regs_init(3, D), 2057 clk_src_regs_init(4, E); 2058 #undef REG_STRUCT 2059 #define REG_STRUCT abm_regs 2060 abm_regs_init(0), 2061 abm_regs_init(1), 2062 abm_regs_init(2), 2063 abm_regs_init(3); 2064 2065 #undef REG_STRUCT 2066 #define REG_STRUCT dccg_regs 2067 dccg_regs_init(); 2068 2069 DC_FP_START(); 2070 2071 ctx->dc_bios->regs = &bios_regs; 2072 2073 pool->base.res_cap = &res_cap_dcn32; 2074 /* max number of pipes for ASIC before checking for pipe fuses */ 2075 num_pipes = pool->base.res_cap->num_timing_generator; 2076 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2077 2078 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2079 if (pipe_fuses & 1 << i) 2080 num_pipes--; 2081 2082 if (pipe_fuses & 1) 2083 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2084 2085 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2086 ASSERT(0); //Entire DCN is harvested! 2087 2088 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2089 * value will be changed, update max_num_dpp and max_num_otg for dml. 2090 */ 2091 dcn3_2_ip.max_num_dpp = num_pipes; 2092 dcn3_2_ip.max_num_otg = num_pipes; 2093 2094 pool->base.funcs = &dcn32_res_pool_funcs; 2095 2096 /************************************************* 2097 * Resource + asic cap harcoding * 2098 *************************************************/ 2099 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2100 pool->base.timing_generator_count = num_pipes; 2101 pool->base.pipe_count = num_pipes; 2102 pool->base.mpcc_count = num_pipes; 2103 dc->caps.max_downscale_ratio = 600; 2104 dc->caps.i2c_speed_in_khz = 100; 2105 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2106 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2107 dc->caps.max_cursor_size = 64; 2108 dc->caps.min_horizontal_blanking_period = 80; 2109 dc->caps.dmdata_alloc_size = 2048; 2110 dc->caps.mall_size_per_mem_channel = 0; 2111 dc->caps.mall_size_total = 0; 2112 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2113 2114 dc->caps.cache_line_size = 64; 2115 dc->caps.cache_num_ways = 16; 2116 dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64 2117 dc->caps.subvp_fw_processing_delay_us = 15; 2118 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2119 dc->caps.subvp_swath_height_margin_lines = 16; 2120 dc->caps.subvp_pstate_allow_width_us = 20; 2121 dc->caps.subvp_vertical_int_margin_us = 30; 2122 2123 dc->caps.max_slave_planes = 2; 2124 dc->caps.max_slave_yuv_planes = 2; 2125 dc->caps.max_slave_rgb_planes = 2; 2126 dc->caps.post_blend_color_processing = true; 2127 dc->caps.force_dp_tps4_for_cp2520 = true; 2128 dc->caps.dp_hpo = true; 2129 dc->caps.dp_hdmi21_pcon_support = true; 2130 dc->caps.edp_dsc_support = true; 2131 dc->caps.extended_aux_timeout_support = true; 2132 dc->caps.dmcub_support = true; 2133 2134 /* Color pipeline capabilities */ 2135 dc->caps.color.dpp.dcn_arch = 1; 2136 dc->caps.color.dpp.input_lut_shared = 0; 2137 dc->caps.color.dpp.icsc = 1; 2138 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2139 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2140 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2141 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2142 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2143 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2144 dc->caps.color.dpp.post_csc = 1; 2145 dc->caps.color.dpp.gamma_corr = 1; 2146 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2147 2148 dc->caps.color.dpp.hw_3d_lut = 1; 2149 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2150 // no OGAM ROM on DCN2 and later ASICs 2151 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2152 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2153 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2154 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2155 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2156 dc->caps.color.dpp.ocsc = 0; 2157 2158 dc->caps.color.mpc.gamut_remap = 1; 2159 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2160 dc->caps.color.mpc.ogam_ram = 1; 2161 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2162 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2163 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2164 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2165 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2166 dc->caps.color.mpc.ocsc = 1; 2167 2168 /* Use pipe context based otg sync logic */ 2169 dc->config.use_pipe_ctx_sync_logic = true; 2170 2171 /* read VBIOS LTTPR caps */ 2172 { 2173 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2174 enum bp_result bp_query_result; 2175 uint8_t is_vbios_lttpr_enable = 0; 2176 2177 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2178 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2179 } 2180 2181 /* interop bit is implicit */ 2182 { 2183 dc->caps.vbios_lttpr_aware = true; 2184 } 2185 } 2186 2187 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2188 dc->debug = debug_defaults_drv; 2189 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2190 dc->debug = debug_defaults_diags; 2191 } else 2192 dc->debug = debug_defaults_diags; 2193 // Init the vm_helper 2194 if (dc->vm_helper) 2195 vm_helper_init(dc->vm_helper, 16); 2196 2197 /************************************************* 2198 * Create resources * 2199 *************************************************/ 2200 2201 /* Clock Sources for Pixel Clock*/ 2202 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2203 dcn32_clock_source_create(ctx, ctx->dc_bios, 2204 CLOCK_SOURCE_COMBO_PHY_PLL0, 2205 &clk_src_regs[0], false); 2206 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2207 dcn32_clock_source_create(ctx, ctx->dc_bios, 2208 CLOCK_SOURCE_COMBO_PHY_PLL1, 2209 &clk_src_regs[1], false); 2210 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2211 dcn32_clock_source_create(ctx, ctx->dc_bios, 2212 CLOCK_SOURCE_COMBO_PHY_PLL2, 2213 &clk_src_regs[2], false); 2214 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2215 dcn32_clock_source_create(ctx, ctx->dc_bios, 2216 CLOCK_SOURCE_COMBO_PHY_PLL3, 2217 &clk_src_regs[3], false); 2218 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2219 dcn32_clock_source_create(ctx, ctx->dc_bios, 2220 CLOCK_SOURCE_COMBO_PHY_PLL4, 2221 &clk_src_regs[4], false); 2222 2223 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2224 2225 /* todo: not reuse phy_pll registers */ 2226 pool->base.dp_clock_source = 2227 dcn32_clock_source_create(ctx, ctx->dc_bios, 2228 CLOCK_SOURCE_ID_DP_DTO, 2229 &clk_src_regs[0], true); 2230 2231 for (i = 0; i < pool->base.clk_src_count; i++) { 2232 if (pool->base.clock_sources[i] == NULL) { 2233 dm_error("DC: failed to create clock sources!\n"); 2234 BREAK_TO_DEBUGGER(); 2235 goto create_fail; 2236 } 2237 } 2238 2239 /* DCCG */ 2240 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2241 if (pool->base.dccg == NULL) { 2242 dm_error("DC: failed to create dccg!\n"); 2243 BREAK_TO_DEBUGGER(); 2244 goto create_fail; 2245 } 2246 2247 /* DML */ 2248 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2249 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2250 2251 /* IRQ Service */ 2252 init_data.ctx = dc->ctx; 2253 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2254 if (!pool->base.irqs) 2255 goto create_fail; 2256 2257 /* HUBBUB */ 2258 pool->base.hubbub = dcn32_hubbub_create(ctx); 2259 if (pool->base.hubbub == NULL) { 2260 BREAK_TO_DEBUGGER(); 2261 dm_error("DC: failed to create hubbub!\n"); 2262 goto create_fail; 2263 } 2264 2265 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2266 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2267 2268 /* if pipe is disabled, skip instance of HW pipe, 2269 * i.e, skip ASIC register instance 2270 */ 2271 if (pipe_fuses & 1 << i) 2272 continue; 2273 2274 /* HUBPs */ 2275 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2276 if (pool->base.hubps[j] == NULL) { 2277 BREAK_TO_DEBUGGER(); 2278 dm_error( 2279 "DC: failed to create hubps!\n"); 2280 goto create_fail; 2281 } 2282 2283 /* DPPs */ 2284 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2285 if (pool->base.dpps[j] == NULL) { 2286 BREAK_TO_DEBUGGER(); 2287 dm_error( 2288 "DC: failed to create dpps!\n"); 2289 goto create_fail; 2290 } 2291 2292 /* OPPs */ 2293 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2294 if (pool->base.opps[j] == NULL) { 2295 BREAK_TO_DEBUGGER(); 2296 dm_error( 2297 "DC: failed to create output pixel processor!\n"); 2298 goto create_fail; 2299 } 2300 2301 /* TGs */ 2302 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2303 ctx, i); 2304 if (pool->base.timing_generators[j] == NULL) { 2305 BREAK_TO_DEBUGGER(); 2306 dm_error("DC: failed to create tg!\n"); 2307 goto create_fail; 2308 } 2309 2310 /* ABMs */ 2311 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2312 &abm_regs[i], 2313 &abm_shift, 2314 &abm_mask); 2315 if (pool->base.multiple_abms[j] == NULL) { 2316 dm_error("DC: failed to create abm for pipe %d!\n", i); 2317 BREAK_TO_DEBUGGER(); 2318 goto create_fail; 2319 } 2320 2321 /* index for resource pool arrays for next valid pipe */ 2322 j++; 2323 } 2324 2325 /* PSR */ 2326 pool->base.psr = dmub_psr_create(ctx); 2327 if (pool->base.psr == NULL) { 2328 dm_error("DC: failed to create psr obj!\n"); 2329 BREAK_TO_DEBUGGER(); 2330 goto create_fail; 2331 } 2332 2333 /* MPCCs */ 2334 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2335 if (pool->base.mpc == NULL) { 2336 BREAK_TO_DEBUGGER(); 2337 dm_error("DC: failed to create mpc!\n"); 2338 goto create_fail; 2339 } 2340 2341 /* DSCs */ 2342 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2343 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2344 if (pool->base.dscs[i] == NULL) { 2345 BREAK_TO_DEBUGGER(); 2346 dm_error("DC: failed to create display stream compressor %d!\n", i); 2347 goto create_fail; 2348 } 2349 } 2350 2351 /* DWB */ 2352 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2353 BREAK_TO_DEBUGGER(); 2354 dm_error("DC: failed to create dwbc!\n"); 2355 goto create_fail; 2356 } 2357 2358 /* MMHUBBUB */ 2359 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2360 BREAK_TO_DEBUGGER(); 2361 dm_error("DC: failed to create mcif_wb!\n"); 2362 goto create_fail; 2363 } 2364 2365 /* AUX and I2C */ 2366 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2367 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2368 if (pool->base.engines[i] == NULL) { 2369 BREAK_TO_DEBUGGER(); 2370 dm_error( 2371 "DC:failed to create aux engine!!\n"); 2372 goto create_fail; 2373 } 2374 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2375 if (pool->base.hw_i2cs[i] == NULL) { 2376 BREAK_TO_DEBUGGER(); 2377 dm_error( 2378 "DC:failed to create hw i2c!!\n"); 2379 goto create_fail; 2380 } 2381 pool->base.sw_i2cs[i] = NULL; 2382 } 2383 2384 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2385 if (!resource_construct(num_virtual_links, dc, &pool->base, 2386 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2387 &res_create_funcs : &res_create_maximus_funcs))) 2388 goto create_fail; 2389 2390 /* HW Sequencer init functions and Plane caps */ 2391 dcn32_hw_sequencer_init_functions(dc); 2392 2393 dc->caps.max_planes = pool->base.pipe_count; 2394 2395 for (i = 0; i < dc->caps.max_planes; ++i) 2396 dc->caps.planes[i] = plane_cap; 2397 2398 dc->cap_funcs = cap_funcs; 2399 2400 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2401 ddc_init_data.ctx = dc->ctx; 2402 ddc_init_data.link = NULL; 2403 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2404 ddc_init_data.id.enum_id = 0; 2405 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2406 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2407 } else { 2408 pool->base.oem_device = NULL; 2409 } 2410 2411 DC_FP_END(); 2412 2413 return true; 2414 2415 create_fail: 2416 2417 DC_FP_END(); 2418 2419 dcn32_resource_destruct(pool); 2420 2421 return false; 2422 } 2423 2424 struct resource_pool *dcn32_create_resource_pool( 2425 const struct dc_init_data *init_data, 2426 struct dc *dc) 2427 { 2428 struct dcn32_resource_pool *pool = 2429 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2430 2431 if (!pool) 2432 return NULL; 2433 2434 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2435 return &pool->base; 2436 2437 BREAK_TO_DEBUGGER(); 2438 kfree(pool); 2439 return NULL; 2440 } 2441 2442 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2443 struct resource_context *res_ctx, 2444 const struct resource_pool *pool, 2445 const struct pipe_ctx *primary_pipe) 2446 { 2447 int i; 2448 struct pipe_ctx *secondary_pipe = NULL; 2449 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2450 int primary_index, preferred_pipe_idx; 2451 struct pipe_ctx *old_primary_pipe = NULL; 2452 2453 /* 2454 * Modified from find_idle_secondary_pipe 2455 * With windowed MPO and ODM, we want to avoid the case where we want a 2456 * free pipe for the left side but the free pipe is being used on the 2457 * right side. 2458 * Add check on current_state if the primary_pipe is the left side, 2459 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2460 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2461 * - If so, then don't use this pipe 2462 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2463 * - in this case, the primary pipe has already gotten a free pipe for the 2464 * MPO window in the left 2465 * - when it tries to get a free pipe for the MPO window on the right, 2466 * it will see that it is already assigned to the right side 2467 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2468 * free pipe, since it will be for the right side. So add an 2469 * additional condition, that skipping the free pipe on the right only 2470 * applies if the primary pipe has no bottom pipe currently assigned 2471 */ 2472 if (primary_pipe) { 2473 primary_index = primary_pipe->pipe_idx; 2474 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2475 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2476 && (!primary_pipe->bottom_pipe)) 2477 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2478 2479 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2480 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2481 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2482 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2483 secondary_pipe->pipe_idx = preferred_pipe_idx; 2484 } 2485 } 2486 2487 /* 2488 * search backwards for the second pipe to keep pipe 2489 * assignment more consistent 2490 */ 2491 if (!secondary_pipe) 2492 for (i = pool->pipe_count - 1; i >= 0; i--) { 2493 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2494 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2495 secondary_pipe = &res_ctx->pipe_ctx[i]; 2496 secondary_pipe->pipe_idx = i; 2497 break; 2498 } 2499 } 2500 2501 return secondary_pipe; 2502 } 2503 2504 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2505 struct dc_state *state, 2506 const struct resource_pool *pool, 2507 struct dc_stream_state *stream, 2508 struct pipe_ctx *head_pipe) 2509 { 2510 struct resource_context *res_ctx = &state->res_ctx; 2511 struct pipe_ctx *idle_pipe, *pipe; 2512 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2513 int head_index; 2514 2515 if (!head_pipe) 2516 ASSERT(0); 2517 2518 /* 2519 * Modified from dcn20_acquire_idle_pipe_for_layer 2520 * Check if head_pipe in old_context already has bottom_pipe allocated. 2521 * - If so, check if that pipe is available in the current context. 2522 * -- If so, reuse pipe from old_context 2523 */ 2524 head_index = head_pipe->pipe_idx; 2525 pipe = &old_ctx->pipe_ctx[head_index]; 2526 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2527 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2528 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2529 } else { 2530 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2531 if (!idle_pipe) 2532 return NULL; 2533 } 2534 2535 idle_pipe->stream = head_pipe->stream; 2536 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2537 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2538 2539 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2540 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2541 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2542 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2543 2544 return idle_pipe; 2545 } 2546