1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dc_link_dp.h" 61 #include "dcn31/dcn31_apg.h" 62 #include "dcn31/dcn31_dio_link_encoder.h" 63 #include "dcn32/dcn32_dio_link_encoder.h" 64 #include "dce/dce_clock_source.h" 65 #include "dce/dce_audio.h" 66 #include "dce/dce_hwseq.h" 67 #include "clk_mgr.h" 68 #include "virtual/virtual_stream_encoder.h" 69 #include "dml/display_mode_vba.h" 70 #include "dcn32/dcn32_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dc_link_ddc.h" 73 #include "dcn31/dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn32/dcn32_mmhubbub.h" 77 78 #include "dcn/dcn_3_2_0_offset.h" 79 #include "dcn/dcn_3_2_0_sh_mask.h" 80 #include "nbio/nbio_4_3_0_offset.h" 81 82 #include "reg_helper.h" 83 #include "dce/dmub_abm.h" 84 #include "dce/dmub_psr.h" 85 #include "dce/dce_aux.h" 86 #include "dce/dce_i2c.h" 87 88 #include "dml/dcn30/display_mode_vba_30.h" 89 #include "vm_helper.h" 90 #include "dcn20/dcn20_vmid.h" 91 #include "dml/dcn32/dcn32_fpu.h" 92 93 #define DC_LOGGER_INIT(logger) 94 95 enum dcn32_clk_src_array_id { 96 DCN32_CLK_SRC_PLL0, 97 DCN32_CLK_SRC_PLL1, 98 DCN32_CLK_SRC_PLL2, 99 DCN32_CLK_SRC_PLL3, 100 DCN32_CLK_SRC_PLL4, 101 DCN32_CLK_SRC_TOTAL 102 }; 103 104 /* begin ********************* 105 * macros to expend register list macro defined in HW object header file 106 */ 107 108 /* DCN */ 109 /* TODO awful hack. fixup dcn20_dwb.h */ 110 #undef BASE_INNER 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id) \ 119 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 120 121 #define SR_ARR_INIT(reg_name, id, value) \ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 .enable_dp_dig_pixel_rate_div_policy = 1, 722 .allow_sw_cursor_fallback = false, 723 .alloc_extra_way_for_cursor = true, 724 }; 725 726 static const struct dc_debug_options debug_defaults_diags = { 727 .disable_dmcu = true, 728 .force_abm_enable = false, 729 .timing_trace = true, 730 .clock_trace = true, 731 .disable_dpp_power_gate = true, 732 .disable_hubp_power_gate = true, 733 .disable_dsc_power_gate = true, 734 .disable_clock_gate = true, 735 .disable_pplib_clock_request = true, 736 .disable_pplib_wm_range = true, 737 .disable_stutter = false, 738 .scl_reset_length10 = true, 739 .dwb_fi_phase = -1, // -1 = disable 740 .dmub_command_table = true, 741 .enable_tri_buf = true, 742 .use_max_lb = true, 743 .force_disable_subvp = true 744 }; 745 746 static struct dce_aux *dcn32_aux_engine_create( 747 struct dc_context *ctx, 748 uint32_t inst) 749 { 750 struct aux_engine_dce110 *aux_engine = 751 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 752 753 if (!aux_engine) 754 return NULL; 755 756 #undef REG_STRUCT 757 #define REG_STRUCT aux_engine_regs 758 aux_engine_regs_init(0), 759 aux_engine_regs_init(1), 760 aux_engine_regs_init(2), 761 aux_engine_regs_init(3), 762 aux_engine_regs_init(4); 763 764 dce110_aux_engine_construct(aux_engine, ctx, inst, 765 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 766 &aux_engine_regs[inst], 767 &aux_mask, 768 &aux_shift, 769 ctx->dc->caps.extended_aux_timeout_support); 770 771 return &aux_engine->base; 772 } 773 #define i2c_inst_regs_init(id)\ 774 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 775 776 static struct dce_i2c_registers i2c_hw_regs[5]; 777 778 static const struct dce_i2c_shift i2c_shifts = { 779 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 780 }; 781 782 static const struct dce_i2c_mask i2c_masks = { 783 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 784 }; 785 786 static struct dce_i2c_hw *dcn32_i2c_hw_create( 787 struct dc_context *ctx, 788 uint32_t inst) 789 { 790 struct dce_i2c_hw *dce_i2c_hw = 791 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 792 793 if (!dce_i2c_hw) 794 return NULL; 795 796 #undef REG_STRUCT 797 #define REG_STRUCT i2c_hw_regs 798 i2c_inst_regs_init(1), 799 i2c_inst_regs_init(2), 800 i2c_inst_regs_init(3), 801 i2c_inst_regs_init(4), 802 i2c_inst_regs_init(5); 803 804 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 805 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 806 807 return dce_i2c_hw; 808 } 809 810 static struct clock_source *dcn32_clock_source_create( 811 struct dc_context *ctx, 812 struct dc_bios *bios, 813 enum clock_source_id id, 814 const struct dce110_clk_src_regs *regs, 815 bool dp_clk_src) 816 { 817 struct dce110_clk_src *clk_src = 818 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 819 820 if (!clk_src) 821 return NULL; 822 823 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 824 regs, &cs_shift, &cs_mask)) { 825 clk_src->base.dp_clk_src = dp_clk_src; 826 return &clk_src->base; 827 } 828 829 BREAK_TO_DEBUGGER(); 830 return NULL; 831 } 832 833 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 834 { 835 int i; 836 837 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 838 GFP_KERNEL); 839 840 if (!hubbub2) 841 return NULL; 842 843 #undef REG_STRUCT 844 #define REG_STRUCT hubbub_reg 845 hubbub_reg_init(); 846 847 #undef REG_STRUCT 848 #define REG_STRUCT vmid_regs 849 vmid_regs_init(0), 850 vmid_regs_init(1), 851 vmid_regs_init(2), 852 vmid_regs_init(3), 853 vmid_regs_init(4), 854 vmid_regs_init(5), 855 vmid_regs_init(6), 856 vmid_regs_init(7), 857 vmid_regs_init(8), 858 vmid_regs_init(9), 859 vmid_regs_init(10), 860 vmid_regs_init(11), 861 vmid_regs_init(12), 862 vmid_regs_init(13), 863 vmid_regs_init(14), 864 vmid_regs_init(15); 865 866 hubbub32_construct(hubbub2, ctx, 867 &hubbub_reg, 868 &hubbub_shift, 869 &hubbub_mask, 870 ctx->dc->dml.ip.det_buffer_size_kbytes, 871 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 872 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 873 874 875 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 876 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 877 878 vmid->ctx = ctx; 879 880 vmid->regs = &vmid_regs[i]; 881 vmid->shifts = &vmid_shifts; 882 vmid->masks = &vmid_masks; 883 } 884 885 return &hubbub2->base; 886 } 887 888 static struct hubp *dcn32_hubp_create( 889 struct dc_context *ctx, 890 uint32_t inst) 891 { 892 struct dcn20_hubp *hubp2 = 893 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 894 895 if (!hubp2) 896 return NULL; 897 898 #undef REG_STRUCT 899 #define REG_STRUCT hubp_regs 900 hubp_regs_init(0), 901 hubp_regs_init(1), 902 hubp_regs_init(2), 903 hubp_regs_init(3); 904 905 if (hubp32_construct(hubp2, ctx, inst, 906 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 907 return &hubp2->base; 908 909 BREAK_TO_DEBUGGER(); 910 kfree(hubp2); 911 return NULL; 912 } 913 914 static void dcn32_dpp_destroy(struct dpp **dpp) 915 { 916 kfree(TO_DCN30_DPP(*dpp)); 917 *dpp = NULL; 918 } 919 920 static struct dpp *dcn32_dpp_create( 921 struct dc_context *ctx, 922 uint32_t inst) 923 { 924 struct dcn3_dpp *dpp3 = 925 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 926 927 if (!dpp3) 928 return NULL; 929 930 #undef REG_STRUCT 931 #define REG_STRUCT dpp_regs 932 dpp_regs_init(0), 933 dpp_regs_init(1), 934 dpp_regs_init(2), 935 dpp_regs_init(3); 936 937 if (dpp32_construct(dpp3, ctx, inst, 938 &dpp_regs[inst], &tf_shift, &tf_mask)) 939 return &dpp3->base; 940 941 BREAK_TO_DEBUGGER(); 942 kfree(dpp3); 943 return NULL; 944 } 945 946 static struct mpc *dcn32_mpc_create( 947 struct dc_context *ctx, 948 int num_mpcc, 949 int num_rmu) 950 { 951 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 952 GFP_KERNEL); 953 954 if (!mpc30) 955 return NULL; 956 957 #undef REG_STRUCT 958 #define REG_STRUCT mpc_regs 959 dcn_mpc_regs_init(); 960 961 dcn32_mpc_construct(mpc30, ctx, 962 &mpc_regs, 963 &mpc_shift, 964 &mpc_mask, 965 num_mpcc, 966 num_rmu); 967 968 return &mpc30->base; 969 } 970 971 static struct output_pixel_processor *dcn32_opp_create( 972 struct dc_context *ctx, uint32_t inst) 973 { 974 struct dcn20_opp *opp2 = 975 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 976 977 if (!opp2) { 978 BREAK_TO_DEBUGGER(); 979 return NULL; 980 } 981 982 #undef REG_STRUCT 983 #define REG_STRUCT opp_regs 984 opp_regs_init(0), 985 opp_regs_init(1), 986 opp_regs_init(2), 987 opp_regs_init(3); 988 989 dcn20_opp_construct(opp2, ctx, inst, 990 &opp_regs[inst], &opp_shift, &opp_mask); 991 return &opp2->base; 992 } 993 994 995 static struct timing_generator *dcn32_timing_generator_create( 996 struct dc_context *ctx, 997 uint32_t instance) 998 { 999 struct optc *tgn10 = 1000 kzalloc(sizeof(struct optc), GFP_KERNEL); 1001 1002 if (!tgn10) 1003 return NULL; 1004 1005 #undef REG_STRUCT 1006 #define REG_STRUCT optc_regs 1007 optc_regs_init(0), 1008 optc_regs_init(1), 1009 optc_regs_init(2), 1010 optc_regs_init(3); 1011 1012 tgn10->base.inst = instance; 1013 tgn10->base.ctx = ctx; 1014 1015 tgn10->tg_regs = &optc_regs[instance]; 1016 tgn10->tg_shift = &optc_shift; 1017 tgn10->tg_mask = &optc_mask; 1018 1019 dcn32_timing_generator_init(tgn10); 1020 1021 return &tgn10->base; 1022 } 1023 1024 static const struct encoder_feature_support link_enc_feature = { 1025 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1026 .max_hdmi_pixel_clock = 600000, 1027 .hdmi_ycbcr420_supported = true, 1028 .dp_ycbcr420_supported = true, 1029 .fec_supported = true, 1030 .flags.bits.IS_HBR2_CAPABLE = true, 1031 .flags.bits.IS_HBR3_CAPABLE = true, 1032 .flags.bits.IS_TPS3_CAPABLE = true, 1033 .flags.bits.IS_TPS4_CAPABLE = true 1034 }; 1035 1036 static struct link_encoder *dcn32_link_encoder_create( 1037 struct dc_context *ctx, 1038 const struct encoder_init_data *enc_init_data) 1039 { 1040 struct dcn20_link_encoder *enc20 = 1041 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1042 1043 if (!enc20) 1044 return NULL; 1045 1046 #undef REG_STRUCT 1047 #define REG_STRUCT link_enc_aux_regs 1048 aux_regs_init(0), 1049 aux_regs_init(1), 1050 aux_regs_init(2), 1051 aux_regs_init(3), 1052 aux_regs_init(4); 1053 1054 #undef REG_STRUCT 1055 #define REG_STRUCT link_enc_hpd_regs 1056 hpd_regs_init(0), 1057 hpd_regs_init(1), 1058 hpd_regs_init(2), 1059 hpd_regs_init(3), 1060 hpd_regs_init(4); 1061 1062 #undef REG_STRUCT 1063 #define REG_STRUCT link_enc_regs 1064 link_regs_init(0, A), 1065 link_regs_init(1, B), 1066 link_regs_init(2, C), 1067 link_regs_init(3, D), 1068 link_regs_init(4, E); 1069 1070 dcn32_link_encoder_construct(enc20, 1071 enc_init_data, 1072 &link_enc_feature, 1073 &link_enc_regs[enc_init_data->transmitter], 1074 &link_enc_aux_regs[enc_init_data->channel - 1], 1075 &link_enc_hpd_regs[enc_init_data->hpd_source], 1076 &le_shift, 1077 &le_mask); 1078 1079 return &enc20->enc10.base; 1080 } 1081 1082 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1083 { 1084 struct dcn31_panel_cntl *panel_cntl = 1085 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1086 1087 if (!panel_cntl) 1088 return NULL; 1089 1090 dcn31_panel_cntl_construct(panel_cntl, init_data); 1091 1092 return &panel_cntl->base; 1093 } 1094 1095 static void read_dce_straps( 1096 struct dc_context *ctx, 1097 struct resource_straps *straps) 1098 { 1099 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1100 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1101 1102 } 1103 1104 static struct audio *dcn32_create_audio( 1105 struct dc_context *ctx, unsigned int inst) 1106 { 1107 1108 #undef REG_STRUCT 1109 #define REG_STRUCT audio_regs 1110 audio_regs_init(0), 1111 audio_regs_init(1), 1112 audio_regs_init(2), 1113 audio_regs_init(3), 1114 audio_regs_init(4); 1115 1116 return dce_audio_create(ctx, inst, 1117 &audio_regs[inst], &audio_shift, &audio_mask); 1118 } 1119 1120 static struct vpg *dcn32_vpg_create( 1121 struct dc_context *ctx, 1122 uint32_t inst) 1123 { 1124 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1125 1126 if (!vpg3) 1127 return NULL; 1128 1129 #undef REG_STRUCT 1130 #define REG_STRUCT vpg_regs 1131 vpg_regs_init(0), 1132 vpg_regs_init(1), 1133 vpg_regs_init(2), 1134 vpg_regs_init(3), 1135 vpg_regs_init(4), 1136 vpg_regs_init(5), 1137 vpg_regs_init(6), 1138 vpg_regs_init(7), 1139 vpg_regs_init(8), 1140 vpg_regs_init(9); 1141 1142 vpg3_construct(vpg3, ctx, inst, 1143 &vpg_regs[inst], 1144 &vpg_shift, 1145 &vpg_mask); 1146 1147 return &vpg3->base; 1148 } 1149 1150 static struct afmt *dcn32_afmt_create( 1151 struct dc_context *ctx, 1152 uint32_t inst) 1153 { 1154 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1155 1156 if (!afmt3) 1157 return NULL; 1158 1159 #undef REG_STRUCT 1160 #define REG_STRUCT afmt_regs 1161 afmt_regs_init(0), 1162 afmt_regs_init(1), 1163 afmt_regs_init(2), 1164 afmt_regs_init(3), 1165 afmt_regs_init(4), 1166 afmt_regs_init(5); 1167 1168 afmt3_construct(afmt3, ctx, inst, 1169 &afmt_regs[inst], 1170 &afmt_shift, 1171 &afmt_mask); 1172 1173 return &afmt3->base; 1174 } 1175 1176 static struct apg *dcn31_apg_create( 1177 struct dc_context *ctx, 1178 uint32_t inst) 1179 { 1180 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1181 1182 if (!apg31) 1183 return NULL; 1184 1185 #undef REG_STRUCT 1186 #define REG_STRUCT apg_regs 1187 apg_regs_init(0), 1188 apg_regs_init(1), 1189 apg_regs_init(2), 1190 apg_regs_init(3); 1191 1192 apg31_construct(apg31, ctx, inst, 1193 &apg_regs[inst], 1194 &apg_shift, 1195 &apg_mask); 1196 1197 return &apg31->base; 1198 } 1199 1200 static struct stream_encoder *dcn32_stream_encoder_create( 1201 enum engine_id eng_id, 1202 struct dc_context *ctx) 1203 { 1204 struct dcn10_stream_encoder *enc1; 1205 struct vpg *vpg; 1206 struct afmt *afmt; 1207 int vpg_inst; 1208 int afmt_inst; 1209 1210 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1211 if (eng_id <= ENGINE_ID_DIGF) { 1212 vpg_inst = eng_id; 1213 afmt_inst = eng_id; 1214 } else 1215 return NULL; 1216 1217 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1218 vpg = dcn32_vpg_create(ctx, vpg_inst); 1219 afmt = dcn32_afmt_create(ctx, afmt_inst); 1220 1221 if (!enc1 || !vpg || !afmt) { 1222 kfree(enc1); 1223 kfree(vpg); 1224 kfree(afmt); 1225 return NULL; 1226 } 1227 1228 #undef REG_STRUCT 1229 #define REG_STRUCT stream_enc_regs 1230 stream_enc_regs_init(0), 1231 stream_enc_regs_init(1), 1232 stream_enc_regs_init(2), 1233 stream_enc_regs_init(3), 1234 stream_enc_regs_init(4); 1235 1236 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1237 eng_id, vpg, afmt, 1238 &stream_enc_regs[eng_id], 1239 &se_shift, &se_mask); 1240 1241 return &enc1->base; 1242 } 1243 1244 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1245 enum engine_id eng_id, 1246 struct dc_context *ctx) 1247 { 1248 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1249 struct vpg *vpg; 1250 struct apg *apg; 1251 uint32_t hpo_dp_inst; 1252 uint32_t vpg_inst; 1253 uint32_t apg_inst; 1254 1255 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1256 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1257 1258 /* Mapping of VPG register blocks to HPO DP block instance: 1259 * VPG[6] -> HPO_DP[0] 1260 * VPG[7] -> HPO_DP[1] 1261 * VPG[8] -> HPO_DP[2] 1262 * VPG[9] -> HPO_DP[3] 1263 */ 1264 vpg_inst = hpo_dp_inst + 6; 1265 1266 /* Mapping of APG register blocks to HPO DP block instance: 1267 * APG[0] -> HPO_DP[0] 1268 * APG[1] -> HPO_DP[1] 1269 * APG[2] -> HPO_DP[2] 1270 * APG[3] -> HPO_DP[3] 1271 */ 1272 apg_inst = hpo_dp_inst; 1273 1274 /* allocate HPO stream encoder and create VPG sub-block */ 1275 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1276 vpg = dcn32_vpg_create(ctx, vpg_inst); 1277 apg = dcn31_apg_create(ctx, apg_inst); 1278 1279 if (!hpo_dp_enc31 || !vpg || !apg) { 1280 kfree(hpo_dp_enc31); 1281 kfree(vpg); 1282 kfree(apg); 1283 return NULL; 1284 } 1285 1286 #undef REG_STRUCT 1287 #define REG_STRUCT hpo_dp_stream_enc_regs 1288 hpo_dp_stream_encoder_reg_init(0), 1289 hpo_dp_stream_encoder_reg_init(1), 1290 hpo_dp_stream_encoder_reg_init(2), 1291 hpo_dp_stream_encoder_reg_init(3); 1292 1293 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1294 hpo_dp_inst, eng_id, vpg, apg, 1295 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1296 &hpo_dp_se_shift, &hpo_dp_se_mask); 1297 1298 return &hpo_dp_enc31->base; 1299 } 1300 1301 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1302 uint8_t inst, 1303 struct dc_context *ctx) 1304 { 1305 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1306 1307 /* allocate HPO link encoder */ 1308 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1309 1310 #undef REG_STRUCT 1311 #define REG_STRUCT hpo_dp_link_enc_regs 1312 hpo_dp_link_encoder_reg_init(0), 1313 hpo_dp_link_encoder_reg_init(1); 1314 1315 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1316 &hpo_dp_link_enc_regs[inst], 1317 &hpo_dp_le_shift, &hpo_dp_le_mask); 1318 1319 return &hpo_dp_enc31->base; 1320 } 1321 1322 static struct dce_hwseq *dcn32_hwseq_create( 1323 struct dc_context *ctx) 1324 { 1325 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1326 1327 #undef REG_STRUCT 1328 #define REG_STRUCT hwseq_reg 1329 hwseq_reg_init(); 1330 1331 if (hws) { 1332 hws->ctx = ctx; 1333 hws->regs = &hwseq_reg; 1334 hws->shifts = &hwseq_shift; 1335 hws->masks = &hwseq_mask; 1336 } 1337 return hws; 1338 } 1339 static const struct resource_create_funcs res_create_funcs = { 1340 .read_dce_straps = read_dce_straps, 1341 .create_audio = dcn32_create_audio, 1342 .create_stream_encoder = dcn32_stream_encoder_create, 1343 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1344 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1345 .create_hwseq = dcn32_hwseq_create, 1346 }; 1347 1348 static const struct resource_create_funcs res_create_maximus_funcs = { 1349 .read_dce_straps = NULL, 1350 .create_audio = NULL, 1351 .create_stream_encoder = NULL, 1352 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1353 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1354 .create_hwseq = dcn32_hwseq_create, 1355 }; 1356 1357 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1358 { 1359 unsigned int i; 1360 1361 for (i = 0; i < pool->base.stream_enc_count; i++) { 1362 if (pool->base.stream_enc[i] != NULL) { 1363 if (pool->base.stream_enc[i]->vpg != NULL) { 1364 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1365 pool->base.stream_enc[i]->vpg = NULL; 1366 } 1367 if (pool->base.stream_enc[i]->afmt != NULL) { 1368 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1369 pool->base.stream_enc[i]->afmt = NULL; 1370 } 1371 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1372 pool->base.stream_enc[i] = NULL; 1373 } 1374 } 1375 1376 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1377 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1378 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1379 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1380 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1381 } 1382 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1383 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1384 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1385 } 1386 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1387 pool->base.hpo_dp_stream_enc[i] = NULL; 1388 } 1389 } 1390 1391 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1392 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1393 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1394 pool->base.hpo_dp_link_enc[i] = NULL; 1395 } 1396 } 1397 1398 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1399 if (pool->base.dscs[i] != NULL) 1400 dcn20_dsc_destroy(&pool->base.dscs[i]); 1401 } 1402 1403 if (pool->base.mpc != NULL) { 1404 kfree(TO_DCN20_MPC(pool->base.mpc)); 1405 pool->base.mpc = NULL; 1406 } 1407 if (pool->base.hubbub != NULL) { 1408 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1409 pool->base.hubbub = NULL; 1410 } 1411 for (i = 0; i < pool->base.pipe_count; i++) { 1412 if (pool->base.dpps[i] != NULL) 1413 dcn32_dpp_destroy(&pool->base.dpps[i]); 1414 1415 if (pool->base.ipps[i] != NULL) 1416 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1417 1418 if (pool->base.hubps[i] != NULL) { 1419 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1420 pool->base.hubps[i] = NULL; 1421 } 1422 1423 if (pool->base.irqs != NULL) { 1424 dal_irq_service_destroy(&pool->base.irqs); 1425 } 1426 } 1427 1428 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1429 if (pool->base.engines[i] != NULL) 1430 dce110_engine_destroy(&pool->base.engines[i]); 1431 if (pool->base.hw_i2cs[i] != NULL) { 1432 kfree(pool->base.hw_i2cs[i]); 1433 pool->base.hw_i2cs[i] = NULL; 1434 } 1435 if (pool->base.sw_i2cs[i] != NULL) { 1436 kfree(pool->base.sw_i2cs[i]); 1437 pool->base.sw_i2cs[i] = NULL; 1438 } 1439 } 1440 1441 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1442 if (pool->base.opps[i] != NULL) 1443 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1444 } 1445 1446 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1447 if (pool->base.timing_generators[i] != NULL) { 1448 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1449 pool->base.timing_generators[i] = NULL; 1450 } 1451 } 1452 1453 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1454 if (pool->base.dwbc[i] != NULL) { 1455 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1456 pool->base.dwbc[i] = NULL; 1457 } 1458 if (pool->base.mcif_wb[i] != NULL) { 1459 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1460 pool->base.mcif_wb[i] = NULL; 1461 } 1462 } 1463 1464 for (i = 0; i < pool->base.audio_count; i++) { 1465 if (pool->base.audios[i]) 1466 dce_aud_destroy(&pool->base.audios[i]); 1467 } 1468 1469 for (i = 0; i < pool->base.clk_src_count; i++) { 1470 if (pool->base.clock_sources[i] != NULL) { 1471 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1472 pool->base.clock_sources[i] = NULL; 1473 } 1474 } 1475 1476 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1477 if (pool->base.mpc_lut[i] != NULL) { 1478 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1479 pool->base.mpc_lut[i] = NULL; 1480 } 1481 if (pool->base.mpc_shaper[i] != NULL) { 1482 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1483 pool->base.mpc_shaper[i] = NULL; 1484 } 1485 } 1486 1487 if (pool->base.dp_clock_source != NULL) { 1488 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1489 pool->base.dp_clock_source = NULL; 1490 } 1491 1492 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1493 if (pool->base.multiple_abms[i] != NULL) 1494 dce_abm_destroy(&pool->base.multiple_abms[i]); 1495 } 1496 1497 if (pool->base.psr != NULL) 1498 dmub_psr_destroy(&pool->base.psr); 1499 1500 if (pool->base.dccg != NULL) 1501 dcn_dccg_destroy(&pool->base.dccg); 1502 1503 if (pool->base.oem_device != NULL) 1504 dal_ddc_service_destroy(&pool->base.oem_device); 1505 } 1506 1507 1508 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1509 { 1510 int i; 1511 uint32_t dwb_count = pool->res_cap->num_dwb; 1512 1513 for (i = 0; i < dwb_count; i++) { 1514 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1515 GFP_KERNEL); 1516 1517 if (!dwbc30) { 1518 dm_error("DC: failed to create dwbc30!\n"); 1519 return false; 1520 } 1521 1522 #undef REG_STRUCT 1523 #define REG_STRUCT dwbc30_regs 1524 dwbc_regs_dcn3_init(0); 1525 1526 dcn30_dwbc_construct(dwbc30, ctx, 1527 &dwbc30_regs[i], 1528 &dwbc30_shift, 1529 &dwbc30_mask, 1530 i); 1531 1532 pool->dwbc[i] = &dwbc30->base; 1533 } 1534 return true; 1535 } 1536 1537 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1538 { 1539 int i; 1540 uint32_t dwb_count = pool->res_cap->num_dwb; 1541 1542 for (i = 0; i < dwb_count; i++) { 1543 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1544 GFP_KERNEL); 1545 1546 if (!mcif_wb30) { 1547 dm_error("DC: failed to create mcif_wb30!\n"); 1548 return false; 1549 } 1550 1551 #undef REG_STRUCT 1552 #define REG_STRUCT mcif_wb30_regs 1553 mcif_wb_regs_dcn3_init(0); 1554 1555 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1556 &mcif_wb30_regs[i], 1557 &mcif_wb30_shift, 1558 &mcif_wb30_mask, 1559 i); 1560 1561 pool->mcif_wb[i] = &mcif_wb30->base; 1562 } 1563 return true; 1564 } 1565 1566 static struct display_stream_compressor *dcn32_dsc_create( 1567 struct dc_context *ctx, uint32_t inst) 1568 { 1569 struct dcn20_dsc *dsc = 1570 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1571 1572 if (!dsc) { 1573 BREAK_TO_DEBUGGER(); 1574 return NULL; 1575 } 1576 1577 #undef REG_STRUCT 1578 #define REG_STRUCT dsc_regs 1579 dsc_regsDCN20_init(0), 1580 dsc_regsDCN20_init(1), 1581 dsc_regsDCN20_init(2), 1582 dsc_regsDCN20_init(3); 1583 1584 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1585 1586 dsc->max_image_width = 6016; 1587 1588 return &dsc->base; 1589 } 1590 1591 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1592 { 1593 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1594 1595 dcn32_resource_destruct(dcn32_pool); 1596 kfree(dcn32_pool); 1597 *pool = NULL; 1598 } 1599 1600 bool dcn32_acquire_post_bldn_3dlut( 1601 struct resource_context *res_ctx, 1602 const struct resource_pool *pool, 1603 int mpcc_id, 1604 struct dc_3dlut **lut, 1605 struct dc_transfer_func **shaper) 1606 { 1607 bool ret = false; 1608 union dc_3dlut_state *state; 1609 1610 ASSERT(*lut == NULL && *shaper == NULL); 1611 *lut = NULL; 1612 *shaper = NULL; 1613 1614 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1615 *lut = pool->mpc_lut[mpcc_id]; 1616 *shaper = pool->mpc_shaper[mpcc_id]; 1617 state = &pool->mpc_lut[mpcc_id]->state; 1618 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1619 ret = true; 1620 } 1621 return ret; 1622 } 1623 1624 bool dcn32_release_post_bldn_3dlut( 1625 struct resource_context *res_ctx, 1626 const struct resource_pool *pool, 1627 struct dc_3dlut **lut, 1628 struct dc_transfer_func **shaper) 1629 { 1630 int i; 1631 bool ret = false; 1632 1633 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1634 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1635 res_ctx->is_mpc_3dlut_acquired[i] = false; 1636 pool->mpc_lut[i]->state.raw = 0; 1637 *lut = NULL; 1638 *shaper = NULL; 1639 ret = true; 1640 break; 1641 } 1642 } 1643 return ret; 1644 } 1645 1646 static void dcn32_enable_phantom_plane(struct dc *dc, 1647 struct dc_state *context, 1648 struct dc_stream_state *phantom_stream, 1649 unsigned int dc_pipe_idx) 1650 { 1651 struct dc_plane_state *phantom_plane = NULL; 1652 struct dc_plane_state *prev_phantom_plane = NULL; 1653 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1654 1655 while (curr_pipe) { 1656 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1657 phantom_plane = prev_phantom_plane; 1658 else 1659 phantom_plane = dc_create_plane_state(dc); 1660 1661 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1662 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1663 sizeof(phantom_plane->scaling_quality)); 1664 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1665 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1666 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1667 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1668 sizeof(phantom_plane->plane_size)); 1669 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1670 sizeof(phantom_plane->tiling_info)); 1671 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1672 phantom_plane->format = curr_pipe->plane_state->format; 1673 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1674 phantom_plane->visible = curr_pipe->plane_state->visible; 1675 1676 /* Shadow pipe has small viewport. */ 1677 phantom_plane->clip_rect.y = 0; 1678 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; 1679 1680 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1681 1682 curr_pipe = curr_pipe->bottom_pipe; 1683 prev_phantom_plane = phantom_plane; 1684 } 1685 } 1686 1687 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1688 struct dc_state *context, 1689 display_e2e_pipe_params_st *pipes, 1690 unsigned int pipe_cnt, 1691 unsigned int dc_pipe_idx) 1692 { 1693 struct dc_stream_state *phantom_stream = NULL; 1694 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1695 1696 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1697 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1698 phantom_stream->dpms_off = true; 1699 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1700 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1701 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1702 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1703 1704 /* stream has limited viewport and small timing */ 1705 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1706 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1707 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1708 DC_FP_START(); 1709 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1710 DC_FP_END(); 1711 1712 dc_add_stream_to_ctx(dc, context, phantom_stream); 1713 return phantom_stream; 1714 } 1715 1716 // return true if removed piped from ctx, false otherwise 1717 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) 1718 { 1719 int i; 1720 bool removed_pipe = false; 1721 struct dc_plane_state *phantom_plane = NULL; 1722 struct dc_stream_state *phantom_stream = NULL; 1723 1724 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1725 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1726 // build scaling params for phantom pipes 1727 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1728 phantom_plane = pipe->plane_state; 1729 phantom_stream = pipe->stream; 1730 1731 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1732 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1733 1734 /* Ref count is incremented on allocation and also when added to the context. 1735 * Therefore we must call release for the the phantom plane and stream once 1736 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1737 */ 1738 dc_plane_state_release(phantom_plane); 1739 dc_stream_release(phantom_stream); 1740 1741 removed_pipe = true; 1742 } 1743 1744 // Clear all phantom stream info 1745 if (pipe->stream) { 1746 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1747 pipe->stream->mall_stream_config.paired_stream = NULL; 1748 } 1749 } 1750 return removed_pipe; 1751 } 1752 1753 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1754 * require a phantom pipe / stream 1755 */ 1756 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1757 display_e2e_pipe_params_st *pipes, 1758 unsigned int pipe_cnt, 1759 unsigned int index) 1760 { 1761 struct dc_stream_state *phantom_stream = NULL; 1762 unsigned int i; 1763 1764 // The index of the DC pipe passed into this function is guarenteed to 1765 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1766 // already have phantom pipe assigned, etc.) by previous checks. 1767 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1768 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1769 1770 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1771 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1772 1773 // Build scaling params for phantom pipes which were newly added. 1774 // We determine which phantom pipes were added by comparing with 1775 // the phantom stream. 1776 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1777 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1778 pipe->stream->use_dynamic_meta = false; 1779 pipe->plane_state->flip_immediate = false; 1780 if (!resource_build_scaling_params(pipe)) { 1781 // Log / remove phantom pipes since failed to build scaling params 1782 } 1783 } 1784 } 1785 } 1786 1787 bool dcn32_validate_bandwidth(struct dc *dc, 1788 struct dc_state *context, 1789 bool fast_validate) 1790 { 1791 bool out = false; 1792 1793 BW_VAL_TRACE_SETUP(); 1794 1795 int vlevel = 0; 1796 int pipe_cnt = 0; 1797 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1798 DC_LOGGER_INIT(dc->ctx->logger); 1799 1800 BW_VAL_TRACE_COUNT(); 1801 1802 DC_FP_START(); 1803 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1804 DC_FP_END(); 1805 1806 if (pipe_cnt == 0) 1807 goto validate_out; 1808 1809 if (!out) 1810 goto validate_fail; 1811 1812 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1813 1814 if (fast_validate) { 1815 BW_VAL_TRACE_SKIP(fast); 1816 goto validate_out; 1817 } 1818 1819 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1820 1821 BW_VAL_TRACE_END_WATERMARKS(); 1822 1823 goto validate_out; 1824 1825 validate_fail: 1826 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1827 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1828 1829 BW_VAL_TRACE_SKIP(fail); 1830 out = false; 1831 1832 validate_out: 1833 kfree(pipes); 1834 1835 BW_VAL_TRACE_FINISH(); 1836 1837 return out; 1838 } 1839 1840 int dcn32_populate_dml_pipes_from_context( 1841 struct dc *dc, struct dc_state *context, 1842 display_e2e_pipe_params_st *pipes, 1843 bool fast_validate) 1844 { 1845 int i, pipe_cnt; 1846 struct resource_context *res_ctx = &context->res_ctx; 1847 struct pipe_ctx *pipe; 1848 bool subvp_in_use = false; 1849 int plane_count = 0; 1850 struct dc_crtc_timing *timing; 1851 1852 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1853 1854 /* Determine whether we will apply ODM 2to1 policy: 1855 * Applies to single display and where the number of planes is less than 3. 1856 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1857 * 1858 * Apply pipe split policy first so we can predict the pipe split correctly 1859 * (dcn32_predict_pipe_split). 1860 */ 1861 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1862 if (!res_ctx->pipe_ctx[i].stream) 1863 continue; 1864 pipe = &res_ctx->pipe_ctx[i]; 1865 timing = &pipe->stream->timing; 1866 1867 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1868 if (context->stream_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1869 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream)) { 1870 if (dc->debug.enable_single_display_2to1_odm_policy) { 1871 if (!((plane_count > 2) && pipe->top_pipe)) 1872 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1873 } 1874 } 1875 pipe_cnt++; 1876 } 1877 1878 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1879 1880 if (!res_ctx->pipe_ctx[i].stream) 1881 continue; 1882 pipe = &res_ctx->pipe_ctx[i]; 1883 timing = &pipe->stream->timing; 1884 1885 pipes[pipe_cnt].pipe.src.gpuvm = true; 1886 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1887 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1888 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1889 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1890 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1891 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1892 1893 switch (pipe->stream->mall_stream_config.type) { 1894 case SUBVP_MAIN: 1895 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1896 subvp_in_use = true; 1897 break; 1898 case SUBVP_PHANTOM: 1899 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1900 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1901 // Disallow unbounded req for SubVP according to DCHUB programming guide 1902 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1903 break; 1904 case SUBVP_NONE: 1905 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1906 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1907 break; 1908 default: 1909 break; 1910 } 1911 1912 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1913 if (pipes[pipe_cnt].dout.dsc_enable) { 1914 switch (timing->display_color_depth) { 1915 case COLOR_DEPTH_888: 1916 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1917 break; 1918 case COLOR_DEPTH_101010: 1919 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1920 break; 1921 case COLOR_DEPTH_121212: 1922 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1923 break; 1924 default: 1925 ASSERT(0); 1926 break; 1927 } 1928 } 1929 1930 /* Calculate the number of planes we have so we can determine 1931 * whether to apply ODM 2to1 policy or not 1932 */ 1933 if (pipe->stream && !pipe->prev_odm_pipe && 1934 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 1935 ++plane_count; 1936 pipe_cnt++; 1937 } 1938 1939 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 1940 * the DET available for each pipe). Use the DET override input to maintain our driver 1941 * policy. 1942 */ 1943 dcn32_set_det_allocations(dc, context, pipes); 1944 1945 // In general cases we want to keep the dram clock change requirement 1946 // (prefer configs that support MCLK switch). Only override to false 1947 // for SubVP 1948 if (subvp_in_use) 1949 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 1950 else 1951 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1952 1953 return pipe_cnt; 1954 } 1955 1956 static struct dc_cap_funcs cap_funcs = { 1957 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1958 }; 1959 1960 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 1961 display_e2e_pipe_params_st *pipes, 1962 int pipe_cnt, 1963 int vlevel) 1964 { 1965 DC_FP_START(); 1966 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 1967 DC_FP_END(); 1968 } 1969 1970 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1971 { 1972 DC_FP_START(); 1973 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 1974 DC_FP_END(); 1975 } 1976 1977 static struct resource_funcs dcn32_res_pool_funcs = { 1978 .destroy = dcn32_destroy_resource_pool, 1979 .link_enc_create = dcn32_link_encoder_create, 1980 .link_enc_create_minimal = NULL, 1981 .panel_cntl_create = dcn32_panel_cntl_create, 1982 .validate_bandwidth = dcn32_validate_bandwidth, 1983 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1984 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1985 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 1986 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1987 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1988 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1989 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1990 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1991 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1992 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1993 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1994 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 1995 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1996 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1997 .add_phantom_pipes = dcn32_add_phantom_pipes, 1998 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1999 }; 2000 2001 2002 static bool dcn32_resource_construct( 2003 uint8_t num_virtual_links, 2004 struct dc *dc, 2005 struct dcn32_resource_pool *pool) 2006 { 2007 int i, j; 2008 struct dc_context *ctx = dc->ctx; 2009 struct irq_service_init_data init_data; 2010 struct ddc_service_init_data ddc_init_data = {0}; 2011 uint32_t pipe_fuses = 0; 2012 uint32_t num_pipes = 4; 2013 2014 #undef REG_STRUCT 2015 #define REG_STRUCT bios_regs 2016 bios_regs_init(); 2017 2018 #undef REG_STRUCT 2019 #define REG_STRUCT clk_src_regs 2020 clk_src_regs_init(0, A), 2021 clk_src_regs_init(1, B), 2022 clk_src_regs_init(2, C), 2023 clk_src_regs_init(3, D), 2024 clk_src_regs_init(4, E); 2025 #undef REG_STRUCT 2026 #define REG_STRUCT abm_regs 2027 abm_regs_init(0), 2028 abm_regs_init(1), 2029 abm_regs_init(2), 2030 abm_regs_init(3); 2031 2032 #undef REG_STRUCT 2033 #define REG_STRUCT dccg_regs 2034 dccg_regs_init(); 2035 2036 DC_FP_START(); 2037 2038 ctx->dc_bios->regs = &bios_regs; 2039 2040 pool->base.res_cap = &res_cap_dcn32; 2041 /* max number of pipes for ASIC before checking for pipe fuses */ 2042 num_pipes = pool->base.res_cap->num_timing_generator; 2043 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2044 2045 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2046 if (pipe_fuses & 1 << i) 2047 num_pipes--; 2048 2049 if (pipe_fuses & 1) 2050 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2051 2052 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2053 ASSERT(0); //Entire DCN is harvested! 2054 2055 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2056 * value will be changed, update max_num_dpp and max_num_otg for dml. 2057 */ 2058 dcn3_2_ip.max_num_dpp = num_pipes; 2059 dcn3_2_ip.max_num_otg = num_pipes; 2060 2061 pool->base.funcs = &dcn32_res_pool_funcs; 2062 2063 /************************************************* 2064 * Resource + asic cap harcoding * 2065 *************************************************/ 2066 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2067 pool->base.timing_generator_count = num_pipes; 2068 pool->base.pipe_count = num_pipes; 2069 pool->base.mpcc_count = num_pipes; 2070 dc->caps.max_downscale_ratio = 600; 2071 dc->caps.i2c_speed_in_khz = 100; 2072 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2073 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2074 dc->caps.max_cursor_size = 64; 2075 dc->caps.min_horizontal_blanking_period = 80; 2076 dc->caps.dmdata_alloc_size = 2048; 2077 dc->caps.mall_size_per_mem_channel = 0; 2078 dc->caps.mall_size_total = 0; 2079 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2080 2081 dc->caps.cache_line_size = 64; 2082 dc->caps.cache_num_ways = 16; 2083 dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64 2084 dc->caps.subvp_fw_processing_delay_us = 15; 2085 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2086 dc->caps.subvp_swath_height_margin_lines = 16; 2087 dc->caps.subvp_pstate_allow_width_us = 20; 2088 dc->caps.subvp_vertical_int_margin_us = 30; 2089 2090 dc->caps.max_slave_planes = 2; 2091 dc->caps.max_slave_yuv_planes = 2; 2092 dc->caps.max_slave_rgb_planes = 2; 2093 dc->caps.post_blend_color_processing = true; 2094 dc->caps.force_dp_tps4_for_cp2520 = true; 2095 dc->caps.dp_hpo = true; 2096 dc->caps.dp_hdmi21_pcon_support = true; 2097 dc->caps.edp_dsc_support = true; 2098 dc->caps.extended_aux_timeout_support = true; 2099 dc->caps.dmcub_support = true; 2100 2101 /* Color pipeline capabilities */ 2102 dc->caps.color.dpp.dcn_arch = 1; 2103 dc->caps.color.dpp.input_lut_shared = 0; 2104 dc->caps.color.dpp.icsc = 1; 2105 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2106 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2107 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2108 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2109 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2110 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2111 dc->caps.color.dpp.post_csc = 1; 2112 dc->caps.color.dpp.gamma_corr = 1; 2113 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2114 2115 dc->caps.color.dpp.hw_3d_lut = 1; 2116 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2117 // no OGAM ROM on DCN2 and later ASICs 2118 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2119 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2120 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2121 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2122 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2123 dc->caps.color.dpp.ocsc = 0; 2124 2125 dc->caps.color.mpc.gamut_remap = 1; 2126 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2127 dc->caps.color.mpc.ogam_ram = 1; 2128 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2129 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2130 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2131 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2132 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2133 dc->caps.color.mpc.ocsc = 1; 2134 2135 /* Use pipe context based otg sync logic */ 2136 dc->config.use_pipe_ctx_sync_logic = true; 2137 2138 /* read VBIOS LTTPR caps */ 2139 { 2140 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2141 enum bp_result bp_query_result; 2142 uint8_t is_vbios_lttpr_enable = 0; 2143 2144 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2145 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2146 } 2147 2148 /* interop bit is implicit */ 2149 { 2150 dc->caps.vbios_lttpr_aware = true; 2151 } 2152 } 2153 2154 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2155 dc->debug = debug_defaults_drv; 2156 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2157 dc->debug = debug_defaults_diags; 2158 } else 2159 dc->debug = debug_defaults_diags; 2160 // Init the vm_helper 2161 if (dc->vm_helper) 2162 vm_helper_init(dc->vm_helper, 16); 2163 2164 /************************************************* 2165 * Create resources * 2166 *************************************************/ 2167 2168 /* Clock Sources for Pixel Clock*/ 2169 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2170 dcn32_clock_source_create(ctx, ctx->dc_bios, 2171 CLOCK_SOURCE_COMBO_PHY_PLL0, 2172 &clk_src_regs[0], false); 2173 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2174 dcn32_clock_source_create(ctx, ctx->dc_bios, 2175 CLOCK_SOURCE_COMBO_PHY_PLL1, 2176 &clk_src_regs[1], false); 2177 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2178 dcn32_clock_source_create(ctx, ctx->dc_bios, 2179 CLOCK_SOURCE_COMBO_PHY_PLL2, 2180 &clk_src_regs[2], false); 2181 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2182 dcn32_clock_source_create(ctx, ctx->dc_bios, 2183 CLOCK_SOURCE_COMBO_PHY_PLL3, 2184 &clk_src_regs[3], false); 2185 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2186 dcn32_clock_source_create(ctx, ctx->dc_bios, 2187 CLOCK_SOURCE_COMBO_PHY_PLL4, 2188 &clk_src_regs[4], false); 2189 2190 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2191 2192 /* todo: not reuse phy_pll registers */ 2193 pool->base.dp_clock_source = 2194 dcn32_clock_source_create(ctx, ctx->dc_bios, 2195 CLOCK_SOURCE_ID_DP_DTO, 2196 &clk_src_regs[0], true); 2197 2198 for (i = 0; i < pool->base.clk_src_count; i++) { 2199 if (pool->base.clock_sources[i] == NULL) { 2200 dm_error("DC: failed to create clock sources!\n"); 2201 BREAK_TO_DEBUGGER(); 2202 goto create_fail; 2203 } 2204 } 2205 2206 /* DCCG */ 2207 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2208 if (pool->base.dccg == NULL) { 2209 dm_error("DC: failed to create dccg!\n"); 2210 BREAK_TO_DEBUGGER(); 2211 goto create_fail; 2212 } 2213 2214 /* DML */ 2215 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2216 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2217 2218 /* IRQ Service */ 2219 init_data.ctx = dc->ctx; 2220 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2221 if (!pool->base.irqs) 2222 goto create_fail; 2223 2224 /* HUBBUB */ 2225 pool->base.hubbub = dcn32_hubbub_create(ctx); 2226 if (pool->base.hubbub == NULL) { 2227 BREAK_TO_DEBUGGER(); 2228 dm_error("DC: failed to create hubbub!\n"); 2229 goto create_fail; 2230 } 2231 2232 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2233 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2234 2235 /* if pipe is disabled, skip instance of HW pipe, 2236 * i.e, skip ASIC register instance 2237 */ 2238 if (pipe_fuses & 1 << i) 2239 continue; 2240 2241 /* HUBPs */ 2242 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2243 if (pool->base.hubps[j] == NULL) { 2244 BREAK_TO_DEBUGGER(); 2245 dm_error( 2246 "DC: failed to create hubps!\n"); 2247 goto create_fail; 2248 } 2249 2250 /* DPPs */ 2251 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2252 if (pool->base.dpps[j] == NULL) { 2253 BREAK_TO_DEBUGGER(); 2254 dm_error( 2255 "DC: failed to create dpps!\n"); 2256 goto create_fail; 2257 } 2258 2259 /* OPPs */ 2260 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2261 if (pool->base.opps[j] == NULL) { 2262 BREAK_TO_DEBUGGER(); 2263 dm_error( 2264 "DC: failed to create output pixel processor!\n"); 2265 goto create_fail; 2266 } 2267 2268 /* TGs */ 2269 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2270 ctx, i); 2271 if (pool->base.timing_generators[j] == NULL) { 2272 BREAK_TO_DEBUGGER(); 2273 dm_error("DC: failed to create tg!\n"); 2274 goto create_fail; 2275 } 2276 2277 /* ABMs */ 2278 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2279 &abm_regs[i], 2280 &abm_shift, 2281 &abm_mask); 2282 if (pool->base.multiple_abms[j] == NULL) { 2283 dm_error("DC: failed to create abm for pipe %d!\n", i); 2284 BREAK_TO_DEBUGGER(); 2285 goto create_fail; 2286 } 2287 2288 /* index for resource pool arrays for next valid pipe */ 2289 j++; 2290 } 2291 2292 /* PSR */ 2293 pool->base.psr = dmub_psr_create(ctx); 2294 if (pool->base.psr == NULL) { 2295 dm_error("DC: failed to create psr obj!\n"); 2296 BREAK_TO_DEBUGGER(); 2297 goto create_fail; 2298 } 2299 2300 /* MPCCs */ 2301 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2302 if (pool->base.mpc == NULL) { 2303 BREAK_TO_DEBUGGER(); 2304 dm_error("DC: failed to create mpc!\n"); 2305 goto create_fail; 2306 } 2307 2308 /* DSCs */ 2309 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2310 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2311 if (pool->base.dscs[i] == NULL) { 2312 BREAK_TO_DEBUGGER(); 2313 dm_error("DC: failed to create display stream compressor %d!\n", i); 2314 goto create_fail; 2315 } 2316 } 2317 2318 /* DWB */ 2319 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2320 BREAK_TO_DEBUGGER(); 2321 dm_error("DC: failed to create dwbc!\n"); 2322 goto create_fail; 2323 } 2324 2325 /* MMHUBBUB */ 2326 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2327 BREAK_TO_DEBUGGER(); 2328 dm_error("DC: failed to create mcif_wb!\n"); 2329 goto create_fail; 2330 } 2331 2332 /* AUX and I2C */ 2333 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2334 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2335 if (pool->base.engines[i] == NULL) { 2336 BREAK_TO_DEBUGGER(); 2337 dm_error( 2338 "DC:failed to create aux engine!!\n"); 2339 goto create_fail; 2340 } 2341 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2342 if (pool->base.hw_i2cs[i] == NULL) { 2343 BREAK_TO_DEBUGGER(); 2344 dm_error( 2345 "DC:failed to create hw i2c!!\n"); 2346 goto create_fail; 2347 } 2348 pool->base.sw_i2cs[i] = NULL; 2349 } 2350 2351 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2352 if (!resource_construct(num_virtual_links, dc, &pool->base, 2353 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2354 &res_create_funcs : &res_create_maximus_funcs))) 2355 goto create_fail; 2356 2357 /* HW Sequencer init functions and Plane caps */ 2358 dcn32_hw_sequencer_init_functions(dc); 2359 2360 dc->caps.max_planes = pool->base.pipe_count; 2361 2362 for (i = 0; i < dc->caps.max_planes; ++i) 2363 dc->caps.planes[i] = plane_cap; 2364 2365 dc->cap_funcs = cap_funcs; 2366 2367 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2368 ddc_init_data.ctx = dc->ctx; 2369 ddc_init_data.link = NULL; 2370 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2371 ddc_init_data.id.enum_id = 0; 2372 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2373 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2374 } else { 2375 pool->base.oem_device = NULL; 2376 } 2377 2378 DC_FP_END(); 2379 2380 return true; 2381 2382 create_fail: 2383 2384 DC_FP_END(); 2385 2386 dcn32_resource_destruct(pool); 2387 2388 return false; 2389 } 2390 2391 struct resource_pool *dcn32_create_resource_pool( 2392 const struct dc_init_data *init_data, 2393 struct dc *dc) 2394 { 2395 struct dcn32_resource_pool *pool = 2396 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2397 2398 if (!pool) 2399 return NULL; 2400 2401 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2402 return &pool->base; 2403 2404 BREAK_TO_DEBUGGER(); 2405 kfree(pool); 2406 return NULL; 2407 } 2408 2409 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2410 struct resource_context *res_ctx, 2411 const struct resource_pool *pool, 2412 const struct pipe_ctx *primary_pipe) 2413 { 2414 int i; 2415 struct pipe_ctx *secondary_pipe = NULL; 2416 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2417 int primary_index, preferred_pipe_idx; 2418 struct pipe_ctx *old_primary_pipe = NULL; 2419 2420 /* 2421 * Modified from find_idle_secondary_pipe 2422 * With windowed MPO and ODM, we want to avoid the case where we want a 2423 * free pipe for the left side but the free pipe is being used on the 2424 * right side. 2425 * Add check on current_state if the primary_pipe is the left side, 2426 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2427 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2428 * - If so, then don't use this pipe 2429 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2430 * - in this case, the primary pipe has already gotten a free pipe for the 2431 * MPO window in the left 2432 * - when it tries to get a free pipe for the MPO window on the right, 2433 * it will see that it is already assigned to the right side 2434 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2435 * free pipe, since it will be for the right side. So add an 2436 * additional condition, that skipping the free pipe on the right only 2437 * applies if the primary pipe has no bottom pipe currently assigned 2438 */ 2439 if (primary_pipe) { 2440 primary_index = primary_pipe->pipe_idx; 2441 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2442 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2443 && (!primary_pipe->bottom_pipe)) 2444 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2445 2446 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2447 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2448 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2449 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2450 secondary_pipe->pipe_idx = preferred_pipe_idx; 2451 } 2452 } 2453 2454 /* 2455 * search backwards for the second pipe to keep pipe 2456 * assignment more consistent 2457 */ 2458 if (!secondary_pipe) 2459 for (i = pool->pipe_count - 1; i >= 0; i--) { 2460 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2461 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2462 secondary_pipe = &res_ctx->pipe_ctx[i]; 2463 secondary_pipe->pipe_idx = i; 2464 break; 2465 } 2466 } 2467 2468 return secondary_pipe; 2469 } 2470 2471 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2472 struct dc_state *state, 2473 const struct resource_pool *pool, 2474 struct dc_stream_state *stream, 2475 struct pipe_ctx *head_pipe) 2476 { 2477 struct resource_context *res_ctx = &state->res_ctx; 2478 struct pipe_ctx *idle_pipe, *pipe; 2479 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2480 int head_index; 2481 2482 if (!head_pipe) 2483 ASSERT(0); 2484 2485 /* 2486 * Modified from dcn20_acquire_idle_pipe_for_layer 2487 * Check if head_pipe in old_context already has bottom_pipe allocated. 2488 * - If so, check if that pipe is available in the current context. 2489 * -- If so, reuse pipe from old_context 2490 */ 2491 head_index = head_pipe->pipe_idx; 2492 pipe = &old_ctx->pipe_ctx[head_index]; 2493 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2494 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2495 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2496 } else { 2497 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2498 if (!idle_pipe) 2499 return NULL; 2500 } 2501 2502 idle_pipe->stream = head_pipe->stream; 2503 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2504 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2505 2506 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2507 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2508 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2509 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2510 2511 return idle_pipe; 2512 } 2513