1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dcn31/dcn31_apg.h" 61 #include "dcn31/dcn31_dio_link_encoder.h" 62 #include "dcn32/dcn32_dio_link_encoder.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn32/dcn32_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "link.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn32/dcn32_mmhubbub.h" 76 77 #include "dcn/dcn_3_2_0_offset.h" 78 #include "dcn/dcn_3_2_0_sh_mask.h" 79 #include "nbio/nbio_4_3_0_offset.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/display_mode_vba_30.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dml/dcn32/dcn32_fpu.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 enum dcn32_clk_src_array_id { 95 DCN32_CLK_SRC_PLL0, 96 DCN32_CLK_SRC_PLL1, 97 DCN32_CLK_SRC_PLL2, 98 DCN32_CLK_SRC_PLL3, 99 DCN32_CLK_SRC_PLL4, 100 DCN32_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 109 110 #define BASE(seg) BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 114 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 117 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name = value 120 121 #define SRI(reg_name, block, id)\ 122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 reg ## block ## id ## _ ## reg_name 124 125 #define SRI_ARR(reg_name, block, id)\ 126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SR_ARR_I2C(reg_name, id) \ 130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 131 132 #define SRI_ARR_I2C(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI2(reg_name, block, id)\ 141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 142 reg ## reg_name 143 #define SRI2_ARR(reg_name, block, id)\ 144 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRIR(var_name, reg_name, block, id)\ 148 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRII(reg_name, block, id)\ 152 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII_ARR_2(reg_name, block, id, inst)\ 156 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_MPC_RMU(reg_name, block, id)\ 160 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_DWB(reg_name, temp_name, block, id)\ 164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## temp_name 166 167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 722 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 723 .enable_double_buffered_dsc_pg_support = true, 724 .enable_dp_dig_pixel_rate_div_policy = 1, 725 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 726 .alloc_extra_way_for_cursor = true, 727 .min_prefetch_in_strobe_ns = 60000, // 60us 728 .disable_unbounded_requesting = false, 729 }; 730 731 static const struct dc_debug_options debug_defaults_diags = { 732 .disable_dmcu = true, 733 .force_abm_enable = false, 734 .timing_trace = true, 735 .clock_trace = true, 736 .disable_dpp_power_gate = true, 737 .disable_hubp_power_gate = true, 738 .disable_dsc_power_gate = true, 739 .disable_clock_gate = true, 740 .disable_pplib_clock_request = true, 741 .disable_pplib_wm_range = true, 742 .disable_stutter = false, 743 .scl_reset_length10 = true, 744 .dwb_fi_phase = -1, // -1 = disable 745 .dmub_command_table = true, 746 .enable_tri_buf = true, 747 .use_max_lb = true, 748 .force_disable_subvp = true 749 }; 750 751 static struct dce_aux *dcn32_aux_engine_create( 752 struct dc_context *ctx, 753 uint32_t inst) 754 { 755 struct aux_engine_dce110 *aux_engine = 756 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 757 758 if (!aux_engine) 759 return NULL; 760 761 #undef REG_STRUCT 762 #define REG_STRUCT aux_engine_regs 763 aux_engine_regs_init(0), 764 aux_engine_regs_init(1), 765 aux_engine_regs_init(2), 766 aux_engine_regs_init(3), 767 aux_engine_regs_init(4); 768 769 dce110_aux_engine_construct(aux_engine, ctx, inst, 770 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 771 &aux_engine_regs[inst], 772 &aux_mask, 773 &aux_shift, 774 ctx->dc->caps.extended_aux_timeout_support); 775 776 return &aux_engine->base; 777 } 778 #define i2c_inst_regs_init(id)\ 779 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 780 781 static struct dce_i2c_registers i2c_hw_regs[5]; 782 783 static const struct dce_i2c_shift i2c_shifts = { 784 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 785 }; 786 787 static const struct dce_i2c_mask i2c_masks = { 788 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 789 }; 790 791 static struct dce_i2c_hw *dcn32_i2c_hw_create( 792 struct dc_context *ctx, 793 uint32_t inst) 794 { 795 struct dce_i2c_hw *dce_i2c_hw = 796 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 797 798 if (!dce_i2c_hw) 799 return NULL; 800 801 #undef REG_STRUCT 802 #define REG_STRUCT i2c_hw_regs 803 i2c_inst_regs_init(1), 804 i2c_inst_regs_init(2), 805 i2c_inst_regs_init(3), 806 i2c_inst_regs_init(4), 807 i2c_inst_regs_init(5); 808 809 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 810 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 811 812 return dce_i2c_hw; 813 } 814 815 static struct clock_source *dcn32_clock_source_create( 816 struct dc_context *ctx, 817 struct dc_bios *bios, 818 enum clock_source_id id, 819 const struct dce110_clk_src_regs *regs, 820 bool dp_clk_src) 821 { 822 struct dce110_clk_src *clk_src = 823 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 824 825 if (!clk_src) 826 return NULL; 827 828 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 829 regs, &cs_shift, &cs_mask)) { 830 clk_src->base.dp_clk_src = dp_clk_src; 831 return &clk_src->base; 832 } 833 834 kfree(clk_src); 835 BREAK_TO_DEBUGGER(); 836 return NULL; 837 } 838 839 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 840 { 841 int i; 842 843 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 844 GFP_KERNEL); 845 846 if (!hubbub2) 847 return NULL; 848 849 #undef REG_STRUCT 850 #define REG_STRUCT hubbub_reg 851 hubbub_reg_init(); 852 853 #undef REG_STRUCT 854 #define REG_STRUCT vmid_regs 855 vmid_regs_init(0), 856 vmid_regs_init(1), 857 vmid_regs_init(2), 858 vmid_regs_init(3), 859 vmid_regs_init(4), 860 vmid_regs_init(5), 861 vmid_regs_init(6), 862 vmid_regs_init(7), 863 vmid_regs_init(8), 864 vmid_regs_init(9), 865 vmid_regs_init(10), 866 vmid_regs_init(11), 867 vmid_regs_init(12), 868 vmid_regs_init(13), 869 vmid_regs_init(14), 870 vmid_regs_init(15); 871 872 hubbub32_construct(hubbub2, ctx, 873 &hubbub_reg, 874 &hubbub_shift, 875 &hubbub_mask, 876 ctx->dc->dml.ip.det_buffer_size_kbytes, 877 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 878 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 879 880 881 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 882 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 883 884 vmid->ctx = ctx; 885 886 vmid->regs = &vmid_regs[i]; 887 vmid->shifts = &vmid_shifts; 888 vmid->masks = &vmid_masks; 889 } 890 891 return &hubbub2->base; 892 } 893 894 static struct hubp *dcn32_hubp_create( 895 struct dc_context *ctx, 896 uint32_t inst) 897 { 898 struct dcn20_hubp *hubp2 = 899 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 900 901 if (!hubp2) 902 return NULL; 903 904 #undef REG_STRUCT 905 #define REG_STRUCT hubp_regs 906 hubp_regs_init(0), 907 hubp_regs_init(1), 908 hubp_regs_init(2), 909 hubp_regs_init(3); 910 911 if (hubp32_construct(hubp2, ctx, inst, 912 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 913 return &hubp2->base; 914 915 BREAK_TO_DEBUGGER(); 916 kfree(hubp2); 917 return NULL; 918 } 919 920 static void dcn32_dpp_destroy(struct dpp **dpp) 921 { 922 kfree(TO_DCN30_DPP(*dpp)); 923 *dpp = NULL; 924 } 925 926 static struct dpp *dcn32_dpp_create( 927 struct dc_context *ctx, 928 uint32_t inst) 929 { 930 struct dcn3_dpp *dpp3 = 931 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 932 933 if (!dpp3) 934 return NULL; 935 936 #undef REG_STRUCT 937 #define REG_STRUCT dpp_regs 938 dpp_regs_init(0), 939 dpp_regs_init(1), 940 dpp_regs_init(2), 941 dpp_regs_init(3); 942 943 if (dpp32_construct(dpp3, ctx, inst, 944 &dpp_regs[inst], &tf_shift, &tf_mask)) 945 return &dpp3->base; 946 947 BREAK_TO_DEBUGGER(); 948 kfree(dpp3); 949 return NULL; 950 } 951 952 static struct mpc *dcn32_mpc_create( 953 struct dc_context *ctx, 954 int num_mpcc, 955 int num_rmu) 956 { 957 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 958 GFP_KERNEL); 959 960 if (!mpc30) 961 return NULL; 962 963 #undef REG_STRUCT 964 #define REG_STRUCT mpc_regs 965 dcn_mpc_regs_init(); 966 967 dcn32_mpc_construct(mpc30, ctx, 968 &mpc_regs, 969 &mpc_shift, 970 &mpc_mask, 971 num_mpcc, 972 num_rmu); 973 974 return &mpc30->base; 975 } 976 977 static struct output_pixel_processor *dcn32_opp_create( 978 struct dc_context *ctx, uint32_t inst) 979 { 980 struct dcn20_opp *opp2 = 981 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 982 983 if (!opp2) { 984 BREAK_TO_DEBUGGER(); 985 return NULL; 986 } 987 988 #undef REG_STRUCT 989 #define REG_STRUCT opp_regs 990 opp_regs_init(0), 991 opp_regs_init(1), 992 opp_regs_init(2), 993 opp_regs_init(3); 994 995 dcn20_opp_construct(opp2, ctx, inst, 996 &opp_regs[inst], &opp_shift, &opp_mask); 997 return &opp2->base; 998 } 999 1000 1001 static struct timing_generator *dcn32_timing_generator_create( 1002 struct dc_context *ctx, 1003 uint32_t instance) 1004 { 1005 struct optc *tgn10 = 1006 kzalloc(sizeof(struct optc), GFP_KERNEL); 1007 1008 if (!tgn10) 1009 return NULL; 1010 1011 #undef REG_STRUCT 1012 #define REG_STRUCT optc_regs 1013 optc_regs_init(0), 1014 optc_regs_init(1), 1015 optc_regs_init(2), 1016 optc_regs_init(3); 1017 1018 tgn10->base.inst = instance; 1019 tgn10->base.ctx = ctx; 1020 1021 tgn10->tg_regs = &optc_regs[instance]; 1022 tgn10->tg_shift = &optc_shift; 1023 tgn10->tg_mask = &optc_mask; 1024 1025 dcn32_timing_generator_init(tgn10); 1026 1027 return &tgn10->base; 1028 } 1029 1030 static const struct encoder_feature_support link_enc_feature = { 1031 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1032 .max_hdmi_pixel_clock = 600000, 1033 .hdmi_ycbcr420_supported = true, 1034 .dp_ycbcr420_supported = true, 1035 .fec_supported = true, 1036 .flags.bits.IS_HBR2_CAPABLE = true, 1037 .flags.bits.IS_HBR3_CAPABLE = true, 1038 .flags.bits.IS_TPS3_CAPABLE = true, 1039 .flags.bits.IS_TPS4_CAPABLE = true 1040 }; 1041 1042 static struct link_encoder *dcn32_link_encoder_create( 1043 struct dc_context *ctx, 1044 const struct encoder_init_data *enc_init_data) 1045 { 1046 struct dcn20_link_encoder *enc20 = 1047 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1048 1049 if (!enc20) 1050 return NULL; 1051 1052 #undef REG_STRUCT 1053 #define REG_STRUCT link_enc_aux_regs 1054 aux_regs_init(0), 1055 aux_regs_init(1), 1056 aux_regs_init(2), 1057 aux_regs_init(3), 1058 aux_regs_init(4); 1059 1060 #undef REG_STRUCT 1061 #define REG_STRUCT link_enc_hpd_regs 1062 hpd_regs_init(0), 1063 hpd_regs_init(1), 1064 hpd_regs_init(2), 1065 hpd_regs_init(3), 1066 hpd_regs_init(4); 1067 1068 #undef REG_STRUCT 1069 #define REG_STRUCT link_enc_regs 1070 link_regs_init(0, A), 1071 link_regs_init(1, B), 1072 link_regs_init(2, C), 1073 link_regs_init(3, D), 1074 link_regs_init(4, E); 1075 1076 dcn32_link_encoder_construct(enc20, 1077 enc_init_data, 1078 &link_enc_feature, 1079 &link_enc_regs[enc_init_data->transmitter], 1080 &link_enc_aux_regs[enc_init_data->channel - 1], 1081 &link_enc_hpd_regs[enc_init_data->hpd_source], 1082 &le_shift, 1083 &le_mask); 1084 1085 return &enc20->enc10.base; 1086 } 1087 1088 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1089 { 1090 struct dcn31_panel_cntl *panel_cntl = 1091 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1092 1093 if (!panel_cntl) 1094 return NULL; 1095 1096 dcn31_panel_cntl_construct(panel_cntl, init_data); 1097 1098 return &panel_cntl->base; 1099 } 1100 1101 static void read_dce_straps( 1102 struct dc_context *ctx, 1103 struct resource_straps *straps) 1104 { 1105 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1106 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1107 1108 } 1109 1110 static struct audio *dcn32_create_audio( 1111 struct dc_context *ctx, unsigned int inst) 1112 { 1113 1114 #undef REG_STRUCT 1115 #define REG_STRUCT audio_regs 1116 audio_regs_init(0), 1117 audio_regs_init(1), 1118 audio_regs_init(2), 1119 audio_regs_init(3), 1120 audio_regs_init(4); 1121 1122 return dce_audio_create(ctx, inst, 1123 &audio_regs[inst], &audio_shift, &audio_mask); 1124 } 1125 1126 static struct vpg *dcn32_vpg_create( 1127 struct dc_context *ctx, 1128 uint32_t inst) 1129 { 1130 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1131 1132 if (!vpg3) 1133 return NULL; 1134 1135 #undef REG_STRUCT 1136 #define REG_STRUCT vpg_regs 1137 vpg_regs_init(0), 1138 vpg_regs_init(1), 1139 vpg_regs_init(2), 1140 vpg_regs_init(3), 1141 vpg_regs_init(4), 1142 vpg_regs_init(5), 1143 vpg_regs_init(6), 1144 vpg_regs_init(7), 1145 vpg_regs_init(8), 1146 vpg_regs_init(9); 1147 1148 vpg3_construct(vpg3, ctx, inst, 1149 &vpg_regs[inst], 1150 &vpg_shift, 1151 &vpg_mask); 1152 1153 return &vpg3->base; 1154 } 1155 1156 static struct afmt *dcn32_afmt_create( 1157 struct dc_context *ctx, 1158 uint32_t inst) 1159 { 1160 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1161 1162 if (!afmt3) 1163 return NULL; 1164 1165 #undef REG_STRUCT 1166 #define REG_STRUCT afmt_regs 1167 afmt_regs_init(0), 1168 afmt_regs_init(1), 1169 afmt_regs_init(2), 1170 afmt_regs_init(3), 1171 afmt_regs_init(4), 1172 afmt_regs_init(5); 1173 1174 afmt3_construct(afmt3, ctx, inst, 1175 &afmt_regs[inst], 1176 &afmt_shift, 1177 &afmt_mask); 1178 1179 return &afmt3->base; 1180 } 1181 1182 static struct apg *dcn31_apg_create( 1183 struct dc_context *ctx, 1184 uint32_t inst) 1185 { 1186 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1187 1188 if (!apg31) 1189 return NULL; 1190 1191 #undef REG_STRUCT 1192 #define REG_STRUCT apg_regs 1193 apg_regs_init(0), 1194 apg_regs_init(1), 1195 apg_regs_init(2), 1196 apg_regs_init(3); 1197 1198 apg31_construct(apg31, ctx, inst, 1199 &apg_regs[inst], 1200 &apg_shift, 1201 &apg_mask); 1202 1203 return &apg31->base; 1204 } 1205 1206 static struct stream_encoder *dcn32_stream_encoder_create( 1207 enum engine_id eng_id, 1208 struct dc_context *ctx) 1209 { 1210 struct dcn10_stream_encoder *enc1; 1211 struct vpg *vpg; 1212 struct afmt *afmt; 1213 int vpg_inst; 1214 int afmt_inst; 1215 1216 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1217 if (eng_id <= ENGINE_ID_DIGF) { 1218 vpg_inst = eng_id; 1219 afmt_inst = eng_id; 1220 } else 1221 return NULL; 1222 1223 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1224 vpg = dcn32_vpg_create(ctx, vpg_inst); 1225 afmt = dcn32_afmt_create(ctx, afmt_inst); 1226 1227 if (!enc1 || !vpg || !afmt) { 1228 kfree(enc1); 1229 kfree(vpg); 1230 kfree(afmt); 1231 return NULL; 1232 } 1233 1234 #undef REG_STRUCT 1235 #define REG_STRUCT stream_enc_regs 1236 stream_enc_regs_init(0), 1237 stream_enc_regs_init(1), 1238 stream_enc_regs_init(2), 1239 stream_enc_regs_init(3), 1240 stream_enc_regs_init(4); 1241 1242 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1243 eng_id, vpg, afmt, 1244 &stream_enc_regs[eng_id], 1245 &se_shift, &se_mask); 1246 1247 return &enc1->base; 1248 } 1249 1250 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1251 enum engine_id eng_id, 1252 struct dc_context *ctx) 1253 { 1254 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1255 struct vpg *vpg; 1256 struct apg *apg; 1257 uint32_t hpo_dp_inst; 1258 uint32_t vpg_inst; 1259 uint32_t apg_inst; 1260 1261 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1262 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1263 1264 /* Mapping of VPG register blocks to HPO DP block instance: 1265 * VPG[6] -> HPO_DP[0] 1266 * VPG[7] -> HPO_DP[1] 1267 * VPG[8] -> HPO_DP[2] 1268 * VPG[9] -> HPO_DP[3] 1269 */ 1270 vpg_inst = hpo_dp_inst + 6; 1271 1272 /* Mapping of APG register blocks to HPO DP block instance: 1273 * APG[0] -> HPO_DP[0] 1274 * APG[1] -> HPO_DP[1] 1275 * APG[2] -> HPO_DP[2] 1276 * APG[3] -> HPO_DP[3] 1277 */ 1278 apg_inst = hpo_dp_inst; 1279 1280 /* allocate HPO stream encoder and create VPG sub-block */ 1281 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1282 vpg = dcn32_vpg_create(ctx, vpg_inst); 1283 apg = dcn31_apg_create(ctx, apg_inst); 1284 1285 if (!hpo_dp_enc31 || !vpg || !apg) { 1286 kfree(hpo_dp_enc31); 1287 kfree(vpg); 1288 kfree(apg); 1289 return NULL; 1290 } 1291 1292 #undef REG_STRUCT 1293 #define REG_STRUCT hpo_dp_stream_enc_regs 1294 hpo_dp_stream_encoder_reg_init(0), 1295 hpo_dp_stream_encoder_reg_init(1), 1296 hpo_dp_stream_encoder_reg_init(2), 1297 hpo_dp_stream_encoder_reg_init(3); 1298 1299 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1300 hpo_dp_inst, eng_id, vpg, apg, 1301 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1302 &hpo_dp_se_shift, &hpo_dp_se_mask); 1303 1304 return &hpo_dp_enc31->base; 1305 } 1306 1307 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1308 uint8_t inst, 1309 struct dc_context *ctx) 1310 { 1311 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1312 1313 /* allocate HPO link encoder */ 1314 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1315 1316 #undef REG_STRUCT 1317 #define REG_STRUCT hpo_dp_link_enc_regs 1318 hpo_dp_link_encoder_reg_init(0), 1319 hpo_dp_link_encoder_reg_init(1); 1320 1321 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1322 &hpo_dp_link_enc_regs[inst], 1323 &hpo_dp_le_shift, &hpo_dp_le_mask); 1324 1325 return &hpo_dp_enc31->base; 1326 } 1327 1328 static struct dce_hwseq *dcn32_hwseq_create( 1329 struct dc_context *ctx) 1330 { 1331 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1332 1333 #undef REG_STRUCT 1334 #define REG_STRUCT hwseq_reg 1335 hwseq_reg_init(); 1336 1337 if (hws) { 1338 hws->ctx = ctx; 1339 hws->regs = &hwseq_reg; 1340 hws->shifts = &hwseq_shift; 1341 hws->masks = &hwseq_mask; 1342 } 1343 return hws; 1344 } 1345 static const struct resource_create_funcs res_create_funcs = { 1346 .read_dce_straps = read_dce_straps, 1347 .create_audio = dcn32_create_audio, 1348 .create_stream_encoder = dcn32_stream_encoder_create, 1349 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1350 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1351 .create_hwseq = dcn32_hwseq_create, 1352 }; 1353 1354 static const struct resource_create_funcs res_create_maximus_funcs = { 1355 .read_dce_straps = NULL, 1356 .create_audio = NULL, 1357 .create_stream_encoder = NULL, 1358 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1359 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1360 .create_hwseq = dcn32_hwseq_create, 1361 }; 1362 1363 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1364 { 1365 unsigned int i; 1366 1367 for (i = 0; i < pool->base.stream_enc_count; i++) { 1368 if (pool->base.stream_enc[i] != NULL) { 1369 if (pool->base.stream_enc[i]->vpg != NULL) { 1370 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1371 pool->base.stream_enc[i]->vpg = NULL; 1372 } 1373 if (pool->base.stream_enc[i]->afmt != NULL) { 1374 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1375 pool->base.stream_enc[i]->afmt = NULL; 1376 } 1377 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1378 pool->base.stream_enc[i] = NULL; 1379 } 1380 } 1381 1382 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1383 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1384 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1385 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1386 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1387 } 1388 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1389 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1390 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1391 } 1392 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1393 pool->base.hpo_dp_stream_enc[i] = NULL; 1394 } 1395 } 1396 1397 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1398 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1399 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1400 pool->base.hpo_dp_link_enc[i] = NULL; 1401 } 1402 } 1403 1404 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1405 if (pool->base.dscs[i] != NULL) 1406 dcn20_dsc_destroy(&pool->base.dscs[i]); 1407 } 1408 1409 if (pool->base.mpc != NULL) { 1410 kfree(TO_DCN20_MPC(pool->base.mpc)); 1411 pool->base.mpc = NULL; 1412 } 1413 if (pool->base.hubbub != NULL) { 1414 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1415 pool->base.hubbub = NULL; 1416 } 1417 for (i = 0; i < pool->base.pipe_count; i++) { 1418 if (pool->base.dpps[i] != NULL) 1419 dcn32_dpp_destroy(&pool->base.dpps[i]); 1420 1421 if (pool->base.ipps[i] != NULL) 1422 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1423 1424 if (pool->base.hubps[i] != NULL) { 1425 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1426 pool->base.hubps[i] = NULL; 1427 } 1428 1429 if (pool->base.irqs != NULL) { 1430 dal_irq_service_destroy(&pool->base.irqs); 1431 } 1432 } 1433 1434 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1435 if (pool->base.engines[i] != NULL) 1436 dce110_engine_destroy(&pool->base.engines[i]); 1437 if (pool->base.hw_i2cs[i] != NULL) { 1438 kfree(pool->base.hw_i2cs[i]); 1439 pool->base.hw_i2cs[i] = NULL; 1440 } 1441 if (pool->base.sw_i2cs[i] != NULL) { 1442 kfree(pool->base.sw_i2cs[i]); 1443 pool->base.sw_i2cs[i] = NULL; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1448 if (pool->base.opps[i] != NULL) 1449 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1450 } 1451 1452 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1453 if (pool->base.timing_generators[i] != NULL) { 1454 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1455 pool->base.timing_generators[i] = NULL; 1456 } 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1460 if (pool->base.dwbc[i] != NULL) { 1461 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1462 pool->base.dwbc[i] = NULL; 1463 } 1464 if (pool->base.mcif_wb[i] != NULL) { 1465 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1466 pool->base.mcif_wb[i] = NULL; 1467 } 1468 } 1469 1470 for (i = 0; i < pool->base.audio_count; i++) { 1471 if (pool->base.audios[i]) 1472 dce_aud_destroy(&pool->base.audios[i]); 1473 } 1474 1475 for (i = 0; i < pool->base.clk_src_count; i++) { 1476 if (pool->base.clock_sources[i] != NULL) { 1477 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1478 pool->base.clock_sources[i] = NULL; 1479 } 1480 } 1481 1482 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1483 if (pool->base.mpc_lut[i] != NULL) { 1484 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1485 pool->base.mpc_lut[i] = NULL; 1486 } 1487 if (pool->base.mpc_shaper[i] != NULL) { 1488 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1489 pool->base.mpc_shaper[i] = NULL; 1490 } 1491 } 1492 1493 if (pool->base.dp_clock_source != NULL) { 1494 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1495 pool->base.dp_clock_source = NULL; 1496 } 1497 1498 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1499 if (pool->base.multiple_abms[i] != NULL) 1500 dce_abm_destroy(&pool->base.multiple_abms[i]); 1501 } 1502 1503 if (pool->base.psr != NULL) 1504 dmub_psr_destroy(&pool->base.psr); 1505 1506 if (pool->base.dccg != NULL) 1507 dcn_dccg_destroy(&pool->base.dccg); 1508 1509 if (pool->base.oem_device != NULL) 1510 link_destroy_ddc_service(&pool->base.oem_device); 1511 } 1512 1513 1514 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1515 { 1516 int i; 1517 uint32_t dwb_count = pool->res_cap->num_dwb; 1518 1519 for (i = 0; i < dwb_count; i++) { 1520 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1521 GFP_KERNEL); 1522 1523 if (!dwbc30) { 1524 dm_error("DC: failed to create dwbc30!\n"); 1525 return false; 1526 } 1527 1528 #undef REG_STRUCT 1529 #define REG_STRUCT dwbc30_regs 1530 dwbc_regs_dcn3_init(0); 1531 1532 dcn30_dwbc_construct(dwbc30, ctx, 1533 &dwbc30_regs[i], 1534 &dwbc30_shift, 1535 &dwbc30_mask, 1536 i); 1537 1538 pool->dwbc[i] = &dwbc30->base; 1539 } 1540 return true; 1541 } 1542 1543 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1544 { 1545 int i; 1546 uint32_t dwb_count = pool->res_cap->num_dwb; 1547 1548 for (i = 0; i < dwb_count; i++) { 1549 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1550 GFP_KERNEL); 1551 1552 if (!mcif_wb30) { 1553 dm_error("DC: failed to create mcif_wb30!\n"); 1554 return false; 1555 } 1556 1557 #undef REG_STRUCT 1558 #define REG_STRUCT mcif_wb30_regs 1559 mcif_wb_regs_dcn3_init(0); 1560 1561 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1562 &mcif_wb30_regs[i], 1563 &mcif_wb30_shift, 1564 &mcif_wb30_mask, 1565 i); 1566 1567 pool->mcif_wb[i] = &mcif_wb30->base; 1568 } 1569 return true; 1570 } 1571 1572 static struct display_stream_compressor *dcn32_dsc_create( 1573 struct dc_context *ctx, uint32_t inst) 1574 { 1575 struct dcn20_dsc *dsc = 1576 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1577 1578 if (!dsc) { 1579 BREAK_TO_DEBUGGER(); 1580 return NULL; 1581 } 1582 1583 #undef REG_STRUCT 1584 #define REG_STRUCT dsc_regs 1585 dsc_regsDCN20_init(0), 1586 dsc_regsDCN20_init(1), 1587 dsc_regsDCN20_init(2), 1588 dsc_regsDCN20_init(3); 1589 1590 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1591 1592 dsc->max_image_width = 6016; 1593 1594 return &dsc->base; 1595 } 1596 1597 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1598 { 1599 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1600 1601 dcn32_resource_destruct(dcn32_pool); 1602 kfree(dcn32_pool); 1603 *pool = NULL; 1604 } 1605 1606 bool dcn32_acquire_post_bldn_3dlut( 1607 struct resource_context *res_ctx, 1608 const struct resource_pool *pool, 1609 int mpcc_id, 1610 struct dc_3dlut **lut, 1611 struct dc_transfer_func **shaper) 1612 { 1613 bool ret = false; 1614 union dc_3dlut_state *state; 1615 1616 ASSERT(*lut == NULL && *shaper == NULL); 1617 *lut = NULL; 1618 *shaper = NULL; 1619 1620 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1621 *lut = pool->mpc_lut[mpcc_id]; 1622 *shaper = pool->mpc_shaper[mpcc_id]; 1623 state = &pool->mpc_lut[mpcc_id]->state; 1624 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1625 ret = true; 1626 } 1627 return ret; 1628 } 1629 1630 bool dcn32_release_post_bldn_3dlut( 1631 struct resource_context *res_ctx, 1632 const struct resource_pool *pool, 1633 struct dc_3dlut **lut, 1634 struct dc_transfer_func **shaper) 1635 { 1636 int i; 1637 bool ret = false; 1638 1639 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1640 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1641 res_ctx->is_mpc_3dlut_acquired[i] = false; 1642 pool->mpc_lut[i]->state.raw = 0; 1643 *lut = NULL; 1644 *shaper = NULL; 1645 ret = true; 1646 break; 1647 } 1648 } 1649 return ret; 1650 } 1651 1652 static void dcn32_enable_phantom_plane(struct dc *dc, 1653 struct dc_state *context, 1654 struct dc_stream_state *phantom_stream, 1655 unsigned int dc_pipe_idx) 1656 { 1657 struct dc_plane_state *phantom_plane = NULL; 1658 struct dc_plane_state *prev_phantom_plane = NULL; 1659 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1660 1661 while (curr_pipe) { 1662 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1663 phantom_plane = prev_phantom_plane; 1664 else 1665 phantom_plane = dc_create_plane_state(dc); 1666 1667 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1668 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1669 sizeof(phantom_plane->scaling_quality)); 1670 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1671 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1672 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1673 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1674 sizeof(phantom_plane->plane_size)); 1675 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1676 sizeof(phantom_plane->tiling_info)); 1677 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1678 phantom_plane->format = curr_pipe->plane_state->format; 1679 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1680 phantom_plane->visible = curr_pipe->plane_state->visible; 1681 1682 /* Shadow pipe has small viewport. */ 1683 phantom_plane->clip_rect.y = 0; 1684 phantom_plane->clip_rect.height = phantom_stream->src.height; 1685 1686 phantom_plane->is_phantom = true; 1687 1688 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1689 1690 curr_pipe = curr_pipe->bottom_pipe; 1691 prev_phantom_plane = phantom_plane; 1692 } 1693 } 1694 1695 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1696 struct dc_state *context, 1697 display_e2e_pipe_params_st *pipes, 1698 unsigned int pipe_cnt, 1699 unsigned int dc_pipe_idx) 1700 { 1701 struct dc_stream_state *phantom_stream = NULL; 1702 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1703 1704 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1705 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1706 phantom_stream->dpms_off = true; 1707 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1708 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1709 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1710 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1711 1712 /* stream has limited viewport and small timing */ 1713 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1714 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1715 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1716 DC_FP_START(); 1717 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1718 DC_FP_END(); 1719 1720 dc_add_stream_to_ctx(dc, context, phantom_stream); 1721 return phantom_stream; 1722 } 1723 1724 void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) 1725 { 1726 int i; 1727 struct dc_plane_state *phantom_plane = NULL; 1728 struct dc_stream_state *phantom_stream = NULL; 1729 1730 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1731 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1732 1733 if (!pipe->top_pipe && !pipe->prev_odm_pipe && 1734 pipe->plane_state && pipe->stream && 1735 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1736 phantom_plane = pipe->plane_state; 1737 phantom_stream = pipe->stream; 1738 1739 dc_plane_state_retain(phantom_plane); 1740 dc_stream_retain(phantom_stream); 1741 } 1742 } 1743 } 1744 1745 // return true if removed piped from ctx, false otherwise 1746 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update) 1747 { 1748 int i; 1749 bool removed_pipe = false; 1750 struct dc_plane_state *phantom_plane = NULL; 1751 struct dc_stream_state *phantom_stream = NULL; 1752 1753 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1754 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1755 // build scaling params for phantom pipes 1756 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1757 phantom_plane = pipe->plane_state; 1758 phantom_stream = pipe->stream; 1759 1760 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1761 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1762 1763 /* Ref count is incremented on allocation and also when added to the context. 1764 * Therefore we must call release for the the phantom plane and stream once 1765 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1766 */ 1767 dc_plane_state_release(phantom_plane); 1768 dc_stream_release(phantom_stream); 1769 1770 removed_pipe = true; 1771 } 1772 1773 /* For non-full updates, a shallow copy of the current state 1774 * is created. In this case we don't want to erase the current 1775 * state (there can be 2 HIRQL threads, one in flip, and one in 1776 * checkMPO) that can cause a race condition. 1777 * 1778 * This is just a workaround, needs a proper fix. 1779 */ 1780 if (!fast_update) { 1781 // Clear all phantom stream info 1782 if (pipe->stream) { 1783 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1784 pipe->stream->mall_stream_config.paired_stream = NULL; 1785 } 1786 1787 if (pipe->plane_state) { 1788 pipe->plane_state->is_phantom = false; 1789 } 1790 } 1791 } 1792 return removed_pipe; 1793 } 1794 1795 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1796 * require a phantom pipe / stream 1797 */ 1798 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1799 display_e2e_pipe_params_st *pipes, 1800 unsigned int pipe_cnt, 1801 unsigned int index) 1802 { 1803 struct dc_stream_state *phantom_stream = NULL; 1804 unsigned int i; 1805 1806 // The index of the DC pipe passed into this function is guarenteed to 1807 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1808 // already have phantom pipe assigned, etc.) by previous checks. 1809 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1810 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1811 1812 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1813 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1814 1815 // Build scaling params for phantom pipes which were newly added. 1816 // We determine which phantom pipes were added by comparing with 1817 // the phantom stream. 1818 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1819 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1820 pipe->stream->use_dynamic_meta = false; 1821 pipe->plane_state->flip_immediate = false; 1822 if (!resource_build_scaling_params(pipe)) { 1823 // Log / remove phantom pipes since failed to build scaling params 1824 } 1825 } 1826 } 1827 } 1828 1829 bool dcn32_validate_bandwidth(struct dc *dc, 1830 struct dc_state *context, 1831 bool fast_validate) 1832 { 1833 bool out = false; 1834 1835 BW_VAL_TRACE_SETUP(); 1836 1837 int vlevel = 0; 1838 int pipe_cnt = 0; 1839 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1840 struct mall_temp_config mall_temp_config; 1841 1842 /* To handle Freesync properly, setting FreeSync DML parameters 1843 * to its default state for the first stage of validation 1844 */ 1845 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1846 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1847 1848 DC_LOGGER_INIT(dc->ctx->logger); 1849 1850 /* For fast validation, there are situations where a shallow copy of 1851 * of the dc->current_state is created for the validation. In this case 1852 * we want to save and restore the mall config because we always 1853 * teardown subvp at the beginning of validation (and don't attempt 1854 * to add it back if it's fast validation). If we don't restore the 1855 * subvp config in cases of fast validation + shallow copy of the 1856 * dc->current_state, the dc->current_state will have a partially 1857 * removed subvp state when we did not intend to remove it. 1858 */ 1859 if (fast_validate) { 1860 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1861 dcn32_save_mall_state(dc, context, &mall_temp_config); 1862 } 1863 1864 BW_VAL_TRACE_COUNT(); 1865 1866 DC_FP_START(); 1867 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1868 DC_FP_END(); 1869 1870 if (fast_validate) 1871 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1872 1873 if (pipe_cnt == 0) 1874 goto validate_out; 1875 1876 if (!out) 1877 goto validate_fail; 1878 1879 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1880 1881 if (fast_validate) { 1882 BW_VAL_TRACE_SKIP(fast); 1883 goto validate_out; 1884 } 1885 1886 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1887 1888 BW_VAL_TRACE_END_WATERMARKS(); 1889 1890 goto validate_out; 1891 1892 validate_fail: 1893 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1894 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1895 1896 BW_VAL_TRACE_SKIP(fail); 1897 out = false; 1898 1899 validate_out: 1900 kfree(pipes); 1901 1902 BW_VAL_TRACE_FINISH(); 1903 1904 return out; 1905 } 1906 1907 int dcn32_populate_dml_pipes_from_context( 1908 struct dc *dc, struct dc_state *context, 1909 display_e2e_pipe_params_st *pipes, 1910 bool fast_validate) 1911 { 1912 int i, pipe_cnt; 1913 struct resource_context *res_ctx = &context->res_ctx; 1914 struct pipe_ctx *pipe; 1915 bool subvp_in_use = false; 1916 uint8_t is_pipe_split_expected[MAX_PIPES] = {0}; 1917 struct dc_crtc_timing *timing; 1918 1919 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1920 1921 /* Determine whether we will apply ODM 2to1 policy: 1922 * Applies to single display and where the number of planes is less than 3. 1923 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1924 * 1925 * Apply pipe split policy first so we can predict the pipe split correctly 1926 * (dcn32_predict_pipe_split). 1927 */ 1928 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1929 if (!res_ctx->pipe_ctx[i].stream) 1930 continue; 1931 pipe = &res_ctx->pipe_ctx[i]; 1932 timing = &pipe->stream->timing; 1933 1934 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1935 if (context->stream_count == 1 && 1936 context->stream_status[0].plane_count == 1 && 1937 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1938 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1939 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1940 dc->debug.enable_single_display_2to1_odm_policy) { 1941 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1942 } 1943 pipe_cnt++; 1944 } 1945 1946 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1947 1948 if (!res_ctx->pipe_ctx[i].stream) 1949 continue; 1950 pipe = &res_ctx->pipe_ctx[i]; 1951 timing = &pipe->stream->timing; 1952 1953 pipes[pipe_cnt].pipe.src.gpuvm = true; 1954 DC_FP_START(); 1955 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1956 DC_FP_END(); 1957 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1958 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1959 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1960 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1961 1962 /* Only populate DML input with subvp info for full updates. 1963 * This is just a workaround -- needs a proper fix. 1964 */ 1965 if (!fast_validate) { 1966 switch (pipe->stream->mall_stream_config.type) { 1967 case SUBVP_MAIN: 1968 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1969 subvp_in_use = true; 1970 break; 1971 case SUBVP_PHANTOM: 1972 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1973 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1974 // Disallow unbounded req for SubVP according to DCHUB programming guide 1975 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1976 break; 1977 case SUBVP_NONE: 1978 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1979 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1980 break; 1981 default: 1982 break; 1983 } 1984 } 1985 1986 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1987 if (pipes[pipe_cnt].dout.dsc_enable) { 1988 switch (timing->display_color_depth) { 1989 case COLOR_DEPTH_888: 1990 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1991 break; 1992 case COLOR_DEPTH_101010: 1993 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1994 break; 1995 case COLOR_DEPTH_121212: 1996 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1997 break; 1998 default: 1999 ASSERT(0); 2000 break; 2001 } 2002 } 2003 2004 DC_FP_START(); 2005 is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 2006 DC_FP_END(); 2007 2008 pipe_cnt++; 2009 } 2010 2011 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2012 * the DET available for each pipe). Use the DET override input to maintain our driver 2013 * policy. 2014 */ 2015 dcn32_set_det_allocations(dc, context, pipes); 2016 2017 // In general cases we want to keep the dram clock change requirement 2018 // (prefer configs that support MCLK switch). Only override to false 2019 // for SubVP 2020 if (subvp_in_use) 2021 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2022 else 2023 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2024 2025 return pipe_cnt; 2026 } 2027 2028 static struct dc_cap_funcs cap_funcs = { 2029 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2030 }; 2031 2032 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2033 display_e2e_pipe_params_st *pipes, 2034 int pipe_cnt, 2035 int vlevel) 2036 { 2037 DC_FP_START(); 2038 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2039 DC_FP_END(); 2040 } 2041 2042 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2043 { 2044 DC_FP_START(); 2045 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2046 DC_FP_END(); 2047 } 2048 2049 static struct resource_funcs dcn32_res_pool_funcs = { 2050 .destroy = dcn32_destroy_resource_pool, 2051 .link_enc_create = dcn32_link_encoder_create, 2052 .link_enc_create_minimal = NULL, 2053 .panel_cntl_create = dcn32_panel_cntl_create, 2054 .validate_bandwidth = dcn32_validate_bandwidth, 2055 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2056 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2057 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2058 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2059 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2060 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2061 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2062 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2063 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2064 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2065 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2066 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2067 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2068 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2069 .add_phantom_pipes = dcn32_add_phantom_pipes, 2070 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2071 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 2072 .save_mall_state = dcn32_save_mall_state, 2073 .restore_mall_state = dcn32_restore_mall_state, 2074 }; 2075 2076 2077 static bool dcn32_resource_construct( 2078 uint8_t num_virtual_links, 2079 struct dc *dc, 2080 struct dcn32_resource_pool *pool) 2081 { 2082 int i, j; 2083 struct dc_context *ctx = dc->ctx; 2084 struct irq_service_init_data init_data; 2085 struct ddc_service_init_data ddc_init_data = {0}; 2086 uint32_t pipe_fuses = 0; 2087 uint32_t num_pipes = 4; 2088 2089 #undef REG_STRUCT 2090 #define REG_STRUCT bios_regs 2091 bios_regs_init(); 2092 2093 #undef REG_STRUCT 2094 #define REG_STRUCT clk_src_regs 2095 clk_src_regs_init(0, A), 2096 clk_src_regs_init(1, B), 2097 clk_src_regs_init(2, C), 2098 clk_src_regs_init(3, D), 2099 clk_src_regs_init(4, E); 2100 #undef REG_STRUCT 2101 #define REG_STRUCT abm_regs 2102 abm_regs_init(0), 2103 abm_regs_init(1), 2104 abm_regs_init(2), 2105 abm_regs_init(3); 2106 2107 #undef REG_STRUCT 2108 #define REG_STRUCT dccg_regs 2109 dccg_regs_init(); 2110 2111 DC_FP_START(); 2112 2113 ctx->dc_bios->regs = &bios_regs; 2114 2115 pool->base.res_cap = &res_cap_dcn32; 2116 /* max number of pipes for ASIC before checking for pipe fuses */ 2117 num_pipes = pool->base.res_cap->num_timing_generator; 2118 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2119 2120 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2121 if (pipe_fuses & 1 << i) 2122 num_pipes--; 2123 2124 if (pipe_fuses & 1) 2125 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2126 2127 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2128 ASSERT(0); //Entire DCN is harvested! 2129 2130 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2131 * value will be changed, update max_num_dpp and max_num_otg for dml. 2132 */ 2133 dcn3_2_ip.max_num_dpp = num_pipes; 2134 dcn3_2_ip.max_num_otg = num_pipes; 2135 2136 pool->base.funcs = &dcn32_res_pool_funcs; 2137 2138 /************************************************* 2139 * Resource + asic cap harcoding * 2140 *************************************************/ 2141 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2142 pool->base.timing_generator_count = num_pipes; 2143 pool->base.pipe_count = num_pipes; 2144 pool->base.mpcc_count = num_pipes; 2145 dc->caps.max_downscale_ratio = 600; 2146 dc->caps.i2c_speed_in_khz = 100; 2147 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2148 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2149 dc->caps.max_cursor_size = 64; 2150 dc->caps.min_horizontal_blanking_period = 80; 2151 dc->caps.dmdata_alloc_size = 2048; 2152 dc->caps.mall_size_per_mem_channel = 4; 2153 dc->caps.mall_size_total = 0; 2154 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2155 2156 dc->caps.cache_line_size = 64; 2157 dc->caps.cache_num_ways = 16; 2158 2159 /* Calculate the available MALL space */ 2160 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2161 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2162 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2163 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2164 2165 dc->caps.subvp_fw_processing_delay_us = 15; 2166 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2167 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2168 dc->caps.subvp_swath_height_margin_lines = 16; 2169 dc->caps.subvp_pstate_allow_width_us = 20; 2170 dc->caps.subvp_vertical_int_margin_us = 30; 2171 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2172 2173 dc->caps.max_slave_planes = 2; 2174 dc->caps.max_slave_yuv_planes = 2; 2175 dc->caps.max_slave_rgb_planes = 2; 2176 dc->caps.post_blend_color_processing = true; 2177 dc->caps.force_dp_tps4_for_cp2520 = true; 2178 if (dc->config.forceHBR2CP2520) 2179 dc->caps.force_dp_tps4_for_cp2520 = false; 2180 dc->caps.dp_hpo = true; 2181 dc->caps.dp_hdmi21_pcon_support = true; 2182 dc->caps.edp_dsc_support = true; 2183 dc->caps.extended_aux_timeout_support = true; 2184 dc->caps.dmcub_support = true; 2185 2186 /* Color pipeline capabilities */ 2187 dc->caps.color.dpp.dcn_arch = 1; 2188 dc->caps.color.dpp.input_lut_shared = 0; 2189 dc->caps.color.dpp.icsc = 1; 2190 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2191 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2192 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2193 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2194 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2195 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2196 dc->caps.color.dpp.post_csc = 1; 2197 dc->caps.color.dpp.gamma_corr = 1; 2198 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2199 2200 dc->caps.color.dpp.hw_3d_lut = 1; 2201 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2202 // no OGAM ROM on DCN2 and later ASICs 2203 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2204 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2205 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2206 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2207 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2208 dc->caps.color.dpp.ocsc = 0; 2209 2210 dc->caps.color.mpc.gamut_remap = 1; 2211 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2212 dc->caps.color.mpc.ogam_ram = 1; 2213 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2214 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2215 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2216 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2217 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2218 dc->caps.color.mpc.ocsc = 1; 2219 2220 /* Use pipe context based otg sync logic */ 2221 dc->config.use_pipe_ctx_sync_logic = true; 2222 2223 /* read VBIOS LTTPR caps */ 2224 { 2225 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2226 enum bp_result bp_query_result; 2227 uint8_t is_vbios_lttpr_enable = 0; 2228 2229 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2230 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2231 } 2232 2233 /* interop bit is implicit */ 2234 { 2235 dc->caps.vbios_lttpr_aware = true; 2236 } 2237 } 2238 2239 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2240 dc->debug = debug_defaults_drv; 2241 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2242 dc->debug = debug_defaults_diags; 2243 } else 2244 dc->debug = debug_defaults_diags; 2245 // Init the vm_helper 2246 if (dc->vm_helper) 2247 vm_helper_init(dc->vm_helper, 16); 2248 2249 /************************************************* 2250 * Create resources * 2251 *************************************************/ 2252 2253 /* Clock Sources for Pixel Clock*/ 2254 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2255 dcn32_clock_source_create(ctx, ctx->dc_bios, 2256 CLOCK_SOURCE_COMBO_PHY_PLL0, 2257 &clk_src_regs[0], false); 2258 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2259 dcn32_clock_source_create(ctx, ctx->dc_bios, 2260 CLOCK_SOURCE_COMBO_PHY_PLL1, 2261 &clk_src_regs[1], false); 2262 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2263 dcn32_clock_source_create(ctx, ctx->dc_bios, 2264 CLOCK_SOURCE_COMBO_PHY_PLL2, 2265 &clk_src_regs[2], false); 2266 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2267 dcn32_clock_source_create(ctx, ctx->dc_bios, 2268 CLOCK_SOURCE_COMBO_PHY_PLL3, 2269 &clk_src_regs[3], false); 2270 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2271 dcn32_clock_source_create(ctx, ctx->dc_bios, 2272 CLOCK_SOURCE_COMBO_PHY_PLL4, 2273 &clk_src_regs[4], false); 2274 2275 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2276 2277 /* todo: not reuse phy_pll registers */ 2278 pool->base.dp_clock_source = 2279 dcn32_clock_source_create(ctx, ctx->dc_bios, 2280 CLOCK_SOURCE_ID_DP_DTO, 2281 &clk_src_regs[0], true); 2282 2283 for (i = 0; i < pool->base.clk_src_count; i++) { 2284 if (pool->base.clock_sources[i] == NULL) { 2285 dm_error("DC: failed to create clock sources!\n"); 2286 BREAK_TO_DEBUGGER(); 2287 goto create_fail; 2288 } 2289 } 2290 2291 /* DCCG */ 2292 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2293 if (pool->base.dccg == NULL) { 2294 dm_error("DC: failed to create dccg!\n"); 2295 BREAK_TO_DEBUGGER(); 2296 goto create_fail; 2297 } 2298 2299 /* DML */ 2300 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2301 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2302 2303 /* IRQ Service */ 2304 init_data.ctx = dc->ctx; 2305 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2306 if (!pool->base.irqs) 2307 goto create_fail; 2308 2309 /* HUBBUB */ 2310 pool->base.hubbub = dcn32_hubbub_create(ctx); 2311 if (pool->base.hubbub == NULL) { 2312 BREAK_TO_DEBUGGER(); 2313 dm_error("DC: failed to create hubbub!\n"); 2314 goto create_fail; 2315 } 2316 2317 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2318 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2319 2320 /* if pipe is disabled, skip instance of HW pipe, 2321 * i.e, skip ASIC register instance 2322 */ 2323 if (pipe_fuses & 1 << i) 2324 continue; 2325 2326 /* HUBPs */ 2327 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2328 if (pool->base.hubps[j] == NULL) { 2329 BREAK_TO_DEBUGGER(); 2330 dm_error( 2331 "DC: failed to create hubps!\n"); 2332 goto create_fail; 2333 } 2334 2335 /* DPPs */ 2336 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2337 if (pool->base.dpps[j] == NULL) { 2338 BREAK_TO_DEBUGGER(); 2339 dm_error( 2340 "DC: failed to create dpps!\n"); 2341 goto create_fail; 2342 } 2343 2344 /* OPPs */ 2345 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2346 if (pool->base.opps[j] == NULL) { 2347 BREAK_TO_DEBUGGER(); 2348 dm_error( 2349 "DC: failed to create output pixel processor!\n"); 2350 goto create_fail; 2351 } 2352 2353 /* TGs */ 2354 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2355 ctx, i); 2356 if (pool->base.timing_generators[j] == NULL) { 2357 BREAK_TO_DEBUGGER(); 2358 dm_error("DC: failed to create tg!\n"); 2359 goto create_fail; 2360 } 2361 2362 /* ABMs */ 2363 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2364 &abm_regs[i], 2365 &abm_shift, 2366 &abm_mask); 2367 if (pool->base.multiple_abms[j] == NULL) { 2368 dm_error("DC: failed to create abm for pipe %d!\n", i); 2369 BREAK_TO_DEBUGGER(); 2370 goto create_fail; 2371 } 2372 2373 /* index for resource pool arrays for next valid pipe */ 2374 j++; 2375 } 2376 2377 /* PSR */ 2378 pool->base.psr = dmub_psr_create(ctx); 2379 if (pool->base.psr == NULL) { 2380 dm_error("DC: failed to create psr obj!\n"); 2381 BREAK_TO_DEBUGGER(); 2382 goto create_fail; 2383 } 2384 2385 /* MPCCs */ 2386 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2387 if (pool->base.mpc == NULL) { 2388 BREAK_TO_DEBUGGER(); 2389 dm_error("DC: failed to create mpc!\n"); 2390 goto create_fail; 2391 } 2392 2393 /* DSCs */ 2394 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2395 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2396 if (pool->base.dscs[i] == NULL) { 2397 BREAK_TO_DEBUGGER(); 2398 dm_error("DC: failed to create display stream compressor %d!\n", i); 2399 goto create_fail; 2400 } 2401 } 2402 2403 /* DWB */ 2404 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2405 BREAK_TO_DEBUGGER(); 2406 dm_error("DC: failed to create dwbc!\n"); 2407 goto create_fail; 2408 } 2409 2410 /* MMHUBBUB */ 2411 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2412 BREAK_TO_DEBUGGER(); 2413 dm_error("DC: failed to create mcif_wb!\n"); 2414 goto create_fail; 2415 } 2416 2417 /* AUX and I2C */ 2418 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2419 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2420 if (pool->base.engines[i] == NULL) { 2421 BREAK_TO_DEBUGGER(); 2422 dm_error( 2423 "DC:failed to create aux engine!!\n"); 2424 goto create_fail; 2425 } 2426 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2427 if (pool->base.hw_i2cs[i] == NULL) { 2428 BREAK_TO_DEBUGGER(); 2429 dm_error( 2430 "DC:failed to create hw i2c!!\n"); 2431 goto create_fail; 2432 } 2433 pool->base.sw_i2cs[i] = NULL; 2434 } 2435 2436 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2437 if (!resource_construct(num_virtual_links, dc, &pool->base, 2438 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2439 &res_create_funcs : &res_create_maximus_funcs))) 2440 goto create_fail; 2441 2442 /* HW Sequencer init functions and Plane caps */ 2443 dcn32_hw_sequencer_init_functions(dc); 2444 2445 dc->caps.max_planes = pool->base.pipe_count; 2446 2447 for (i = 0; i < dc->caps.max_planes; ++i) 2448 dc->caps.planes[i] = plane_cap; 2449 2450 dc->cap_funcs = cap_funcs; 2451 2452 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2453 ddc_init_data.ctx = dc->ctx; 2454 ddc_init_data.link = NULL; 2455 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2456 ddc_init_data.id.enum_id = 0; 2457 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2458 pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2459 } else { 2460 pool->base.oem_device = NULL; 2461 } 2462 2463 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2464 dc->config.sdpif_request_limit_words_per_umc = 16; 2465 2466 DC_FP_END(); 2467 2468 return true; 2469 2470 create_fail: 2471 2472 DC_FP_END(); 2473 2474 dcn32_resource_destruct(pool); 2475 2476 return false; 2477 } 2478 2479 struct resource_pool *dcn32_create_resource_pool( 2480 const struct dc_init_data *init_data, 2481 struct dc *dc) 2482 { 2483 struct dcn32_resource_pool *pool = 2484 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2485 2486 if (!pool) 2487 return NULL; 2488 2489 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2490 return &pool->base; 2491 2492 BREAK_TO_DEBUGGER(); 2493 kfree(pool); 2494 return NULL; 2495 } 2496 2497 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2498 struct resource_context *res_ctx, 2499 const struct resource_pool *pool, 2500 const struct pipe_ctx *primary_pipe) 2501 { 2502 int i; 2503 struct pipe_ctx *secondary_pipe = NULL; 2504 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2505 int primary_index, preferred_pipe_idx; 2506 struct pipe_ctx *old_primary_pipe = NULL; 2507 2508 /* 2509 * Modified from find_idle_secondary_pipe 2510 * With windowed MPO and ODM, we want to avoid the case where we want a 2511 * free pipe for the left side but the free pipe is being used on the 2512 * right side. 2513 * Add check on current_state if the primary_pipe is the left side, 2514 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2515 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2516 * - If so, then don't use this pipe 2517 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2518 * - in this case, the primary pipe has already gotten a free pipe for the 2519 * MPO window in the left 2520 * - when it tries to get a free pipe for the MPO window on the right, 2521 * it will see that it is already assigned to the right side 2522 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2523 * free pipe, since it will be for the right side. So add an 2524 * additional condition, that skipping the free pipe on the right only 2525 * applies if the primary pipe has no bottom pipe currently assigned 2526 */ 2527 if (primary_pipe) { 2528 primary_index = primary_pipe->pipe_idx; 2529 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2530 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2531 && (!primary_pipe->bottom_pipe)) 2532 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2533 2534 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2535 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2536 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2537 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2538 secondary_pipe->pipe_idx = preferred_pipe_idx; 2539 } 2540 } 2541 2542 /* 2543 * search backwards for the second pipe to keep pipe 2544 * assignment more consistent 2545 */ 2546 if (!secondary_pipe) 2547 for (i = pool->pipe_count - 1; i >= 0; i--) { 2548 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2549 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2550 secondary_pipe = &res_ctx->pipe_ctx[i]; 2551 secondary_pipe->pipe_idx = i; 2552 break; 2553 } 2554 } 2555 2556 return secondary_pipe; 2557 } 2558 2559 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2560 struct dc_state *state, 2561 const struct resource_pool *pool, 2562 struct dc_stream_state *stream, 2563 struct pipe_ctx *head_pipe) 2564 { 2565 struct resource_context *res_ctx = &state->res_ctx; 2566 struct pipe_ctx *idle_pipe, *pipe; 2567 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2568 int head_index; 2569 2570 if (!head_pipe) 2571 ASSERT(0); 2572 2573 /* 2574 * Modified from dcn20_acquire_idle_pipe_for_layer 2575 * Check if head_pipe in old_context already has bottom_pipe allocated. 2576 * - If so, check if that pipe is available in the current context. 2577 * -- If so, reuse pipe from old_context 2578 */ 2579 head_index = head_pipe->pipe_idx; 2580 pipe = &old_ctx->pipe_ctx[head_index]; 2581 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2582 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2583 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2584 } else { 2585 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2586 if (!idle_pipe) 2587 return NULL; 2588 } 2589 2590 idle_pipe->stream = head_pipe->stream; 2591 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2592 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2593 2594 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2595 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2596 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2597 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2598 2599 return idle_pipe; 2600 } 2601 2602 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2603 { 2604 /* 2605 * DCN32 and DCN321 SKUs may have different sizes for MALL 2606 * but we may not be able to access all the MALL space. 2607 * If the num_chans is power of 2, then we can access all 2608 * of the available MALL space. Otherwise, we can only 2609 * access: 2610 * 2611 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2612 * ((2^floor(log2(num_chans)))/num_chans) 2613 * 2614 * Calculating the MALL sizes for all available SKUs, we 2615 * have come up with the follow simplified check. 2616 * - we have max_chans which provides the max MALL size. 2617 * Each chans supports 4MB of MALL so: 2618 * 2619 * total_cache_size_in_bytes = max_chans * 4 MB 2620 * 2621 * - we have avail_chans which shows the number of channels 2622 * we can use if we can't access the entire MALL space. 2623 * It is generally half of max_chans 2624 * - so we use the following checks: 2625 * 2626 * if (num_chans == max_chans), return max_chans 2627 * if (num_chans < max_chans), return avail_chans 2628 * 2629 * - exception is GC_11_0_0 where we can't access max_chans, 2630 * so we define max_avail_chans as the maximum available 2631 * MALL space 2632 * 2633 */ 2634 int gc_11_0_0_max_chans = 48; 2635 int gc_11_0_0_max_avail_chans = 32; 2636 int gc_11_0_0_avail_chans = 16; 2637 int gc_11_0_3_max_chans = 16; 2638 int gc_11_0_3_avail_chans = 8; 2639 int gc_11_0_2_max_chans = 8; 2640 int gc_11_0_2_avail_chans = 4; 2641 2642 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2643 return (num_chans == gc_11_0_0_max_chans) ? 2644 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2645 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2646 return (num_chans == gc_11_0_2_max_chans) ? 2647 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2648 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2649 return (num_chans == gc_11_0_3_max_chans) ? 2650 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2651 } 2652 } 2653