1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dc_link_dp.h" 61 #include "dcn31/dcn31_apg.h" 62 #include "dcn31/dcn31_dio_link_encoder.h" 63 #include "dcn32/dcn32_dio_link_encoder.h" 64 #include "dce/dce_clock_source.h" 65 #include "dce/dce_audio.h" 66 #include "dce/dce_hwseq.h" 67 #include "clk_mgr.h" 68 #include "virtual/virtual_stream_encoder.h" 69 #include "dml/display_mode_vba.h" 70 #include "dcn32/dcn32_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dc_link_ddc.h" 73 #include "dcn31/dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn32/dcn32_mmhubbub.h" 77 78 #include "dcn/dcn_3_2_0_offset.h" 79 #include "dcn/dcn_3_2_0_sh_mask.h" 80 #include "nbio/nbio_4_3_0_offset.h" 81 82 #include "reg_helper.h" 83 #include "dce/dmub_abm.h" 84 #include "dce/dmub_psr.h" 85 #include "dce/dce_aux.h" 86 #include "dce/dce_i2c.h" 87 88 #include "dml/dcn30/display_mode_vba_30.h" 89 #include "vm_helper.h" 90 #include "dcn20/dcn20_vmid.h" 91 #include "dml/dcn32/dcn32_fpu.h" 92 93 #define DC_LOGGER_INIT(logger) 94 95 enum dcn32_clk_src_array_id { 96 DCN32_CLK_SRC_PLL0, 97 DCN32_CLK_SRC_PLL1, 98 DCN32_CLK_SRC_PLL2, 99 DCN32_CLK_SRC_PLL3, 100 DCN32_CLK_SRC_PLL4, 101 DCN32_CLK_SRC_TOTAL 102 }; 103 104 /* begin ********************* 105 * macros to expend register list macro defined in HW object header file 106 */ 107 108 /* DCN */ 109 /* TODO awful hack. fixup dcn20_dwb.h */ 110 #undef BASE_INNER 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id) \ 119 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 120 121 #define SR_ARR_INIT(reg_name, id, value) \ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SR_ARR_I2C(reg_name, id) \ 133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 134 135 #define SRI_ARR_I2C(reg_name, block, id)\ 136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 reg ## block ## id ## _ ## reg_name 138 139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## _ ## reg_name 142 143 #define SRI2(reg_name, block, id)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 #define SRI2_ARR(reg_name, block, id)\ 147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_ARR_2(reg_name, block, id, inst)\ 159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 722 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 723 .enable_double_buffered_dsc_pg_support = true, 724 .enable_dp_dig_pixel_rate_div_policy = 1, 725 .allow_sw_cursor_fallback = false, 726 .alloc_extra_way_for_cursor = true, 727 .min_prefetch_in_strobe_ns = 60000, // 60us 728 }; 729 730 static const struct dc_debug_options debug_defaults_diags = { 731 .disable_dmcu = true, 732 .force_abm_enable = false, 733 .timing_trace = true, 734 .clock_trace = true, 735 .disable_dpp_power_gate = true, 736 .disable_hubp_power_gate = true, 737 .disable_dsc_power_gate = true, 738 .disable_clock_gate = true, 739 .disable_pplib_clock_request = true, 740 .disable_pplib_wm_range = true, 741 .disable_stutter = false, 742 .scl_reset_length10 = true, 743 .dwb_fi_phase = -1, // -1 = disable 744 .dmub_command_table = true, 745 .enable_tri_buf = true, 746 .use_max_lb = true, 747 .force_disable_subvp = true 748 }; 749 750 static struct dce_aux *dcn32_aux_engine_create( 751 struct dc_context *ctx, 752 uint32_t inst) 753 { 754 struct aux_engine_dce110 *aux_engine = 755 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 756 757 if (!aux_engine) 758 return NULL; 759 760 #undef REG_STRUCT 761 #define REG_STRUCT aux_engine_regs 762 aux_engine_regs_init(0), 763 aux_engine_regs_init(1), 764 aux_engine_regs_init(2), 765 aux_engine_regs_init(3), 766 aux_engine_regs_init(4); 767 768 dce110_aux_engine_construct(aux_engine, ctx, inst, 769 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 770 &aux_engine_regs[inst], 771 &aux_mask, 772 &aux_shift, 773 ctx->dc->caps.extended_aux_timeout_support); 774 775 return &aux_engine->base; 776 } 777 #define i2c_inst_regs_init(id)\ 778 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 779 780 static struct dce_i2c_registers i2c_hw_regs[5]; 781 782 static const struct dce_i2c_shift i2c_shifts = { 783 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 784 }; 785 786 static const struct dce_i2c_mask i2c_masks = { 787 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 788 }; 789 790 static struct dce_i2c_hw *dcn32_i2c_hw_create( 791 struct dc_context *ctx, 792 uint32_t inst) 793 { 794 struct dce_i2c_hw *dce_i2c_hw = 795 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 796 797 if (!dce_i2c_hw) 798 return NULL; 799 800 #undef REG_STRUCT 801 #define REG_STRUCT i2c_hw_regs 802 i2c_inst_regs_init(1), 803 i2c_inst_regs_init(2), 804 i2c_inst_regs_init(3), 805 i2c_inst_regs_init(4), 806 i2c_inst_regs_init(5); 807 808 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 809 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 810 811 return dce_i2c_hw; 812 } 813 814 static struct clock_source *dcn32_clock_source_create( 815 struct dc_context *ctx, 816 struct dc_bios *bios, 817 enum clock_source_id id, 818 const struct dce110_clk_src_regs *regs, 819 bool dp_clk_src) 820 { 821 struct dce110_clk_src *clk_src = 822 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 823 824 if (!clk_src) 825 return NULL; 826 827 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 828 regs, &cs_shift, &cs_mask)) { 829 clk_src->base.dp_clk_src = dp_clk_src; 830 return &clk_src->base; 831 } 832 833 BREAK_TO_DEBUGGER(); 834 return NULL; 835 } 836 837 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 838 { 839 int i; 840 841 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 842 GFP_KERNEL); 843 844 if (!hubbub2) 845 return NULL; 846 847 #undef REG_STRUCT 848 #define REG_STRUCT hubbub_reg 849 hubbub_reg_init(); 850 851 #undef REG_STRUCT 852 #define REG_STRUCT vmid_regs 853 vmid_regs_init(0), 854 vmid_regs_init(1), 855 vmid_regs_init(2), 856 vmid_regs_init(3), 857 vmid_regs_init(4), 858 vmid_regs_init(5), 859 vmid_regs_init(6), 860 vmid_regs_init(7), 861 vmid_regs_init(8), 862 vmid_regs_init(9), 863 vmid_regs_init(10), 864 vmid_regs_init(11), 865 vmid_regs_init(12), 866 vmid_regs_init(13), 867 vmid_regs_init(14), 868 vmid_regs_init(15); 869 870 hubbub32_construct(hubbub2, ctx, 871 &hubbub_reg, 872 &hubbub_shift, 873 &hubbub_mask, 874 ctx->dc->dml.ip.det_buffer_size_kbytes, 875 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 876 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 877 878 879 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 880 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 881 882 vmid->ctx = ctx; 883 884 vmid->regs = &vmid_regs[i]; 885 vmid->shifts = &vmid_shifts; 886 vmid->masks = &vmid_masks; 887 } 888 889 return &hubbub2->base; 890 } 891 892 static struct hubp *dcn32_hubp_create( 893 struct dc_context *ctx, 894 uint32_t inst) 895 { 896 struct dcn20_hubp *hubp2 = 897 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 898 899 if (!hubp2) 900 return NULL; 901 902 #undef REG_STRUCT 903 #define REG_STRUCT hubp_regs 904 hubp_regs_init(0), 905 hubp_regs_init(1), 906 hubp_regs_init(2), 907 hubp_regs_init(3); 908 909 if (hubp32_construct(hubp2, ctx, inst, 910 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 911 return &hubp2->base; 912 913 BREAK_TO_DEBUGGER(); 914 kfree(hubp2); 915 return NULL; 916 } 917 918 static void dcn32_dpp_destroy(struct dpp **dpp) 919 { 920 kfree(TO_DCN30_DPP(*dpp)); 921 *dpp = NULL; 922 } 923 924 static struct dpp *dcn32_dpp_create( 925 struct dc_context *ctx, 926 uint32_t inst) 927 { 928 struct dcn3_dpp *dpp3 = 929 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 930 931 if (!dpp3) 932 return NULL; 933 934 #undef REG_STRUCT 935 #define REG_STRUCT dpp_regs 936 dpp_regs_init(0), 937 dpp_regs_init(1), 938 dpp_regs_init(2), 939 dpp_regs_init(3); 940 941 if (dpp32_construct(dpp3, ctx, inst, 942 &dpp_regs[inst], &tf_shift, &tf_mask)) 943 return &dpp3->base; 944 945 BREAK_TO_DEBUGGER(); 946 kfree(dpp3); 947 return NULL; 948 } 949 950 static struct mpc *dcn32_mpc_create( 951 struct dc_context *ctx, 952 int num_mpcc, 953 int num_rmu) 954 { 955 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 956 GFP_KERNEL); 957 958 if (!mpc30) 959 return NULL; 960 961 #undef REG_STRUCT 962 #define REG_STRUCT mpc_regs 963 dcn_mpc_regs_init(); 964 965 dcn32_mpc_construct(mpc30, ctx, 966 &mpc_regs, 967 &mpc_shift, 968 &mpc_mask, 969 num_mpcc, 970 num_rmu); 971 972 return &mpc30->base; 973 } 974 975 static struct output_pixel_processor *dcn32_opp_create( 976 struct dc_context *ctx, uint32_t inst) 977 { 978 struct dcn20_opp *opp2 = 979 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 980 981 if (!opp2) { 982 BREAK_TO_DEBUGGER(); 983 return NULL; 984 } 985 986 #undef REG_STRUCT 987 #define REG_STRUCT opp_regs 988 opp_regs_init(0), 989 opp_regs_init(1), 990 opp_regs_init(2), 991 opp_regs_init(3); 992 993 dcn20_opp_construct(opp2, ctx, inst, 994 &opp_regs[inst], &opp_shift, &opp_mask); 995 return &opp2->base; 996 } 997 998 999 static struct timing_generator *dcn32_timing_generator_create( 1000 struct dc_context *ctx, 1001 uint32_t instance) 1002 { 1003 struct optc *tgn10 = 1004 kzalloc(sizeof(struct optc), GFP_KERNEL); 1005 1006 if (!tgn10) 1007 return NULL; 1008 1009 #undef REG_STRUCT 1010 #define REG_STRUCT optc_regs 1011 optc_regs_init(0), 1012 optc_regs_init(1), 1013 optc_regs_init(2), 1014 optc_regs_init(3); 1015 1016 tgn10->base.inst = instance; 1017 tgn10->base.ctx = ctx; 1018 1019 tgn10->tg_regs = &optc_regs[instance]; 1020 tgn10->tg_shift = &optc_shift; 1021 tgn10->tg_mask = &optc_mask; 1022 1023 dcn32_timing_generator_init(tgn10); 1024 1025 return &tgn10->base; 1026 } 1027 1028 static const struct encoder_feature_support link_enc_feature = { 1029 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1030 .max_hdmi_pixel_clock = 600000, 1031 .hdmi_ycbcr420_supported = true, 1032 .dp_ycbcr420_supported = true, 1033 .fec_supported = true, 1034 .flags.bits.IS_HBR2_CAPABLE = true, 1035 .flags.bits.IS_HBR3_CAPABLE = true, 1036 .flags.bits.IS_TPS3_CAPABLE = true, 1037 .flags.bits.IS_TPS4_CAPABLE = true 1038 }; 1039 1040 static struct link_encoder *dcn32_link_encoder_create( 1041 struct dc_context *ctx, 1042 const struct encoder_init_data *enc_init_data) 1043 { 1044 struct dcn20_link_encoder *enc20 = 1045 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1046 1047 if (!enc20) 1048 return NULL; 1049 1050 #undef REG_STRUCT 1051 #define REG_STRUCT link_enc_aux_regs 1052 aux_regs_init(0), 1053 aux_regs_init(1), 1054 aux_regs_init(2), 1055 aux_regs_init(3), 1056 aux_regs_init(4); 1057 1058 #undef REG_STRUCT 1059 #define REG_STRUCT link_enc_hpd_regs 1060 hpd_regs_init(0), 1061 hpd_regs_init(1), 1062 hpd_regs_init(2), 1063 hpd_regs_init(3), 1064 hpd_regs_init(4); 1065 1066 #undef REG_STRUCT 1067 #define REG_STRUCT link_enc_regs 1068 link_regs_init(0, A), 1069 link_regs_init(1, B), 1070 link_regs_init(2, C), 1071 link_regs_init(3, D), 1072 link_regs_init(4, E); 1073 1074 dcn32_link_encoder_construct(enc20, 1075 enc_init_data, 1076 &link_enc_feature, 1077 &link_enc_regs[enc_init_data->transmitter], 1078 &link_enc_aux_regs[enc_init_data->channel - 1], 1079 &link_enc_hpd_regs[enc_init_data->hpd_source], 1080 &le_shift, 1081 &le_mask); 1082 1083 return &enc20->enc10.base; 1084 } 1085 1086 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1087 { 1088 struct dcn31_panel_cntl *panel_cntl = 1089 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1090 1091 if (!panel_cntl) 1092 return NULL; 1093 1094 dcn31_panel_cntl_construct(panel_cntl, init_data); 1095 1096 return &panel_cntl->base; 1097 } 1098 1099 static void read_dce_straps( 1100 struct dc_context *ctx, 1101 struct resource_straps *straps) 1102 { 1103 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1104 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1105 1106 } 1107 1108 static struct audio *dcn32_create_audio( 1109 struct dc_context *ctx, unsigned int inst) 1110 { 1111 1112 #undef REG_STRUCT 1113 #define REG_STRUCT audio_regs 1114 audio_regs_init(0), 1115 audio_regs_init(1), 1116 audio_regs_init(2), 1117 audio_regs_init(3), 1118 audio_regs_init(4); 1119 1120 return dce_audio_create(ctx, inst, 1121 &audio_regs[inst], &audio_shift, &audio_mask); 1122 } 1123 1124 static struct vpg *dcn32_vpg_create( 1125 struct dc_context *ctx, 1126 uint32_t inst) 1127 { 1128 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1129 1130 if (!vpg3) 1131 return NULL; 1132 1133 #undef REG_STRUCT 1134 #define REG_STRUCT vpg_regs 1135 vpg_regs_init(0), 1136 vpg_regs_init(1), 1137 vpg_regs_init(2), 1138 vpg_regs_init(3), 1139 vpg_regs_init(4), 1140 vpg_regs_init(5), 1141 vpg_regs_init(6), 1142 vpg_regs_init(7), 1143 vpg_regs_init(8), 1144 vpg_regs_init(9); 1145 1146 vpg3_construct(vpg3, ctx, inst, 1147 &vpg_regs[inst], 1148 &vpg_shift, 1149 &vpg_mask); 1150 1151 return &vpg3->base; 1152 } 1153 1154 static struct afmt *dcn32_afmt_create( 1155 struct dc_context *ctx, 1156 uint32_t inst) 1157 { 1158 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1159 1160 if (!afmt3) 1161 return NULL; 1162 1163 #undef REG_STRUCT 1164 #define REG_STRUCT afmt_regs 1165 afmt_regs_init(0), 1166 afmt_regs_init(1), 1167 afmt_regs_init(2), 1168 afmt_regs_init(3), 1169 afmt_regs_init(4), 1170 afmt_regs_init(5); 1171 1172 afmt3_construct(afmt3, ctx, inst, 1173 &afmt_regs[inst], 1174 &afmt_shift, 1175 &afmt_mask); 1176 1177 return &afmt3->base; 1178 } 1179 1180 static struct apg *dcn31_apg_create( 1181 struct dc_context *ctx, 1182 uint32_t inst) 1183 { 1184 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1185 1186 if (!apg31) 1187 return NULL; 1188 1189 #undef REG_STRUCT 1190 #define REG_STRUCT apg_regs 1191 apg_regs_init(0), 1192 apg_regs_init(1), 1193 apg_regs_init(2), 1194 apg_regs_init(3); 1195 1196 apg31_construct(apg31, ctx, inst, 1197 &apg_regs[inst], 1198 &apg_shift, 1199 &apg_mask); 1200 1201 return &apg31->base; 1202 } 1203 1204 static struct stream_encoder *dcn32_stream_encoder_create( 1205 enum engine_id eng_id, 1206 struct dc_context *ctx) 1207 { 1208 struct dcn10_stream_encoder *enc1; 1209 struct vpg *vpg; 1210 struct afmt *afmt; 1211 int vpg_inst; 1212 int afmt_inst; 1213 1214 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1215 if (eng_id <= ENGINE_ID_DIGF) { 1216 vpg_inst = eng_id; 1217 afmt_inst = eng_id; 1218 } else 1219 return NULL; 1220 1221 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1222 vpg = dcn32_vpg_create(ctx, vpg_inst); 1223 afmt = dcn32_afmt_create(ctx, afmt_inst); 1224 1225 if (!enc1 || !vpg || !afmt) { 1226 kfree(enc1); 1227 kfree(vpg); 1228 kfree(afmt); 1229 return NULL; 1230 } 1231 1232 #undef REG_STRUCT 1233 #define REG_STRUCT stream_enc_regs 1234 stream_enc_regs_init(0), 1235 stream_enc_regs_init(1), 1236 stream_enc_regs_init(2), 1237 stream_enc_regs_init(3), 1238 stream_enc_regs_init(4); 1239 1240 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1241 eng_id, vpg, afmt, 1242 &stream_enc_regs[eng_id], 1243 &se_shift, &se_mask); 1244 1245 return &enc1->base; 1246 } 1247 1248 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1249 enum engine_id eng_id, 1250 struct dc_context *ctx) 1251 { 1252 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1253 struct vpg *vpg; 1254 struct apg *apg; 1255 uint32_t hpo_dp_inst; 1256 uint32_t vpg_inst; 1257 uint32_t apg_inst; 1258 1259 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1260 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1261 1262 /* Mapping of VPG register blocks to HPO DP block instance: 1263 * VPG[6] -> HPO_DP[0] 1264 * VPG[7] -> HPO_DP[1] 1265 * VPG[8] -> HPO_DP[2] 1266 * VPG[9] -> HPO_DP[3] 1267 */ 1268 vpg_inst = hpo_dp_inst + 6; 1269 1270 /* Mapping of APG register blocks to HPO DP block instance: 1271 * APG[0] -> HPO_DP[0] 1272 * APG[1] -> HPO_DP[1] 1273 * APG[2] -> HPO_DP[2] 1274 * APG[3] -> HPO_DP[3] 1275 */ 1276 apg_inst = hpo_dp_inst; 1277 1278 /* allocate HPO stream encoder and create VPG sub-block */ 1279 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1280 vpg = dcn32_vpg_create(ctx, vpg_inst); 1281 apg = dcn31_apg_create(ctx, apg_inst); 1282 1283 if (!hpo_dp_enc31 || !vpg || !apg) { 1284 kfree(hpo_dp_enc31); 1285 kfree(vpg); 1286 kfree(apg); 1287 return NULL; 1288 } 1289 1290 #undef REG_STRUCT 1291 #define REG_STRUCT hpo_dp_stream_enc_regs 1292 hpo_dp_stream_encoder_reg_init(0), 1293 hpo_dp_stream_encoder_reg_init(1), 1294 hpo_dp_stream_encoder_reg_init(2), 1295 hpo_dp_stream_encoder_reg_init(3); 1296 1297 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1298 hpo_dp_inst, eng_id, vpg, apg, 1299 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1300 &hpo_dp_se_shift, &hpo_dp_se_mask); 1301 1302 return &hpo_dp_enc31->base; 1303 } 1304 1305 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1306 uint8_t inst, 1307 struct dc_context *ctx) 1308 { 1309 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1310 1311 /* allocate HPO link encoder */ 1312 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1313 1314 #undef REG_STRUCT 1315 #define REG_STRUCT hpo_dp_link_enc_regs 1316 hpo_dp_link_encoder_reg_init(0), 1317 hpo_dp_link_encoder_reg_init(1); 1318 1319 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1320 &hpo_dp_link_enc_regs[inst], 1321 &hpo_dp_le_shift, &hpo_dp_le_mask); 1322 1323 return &hpo_dp_enc31->base; 1324 } 1325 1326 static struct dce_hwseq *dcn32_hwseq_create( 1327 struct dc_context *ctx) 1328 { 1329 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1330 1331 #undef REG_STRUCT 1332 #define REG_STRUCT hwseq_reg 1333 hwseq_reg_init(); 1334 1335 if (hws) { 1336 hws->ctx = ctx; 1337 hws->regs = &hwseq_reg; 1338 hws->shifts = &hwseq_shift; 1339 hws->masks = &hwseq_mask; 1340 } 1341 return hws; 1342 } 1343 static const struct resource_create_funcs res_create_funcs = { 1344 .read_dce_straps = read_dce_straps, 1345 .create_audio = dcn32_create_audio, 1346 .create_stream_encoder = dcn32_stream_encoder_create, 1347 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1348 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1349 .create_hwseq = dcn32_hwseq_create, 1350 }; 1351 1352 static const struct resource_create_funcs res_create_maximus_funcs = { 1353 .read_dce_straps = NULL, 1354 .create_audio = NULL, 1355 .create_stream_encoder = NULL, 1356 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1357 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1358 .create_hwseq = dcn32_hwseq_create, 1359 }; 1360 1361 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1362 { 1363 unsigned int i; 1364 1365 for (i = 0; i < pool->base.stream_enc_count; i++) { 1366 if (pool->base.stream_enc[i] != NULL) { 1367 if (pool->base.stream_enc[i]->vpg != NULL) { 1368 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1369 pool->base.stream_enc[i]->vpg = NULL; 1370 } 1371 if (pool->base.stream_enc[i]->afmt != NULL) { 1372 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1373 pool->base.stream_enc[i]->afmt = NULL; 1374 } 1375 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1376 pool->base.stream_enc[i] = NULL; 1377 } 1378 } 1379 1380 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1381 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1382 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1383 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1384 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1385 } 1386 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1387 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1388 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1389 } 1390 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1391 pool->base.hpo_dp_stream_enc[i] = NULL; 1392 } 1393 } 1394 1395 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1396 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1397 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1398 pool->base.hpo_dp_link_enc[i] = NULL; 1399 } 1400 } 1401 1402 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1403 if (pool->base.dscs[i] != NULL) 1404 dcn20_dsc_destroy(&pool->base.dscs[i]); 1405 } 1406 1407 if (pool->base.mpc != NULL) { 1408 kfree(TO_DCN20_MPC(pool->base.mpc)); 1409 pool->base.mpc = NULL; 1410 } 1411 if (pool->base.hubbub != NULL) { 1412 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1413 pool->base.hubbub = NULL; 1414 } 1415 for (i = 0; i < pool->base.pipe_count; i++) { 1416 if (pool->base.dpps[i] != NULL) 1417 dcn32_dpp_destroy(&pool->base.dpps[i]); 1418 1419 if (pool->base.ipps[i] != NULL) 1420 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1421 1422 if (pool->base.hubps[i] != NULL) { 1423 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1424 pool->base.hubps[i] = NULL; 1425 } 1426 1427 if (pool->base.irqs != NULL) { 1428 dal_irq_service_destroy(&pool->base.irqs); 1429 } 1430 } 1431 1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1433 if (pool->base.engines[i] != NULL) 1434 dce110_engine_destroy(&pool->base.engines[i]); 1435 if (pool->base.hw_i2cs[i] != NULL) { 1436 kfree(pool->base.hw_i2cs[i]); 1437 pool->base.hw_i2cs[i] = NULL; 1438 } 1439 if (pool->base.sw_i2cs[i] != NULL) { 1440 kfree(pool->base.sw_i2cs[i]); 1441 pool->base.sw_i2cs[i] = NULL; 1442 } 1443 } 1444 1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1446 if (pool->base.opps[i] != NULL) 1447 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1448 } 1449 1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1451 if (pool->base.timing_generators[i] != NULL) { 1452 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1453 pool->base.timing_generators[i] = NULL; 1454 } 1455 } 1456 1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1458 if (pool->base.dwbc[i] != NULL) { 1459 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1460 pool->base.dwbc[i] = NULL; 1461 } 1462 if (pool->base.mcif_wb[i] != NULL) { 1463 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1464 pool->base.mcif_wb[i] = NULL; 1465 } 1466 } 1467 1468 for (i = 0; i < pool->base.audio_count; i++) { 1469 if (pool->base.audios[i]) 1470 dce_aud_destroy(&pool->base.audios[i]); 1471 } 1472 1473 for (i = 0; i < pool->base.clk_src_count; i++) { 1474 if (pool->base.clock_sources[i] != NULL) { 1475 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1476 pool->base.clock_sources[i] = NULL; 1477 } 1478 } 1479 1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1481 if (pool->base.mpc_lut[i] != NULL) { 1482 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1483 pool->base.mpc_lut[i] = NULL; 1484 } 1485 if (pool->base.mpc_shaper[i] != NULL) { 1486 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1487 pool->base.mpc_shaper[i] = NULL; 1488 } 1489 } 1490 1491 if (pool->base.dp_clock_source != NULL) { 1492 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1493 pool->base.dp_clock_source = NULL; 1494 } 1495 1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1497 if (pool->base.multiple_abms[i] != NULL) 1498 dce_abm_destroy(&pool->base.multiple_abms[i]); 1499 } 1500 1501 if (pool->base.psr != NULL) 1502 dmub_psr_destroy(&pool->base.psr); 1503 1504 if (pool->base.dccg != NULL) 1505 dcn_dccg_destroy(&pool->base.dccg); 1506 1507 if (pool->base.oem_device != NULL) 1508 dal_ddc_service_destroy(&pool->base.oem_device); 1509 } 1510 1511 1512 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1513 { 1514 int i; 1515 uint32_t dwb_count = pool->res_cap->num_dwb; 1516 1517 for (i = 0; i < dwb_count; i++) { 1518 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1519 GFP_KERNEL); 1520 1521 if (!dwbc30) { 1522 dm_error("DC: failed to create dwbc30!\n"); 1523 return false; 1524 } 1525 1526 #undef REG_STRUCT 1527 #define REG_STRUCT dwbc30_regs 1528 dwbc_regs_dcn3_init(0); 1529 1530 dcn30_dwbc_construct(dwbc30, ctx, 1531 &dwbc30_regs[i], 1532 &dwbc30_shift, 1533 &dwbc30_mask, 1534 i); 1535 1536 pool->dwbc[i] = &dwbc30->base; 1537 } 1538 return true; 1539 } 1540 1541 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1542 { 1543 int i; 1544 uint32_t dwb_count = pool->res_cap->num_dwb; 1545 1546 for (i = 0; i < dwb_count; i++) { 1547 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1548 GFP_KERNEL); 1549 1550 if (!mcif_wb30) { 1551 dm_error("DC: failed to create mcif_wb30!\n"); 1552 return false; 1553 } 1554 1555 #undef REG_STRUCT 1556 #define REG_STRUCT mcif_wb30_regs 1557 mcif_wb_regs_dcn3_init(0); 1558 1559 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1560 &mcif_wb30_regs[i], 1561 &mcif_wb30_shift, 1562 &mcif_wb30_mask, 1563 i); 1564 1565 pool->mcif_wb[i] = &mcif_wb30->base; 1566 } 1567 return true; 1568 } 1569 1570 static struct display_stream_compressor *dcn32_dsc_create( 1571 struct dc_context *ctx, uint32_t inst) 1572 { 1573 struct dcn20_dsc *dsc = 1574 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1575 1576 if (!dsc) { 1577 BREAK_TO_DEBUGGER(); 1578 return NULL; 1579 } 1580 1581 #undef REG_STRUCT 1582 #define REG_STRUCT dsc_regs 1583 dsc_regsDCN20_init(0), 1584 dsc_regsDCN20_init(1), 1585 dsc_regsDCN20_init(2), 1586 dsc_regsDCN20_init(3); 1587 1588 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1589 1590 dsc->max_image_width = 6016; 1591 1592 return &dsc->base; 1593 } 1594 1595 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1596 { 1597 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1598 1599 dcn32_resource_destruct(dcn32_pool); 1600 kfree(dcn32_pool); 1601 *pool = NULL; 1602 } 1603 1604 bool dcn32_acquire_post_bldn_3dlut( 1605 struct resource_context *res_ctx, 1606 const struct resource_pool *pool, 1607 int mpcc_id, 1608 struct dc_3dlut **lut, 1609 struct dc_transfer_func **shaper) 1610 { 1611 bool ret = false; 1612 union dc_3dlut_state *state; 1613 1614 ASSERT(*lut == NULL && *shaper == NULL); 1615 *lut = NULL; 1616 *shaper = NULL; 1617 1618 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1619 *lut = pool->mpc_lut[mpcc_id]; 1620 *shaper = pool->mpc_shaper[mpcc_id]; 1621 state = &pool->mpc_lut[mpcc_id]->state; 1622 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1623 ret = true; 1624 } 1625 return ret; 1626 } 1627 1628 bool dcn32_release_post_bldn_3dlut( 1629 struct resource_context *res_ctx, 1630 const struct resource_pool *pool, 1631 struct dc_3dlut **lut, 1632 struct dc_transfer_func **shaper) 1633 { 1634 int i; 1635 bool ret = false; 1636 1637 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1638 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1639 res_ctx->is_mpc_3dlut_acquired[i] = false; 1640 pool->mpc_lut[i]->state.raw = 0; 1641 *lut = NULL; 1642 *shaper = NULL; 1643 ret = true; 1644 break; 1645 } 1646 } 1647 return ret; 1648 } 1649 1650 static void dcn32_enable_phantom_plane(struct dc *dc, 1651 struct dc_state *context, 1652 struct dc_stream_state *phantom_stream, 1653 unsigned int dc_pipe_idx) 1654 { 1655 struct dc_plane_state *phantom_plane = NULL; 1656 struct dc_plane_state *prev_phantom_plane = NULL; 1657 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1658 1659 while (curr_pipe) { 1660 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1661 phantom_plane = prev_phantom_plane; 1662 else 1663 phantom_plane = dc_create_plane_state(dc); 1664 1665 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1666 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1667 sizeof(phantom_plane->scaling_quality)); 1668 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1669 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1670 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1671 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1672 sizeof(phantom_plane->plane_size)); 1673 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1674 sizeof(phantom_plane->tiling_info)); 1675 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1676 phantom_plane->format = curr_pipe->plane_state->format; 1677 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1678 phantom_plane->visible = curr_pipe->plane_state->visible; 1679 1680 /* Shadow pipe has small viewport. */ 1681 phantom_plane->clip_rect.y = 0; 1682 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; 1683 1684 phantom_plane->is_phantom = true; 1685 1686 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1687 1688 curr_pipe = curr_pipe->bottom_pipe; 1689 prev_phantom_plane = phantom_plane; 1690 } 1691 } 1692 1693 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1694 struct dc_state *context, 1695 display_e2e_pipe_params_st *pipes, 1696 unsigned int pipe_cnt, 1697 unsigned int dc_pipe_idx) 1698 { 1699 struct dc_stream_state *phantom_stream = NULL; 1700 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1701 1702 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1703 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1704 phantom_stream->dpms_off = true; 1705 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1706 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1707 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1708 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1709 1710 /* stream has limited viewport and small timing */ 1711 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1712 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1713 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1714 DC_FP_START(); 1715 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1716 DC_FP_END(); 1717 1718 dc_add_stream_to_ctx(dc, context, phantom_stream); 1719 return phantom_stream; 1720 } 1721 1722 // return true if removed piped from ctx, false otherwise 1723 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) 1724 { 1725 int i; 1726 bool removed_pipe = false; 1727 struct dc_plane_state *phantom_plane = NULL; 1728 struct dc_stream_state *phantom_stream = NULL; 1729 1730 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1731 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1732 // build scaling params for phantom pipes 1733 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1734 phantom_plane = pipe->plane_state; 1735 phantom_stream = pipe->stream; 1736 1737 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1738 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1739 1740 /* Ref count is incremented on allocation and also when added to the context. 1741 * Therefore we must call release for the the phantom plane and stream once 1742 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1743 */ 1744 dc_plane_state_release(phantom_plane); 1745 dc_stream_release(phantom_stream); 1746 1747 removed_pipe = true; 1748 } 1749 1750 // Clear all phantom stream info 1751 if (pipe->stream) { 1752 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1753 pipe->stream->mall_stream_config.paired_stream = NULL; 1754 } 1755 1756 if (pipe->plane_state) { 1757 pipe->plane_state->is_phantom = false; 1758 } 1759 } 1760 return removed_pipe; 1761 } 1762 1763 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1764 * require a phantom pipe / stream 1765 */ 1766 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1767 display_e2e_pipe_params_st *pipes, 1768 unsigned int pipe_cnt, 1769 unsigned int index) 1770 { 1771 struct dc_stream_state *phantom_stream = NULL; 1772 unsigned int i; 1773 1774 // The index of the DC pipe passed into this function is guarenteed to 1775 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1776 // already have phantom pipe assigned, etc.) by previous checks. 1777 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1778 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1779 1780 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1781 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1782 1783 // Build scaling params for phantom pipes which were newly added. 1784 // We determine which phantom pipes were added by comparing with 1785 // the phantom stream. 1786 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1787 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1788 pipe->stream->use_dynamic_meta = false; 1789 pipe->plane_state->flip_immediate = false; 1790 if (!resource_build_scaling_params(pipe)) { 1791 // Log / remove phantom pipes since failed to build scaling params 1792 } 1793 } 1794 } 1795 } 1796 1797 bool dcn32_validate_bandwidth(struct dc *dc, 1798 struct dc_state *context, 1799 bool fast_validate) 1800 { 1801 bool out = false; 1802 1803 BW_VAL_TRACE_SETUP(); 1804 1805 int vlevel = 0; 1806 int pipe_cnt = 0; 1807 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1808 struct mall_temp_config mall_temp_config; 1809 1810 /* To handle Freesync properly, setting FreeSync DML parameters 1811 * to its default state for the first stage of validation 1812 */ 1813 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1814 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1815 1816 DC_LOGGER_INIT(dc->ctx->logger); 1817 1818 /* For fast validation, there are situations where a shallow copy of 1819 * of the dc->current_state is created for the validation. In this case 1820 * we want to save and restore the mall config because we always 1821 * teardown subvp at the beginning of validation (and don't attempt 1822 * to add it back if it's fast validation). If we don't restore the 1823 * subvp config in cases of fast validation + shallow copy of the 1824 * dc->current_state, the dc->current_state will have a partially 1825 * removed subvp state when we did not intend to remove it. 1826 */ 1827 if (fast_validate) { 1828 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1829 dcn32_save_mall_state(dc, context, &mall_temp_config); 1830 } 1831 1832 BW_VAL_TRACE_COUNT(); 1833 1834 DC_FP_START(); 1835 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1836 DC_FP_END(); 1837 1838 if (fast_validate) 1839 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1840 1841 if (pipe_cnt == 0) 1842 goto validate_out; 1843 1844 if (!out) 1845 goto validate_fail; 1846 1847 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1848 1849 if (fast_validate) { 1850 BW_VAL_TRACE_SKIP(fast); 1851 goto validate_out; 1852 } 1853 1854 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1855 1856 BW_VAL_TRACE_END_WATERMARKS(); 1857 1858 goto validate_out; 1859 1860 validate_fail: 1861 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1862 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1863 1864 BW_VAL_TRACE_SKIP(fail); 1865 out = false; 1866 1867 validate_out: 1868 kfree(pipes); 1869 1870 BW_VAL_TRACE_FINISH(); 1871 1872 return out; 1873 } 1874 1875 int dcn32_populate_dml_pipes_from_context( 1876 struct dc *dc, struct dc_state *context, 1877 display_e2e_pipe_params_st *pipes, 1878 bool fast_validate) 1879 { 1880 int i, pipe_cnt; 1881 struct resource_context *res_ctx = &context->res_ctx; 1882 struct pipe_ctx *pipe; 1883 bool subvp_in_use = false; 1884 uint8_t is_pipe_split_expected[MAX_PIPES] = {0}; 1885 struct dc_crtc_timing *timing; 1886 1887 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1888 1889 /* Determine whether we will apply ODM 2to1 policy: 1890 * Applies to single display and where the number of planes is less than 3. 1891 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1892 * 1893 * Apply pipe split policy first so we can predict the pipe split correctly 1894 * (dcn32_predict_pipe_split). 1895 */ 1896 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1897 if (!res_ctx->pipe_ctx[i].stream) 1898 continue; 1899 pipe = &res_ctx->pipe_ctx[i]; 1900 timing = &pipe->stream->timing; 1901 1902 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1903 if (context->stream_count == 1 && 1904 context->stream_status[0].plane_count <= 1 && 1905 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1906 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1907 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1908 dc->debug.enable_single_display_2to1_odm_policy) { 1909 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1910 } 1911 pipe_cnt++; 1912 } 1913 1914 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1915 1916 if (!res_ctx->pipe_ctx[i].stream) 1917 continue; 1918 pipe = &res_ctx->pipe_ctx[i]; 1919 timing = &pipe->stream->timing; 1920 1921 pipes[pipe_cnt].pipe.src.gpuvm = true; 1922 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1923 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1924 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1925 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1926 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1927 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1928 1929 switch (pipe->stream->mall_stream_config.type) { 1930 case SUBVP_MAIN: 1931 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1932 subvp_in_use = true; 1933 break; 1934 case SUBVP_PHANTOM: 1935 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1936 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1937 // Disallow unbounded req for SubVP according to DCHUB programming guide 1938 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1939 break; 1940 case SUBVP_NONE: 1941 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1942 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1943 break; 1944 default: 1945 break; 1946 } 1947 1948 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1949 if (pipes[pipe_cnt].dout.dsc_enable) { 1950 switch (timing->display_color_depth) { 1951 case COLOR_DEPTH_888: 1952 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1953 break; 1954 case COLOR_DEPTH_101010: 1955 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1956 break; 1957 case COLOR_DEPTH_121212: 1958 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1959 break; 1960 default: 1961 ASSERT(0); 1962 break; 1963 } 1964 } 1965 1966 DC_FP_START(); 1967 is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 1968 DC_FP_END(); 1969 1970 pipe_cnt++; 1971 } 1972 1973 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 1974 * the DET available for each pipe). Use the DET override input to maintain our driver 1975 * policy. 1976 */ 1977 dcn32_set_det_allocations(dc, context, pipes); 1978 1979 // In general cases we want to keep the dram clock change requirement 1980 // (prefer configs that support MCLK switch). Only override to false 1981 // for SubVP 1982 if (subvp_in_use) 1983 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 1984 else 1985 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1986 1987 return pipe_cnt; 1988 } 1989 1990 static struct dc_cap_funcs cap_funcs = { 1991 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1992 }; 1993 1994 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 1995 display_e2e_pipe_params_st *pipes, 1996 int pipe_cnt, 1997 int vlevel) 1998 { 1999 DC_FP_START(); 2000 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2001 DC_FP_END(); 2002 } 2003 2004 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2005 { 2006 DC_FP_START(); 2007 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2008 DC_FP_END(); 2009 } 2010 2011 static struct resource_funcs dcn32_res_pool_funcs = { 2012 .destroy = dcn32_destroy_resource_pool, 2013 .link_enc_create = dcn32_link_encoder_create, 2014 .link_enc_create_minimal = NULL, 2015 .panel_cntl_create = dcn32_panel_cntl_create, 2016 .validate_bandwidth = dcn32_validate_bandwidth, 2017 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2018 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2019 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2020 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2021 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2022 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2023 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2024 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2025 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2026 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2027 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2028 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2029 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2030 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2031 .add_phantom_pipes = dcn32_add_phantom_pipes, 2032 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2033 }; 2034 2035 2036 static bool dcn32_resource_construct( 2037 uint8_t num_virtual_links, 2038 struct dc *dc, 2039 struct dcn32_resource_pool *pool) 2040 { 2041 int i, j; 2042 struct dc_context *ctx = dc->ctx; 2043 struct irq_service_init_data init_data; 2044 struct ddc_service_init_data ddc_init_data = {0}; 2045 uint32_t pipe_fuses = 0; 2046 uint32_t num_pipes = 4; 2047 2048 #undef REG_STRUCT 2049 #define REG_STRUCT bios_regs 2050 bios_regs_init(); 2051 2052 #undef REG_STRUCT 2053 #define REG_STRUCT clk_src_regs 2054 clk_src_regs_init(0, A), 2055 clk_src_regs_init(1, B), 2056 clk_src_regs_init(2, C), 2057 clk_src_regs_init(3, D), 2058 clk_src_regs_init(4, E); 2059 #undef REG_STRUCT 2060 #define REG_STRUCT abm_regs 2061 abm_regs_init(0), 2062 abm_regs_init(1), 2063 abm_regs_init(2), 2064 abm_regs_init(3); 2065 2066 #undef REG_STRUCT 2067 #define REG_STRUCT dccg_regs 2068 dccg_regs_init(); 2069 2070 DC_FP_START(); 2071 2072 ctx->dc_bios->regs = &bios_regs; 2073 2074 pool->base.res_cap = &res_cap_dcn32; 2075 /* max number of pipes for ASIC before checking for pipe fuses */ 2076 num_pipes = pool->base.res_cap->num_timing_generator; 2077 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2078 2079 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2080 if (pipe_fuses & 1 << i) 2081 num_pipes--; 2082 2083 if (pipe_fuses & 1) 2084 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2085 2086 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2087 ASSERT(0); //Entire DCN is harvested! 2088 2089 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2090 * value will be changed, update max_num_dpp and max_num_otg for dml. 2091 */ 2092 dcn3_2_ip.max_num_dpp = num_pipes; 2093 dcn3_2_ip.max_num_otg = num_pipes; 2094 2095 pool->base.funcs = &dcn32_res_pool_funcs; 2096 2097 /************************************************* 2098 * Resource + asic cap harcoding * 2099 *************************************************/ 2100 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2101 pool->base.timing_generator_count = num_pipes; 2102 pool->base.pipe_count = num_pipes; 2103 pool->base.mpcc_count = num_pipes; 2104 dc->caps.max_downscale_ratio = 600; 2105 dc->caps.i2c_speed_in_khz = 100; 2106 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2107 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2108 dc->caps.max_cursor_size = 64; 2109 dc->caps.min_horizontal_blanking_period = 80; 2110 dc->caps.dmdata_alloc_size = 2048; 2111 dc->caps.mall_size_per_mem_channel = 0; 2112 dc->caps.mall_size_total = 0; 2113 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2114 2115 dc->caps.cache_line_size = 64; 2116 dc->caps.cache_num_ways = 16; 2117 dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64 2118 dc->caps.subvp_fw_processing_delay_us = 15; 2119 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2120 dc->caps.subvp_swath_height_margin_lines = 16; 2121 dc->caps.subvp_pstate_allow_width_us = 20; 2122 dc->caps.subvp_vertical_int_margin_us = 30; 2123 2124 dc->caps.max_slave_planes = 2; 2125 dc->caps.max_slave_yuv_planes = 2; 2126 dc->caps.max_slave_rgb_planes = 2; 2127 dc->caps.post_blend_color_processing = true; 2128 dc->caps.force_dp_tps4_for_cp2520 = true; 2129 dc->caps.dp_hpo = true; 2130 dc->caps.dp_hdmi21_pcon_support = true; 2131 dc->caps.edp_dsc_support = true; 2132 dc->caps.extended_aux_timeout_support = true; 2133 dc->caps.dmcub_support = true; 2134 2135 /* Color pipeline capabilities */ 2136 dc->caps.color.dpp.dcn_arch = 1; 2137 dc->caps.color.dpp.input_lut_shared = 0; 2138 dc->caps.color.dpp.icsc = 1; 2139 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2140 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2141 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2142 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2143 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2144 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2145 dc->caps.color.dpp.post_csc = 1; 2146 dc->caps.color.dpp.gamma_corr = 1; 2147 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2148 2149 dc->caps.color.dpp.hw_3d_lut = 1; 2150 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2151 // no OGAM ROM on DCN2 and later ASICs 2152 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2153 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2154 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2155 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2156 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2157 dc->caps.color.dpp.ocsc = 0; 2158 2159 dc->caps.color.mpc.gamut_remap = 1; 2160 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2161 dc->caps.color.mpc.ogam_ram = 1; 2162 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2163 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2164 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2165 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2166 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2167 dc->caps.color.mpc.ocsc = 1; 2168 2169 /* Use pipe context based otg sync logic */ 2170 dc->config.use_pipe_ctx_sync_logic = true; 2171 2172 /* read VBIOS LTTPR caps */ 2173 { 2174 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2175 enum bp_result bp_query_result; 2176 uint8_t is_vbios_lttpr_enable = 0; 2177 2178 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2179 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2180 } 2181 2182 /* interop bit is implicit */ 2183 { 2184 dc->caps.vbios_lttpr_aware = true; 2185 } 2186 } 2187 2188 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2189 dc->debug = debug_defaults_drv; 2190 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2191 dc->debug = debug_defaults_diags; 2192 } else 2193 dc->debug = debug_defaults_diags; 2194 // Init the vm_helper 2195 if (dc->vm_helper) 2196 vm_helper_init(dc->vm_helper, 16); 2197 2198 /************************************************* 2199 * Create resources * 2200 *************************************************/ 2201 2202 /* Clock Sources for Pixel Clock*/ 2203 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2204 dcn32_clock_source_create(ctx, ctx->dc_bios, 2205 CLOCK_SOURCE_COMBO_PHY_PLL0, 2206 &clk_src_regs[0], false); 2207 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2208 dcn32_clock_source_create(ctx, ctx->dc_bios, 2209 CLOCK_SOURCE_COMBO_PHY_PLL1, 2210 &clk_src_regs[1], false); 2211 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2212 dcn32_clock_source_create(ctx, ctx->dc_bios, 2213 CLOCK_SOURCE_COMBO_PHY_PLL2, 2214 &clk_src_regs[2], false); 2215 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2216 dcn32_clock_source_create(ctx, ctx->dc_bios, 2217 CLOCK_SOURCE_COMBO_PHY_PLL3, 2218 &clk_src_regs[3], false); 2219 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2220 dcn32_clock_source_create(ctx, ctx->dc_bios, 2221 CLOCK_SOURCE_COMBO_PHY_PLL4, 2222 &clk_src_regs[4], false); 2223 2224 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2225 2226 /* todo: not reuse phy_pll registers */ 2227 pool->base.dp_clock_source = 2228 dcn32_clock_source_create(ctx, ctx->dc_bios, 2229 CLOCK_SOURCE_ID_DP_DTO, 2230 &clk_src_regs[0], true); 2231 2232 for (i = 0; i < pool->base.clk_src_count; i++) { 2233 if (pool->base.clock_sources[i] == NULL) { 2234 dm_error("DC: failed to create clock sources!\n"); 2235 BREAK_TO_DEBUGGER(); 2236 goto create_fail; 2237 } 2238 } 2239 2240 /* DCCG */ 2241 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2242 if (pool->base.dccg == NULL) { 2243 dm_error("DC: failed to create dccg!\n"); 2244 BREAK_TO_DEBUGGER(); 2245 goto create_fail; 2246 } 2247 2248 /* DML */ 2249 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2250 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2251 2252 /* IRQ Service */ 2253 init_data.ctx = dc->ctx; 2254 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2255 if (!pool->base.irqs) 2256 goto create_fail; 2257 2258 /* HUBBUB */ 2259 pool->base.hubbub = dcn32_hubbub_create(ctx); 2260 if (pool->base.hubbub == NULL) { 2261 BREAK_TO_DEBUGGER(); 2262 dm_error("DC: failed to create hubbub!\n"); 2263 goto create_fail; 2264 } 2265 2266 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2267 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2268 2269 /* if pipe is disabled, skip instance of HW pipe, 2270 * i.e, skip ASIC register instance 2271 */ 2272 if (pipe_fuses & 1 << i) 2273 continue; 2274 2275 /* HUBPs */ 2276 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2277 if (pool->base.hubps[j] == NULL) { 2278 BREAK_TO_DEBUGGER(); 2279 dm_error( 2280 "DC: failed to create hubps!\n"); 2281 goto create_fail; 2282 } 2283 2284 /* DPPs */ 2285 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2286 if (pool->base.dpps[j] == NULL) { 2287 BREAK_TO_DEBUGGER(); 2288 dm_error( 2289 "DC: failed to create dpps!\n"); 2290 goto create_fail; 2291 } 2292 2293 /* OPPs */ 2294 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2295 if (pool->base.opps[j] == NULL) { 2296 BREAK_TO_DEBUGGER(); 2297 dm_error( 2298 "DC: failed to create output pixel processor!\n"); 2299 goto create_fail; 2300 } 2301 2302 /* TGs */ 2303 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2304 ctx, i); 2305 if (pool->base.timing_generators[j] == NULL) { 2306 BREAK_TO_DEBUGGER(); 2307 dm_error("DC: failed to create tg!\n"); 2308 goto create_fail; 2309 } 2310 2311 /* ABMs */ 2312 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2313 &abm_regs[i], 2314 &abm_shift, 2315 &abm_mask); 2316 if (pool->base.multiple_abms[j] == NULL) { 2317 dm_error("DC: failed to create abm for pipe %d!\n", i); 2318 BREAK_TO_DEBUGGER(); 2319 goto create_fail; 2320 } 2321 2322 /* index for resource pool arrays for next valid pipe */ 2323 j++; 2324 } 2325 2326 /* PSR */ 2327 pool->base.psr = dmub_psr_create(ctx); 2328 if (pool->base.psr == NULL) { 2329 dm_error("DC: failed to create psr obj!\n"); 2330 BREAK_TO_DEBUGGER(); 2331 goto create_fail; 2332 } 2333 2334 /* MPCCs */ 2335 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2336 if (pool->base.mpc == NULL) { 2337 BREAK_TO_DEBUGGER(); 2338 dm_error("DC: failed to create mpc!\n"); 2339 goto create_fail; 2340 } 2341 2342 /* DSCs */ 2343 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2344 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2345 if (pool->base.dscs[i] == NULL) { 2346 BREAK_TO_DEBUGGER(); 2347 dm_error("DC: failed to create display stream compressor %d!\n", i); 2348 goto create_fail; 2349 } 2350 } 2351 2352 /* DWB */ 2353 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2354 BREAK_TO_DEBUGGER(); 2355 dm_error("DC: failed to create dwbc!\n"); 2356 goto create_fail; 2357 } 2358 2359 /* MMHUBBUB */ 2360 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2361 BREAK_TO_DEBUGGER(); 2362 dm_error("DC: failed to create mcif_wb!\n"); 2363 goto create_fail; 2364 } 2365 2366 /* AUX and I2C */ 2367 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2368 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2369 if (pool->base.engines[i] == NULL) { 2370 BREAK_TO_DEBUGGER(); 2371 dm_error( 2372 "DC:failed to create aux engine!!\n"); 2373 goto create_fail; 2374 } 2375 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2376 if (pool->base.hw_i2cs[i] == NULL) { 2377 BREAK_TO_DEBUGGER(); 2378 dm_error( 2379 "DC:failed to create hw i2c!!\n"); 2380 goto create_fail; 2381 } 2382 pool->base.sw_i2cs[i] = NULL; 2383 } 2384 2385 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2386 if (!resource_construct(num_virtual_links, dc, &pool->base, 2387 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2388 &res_create_funcs : &res_create_maximus_funcs))) 2389 goto create_fail; 2390 2391 /* HW Sequencer init functions and Plane caps */ 2392 dcn32_hw_sequencer_init_functions(dc); 2393 2394 dc->caps.max_planes = pool->base.pipe_count; 2395 2396 for (i = 0; i < dc->caps.max_planes; ++i) 2397 dc->caps.planes[i] = plane_cap; 2398 2399 dc->cap_funcs = cap_funcs; 2400 2401 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2402 ddc_init_data.ctx = dc->ctx; 2403 ddc_init_data.link = NULL; 2404 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2405 ddc_init_data.id.enum_id = 0; 2406 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2407 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2408 } else { 2409 pool->base.oem_device = NULL; 2410 } 2411 2412 DC_FP_END(); 2413 2414 return true; 2415 2416 create_fail: 2417 2418 DC_FP_END(); 2419 2420 dcn32_resource_destruct(pool); 2421 2422 return false; 2423 } 2424 2425 struct resource_pool *dcn32_create_resource_pool( 2426 const struct dc_init_data *init_data, 2427 struct dc *dc) 2428 { 2429 struct dcn32_resource_pool *pool = 2430 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2431 2432 if (!pool) 2433 return NULL; 2434 2435 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2436 return &pool->base; 2437 2438 BREAK_TO_DEBUGGER(); 2439 kfree(pool); 2440 return NULL; 2441 } 2442 2443 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2444 struct resource_context *res_ctx, 2445 const struct resource_pool *pool, 2446 const struct pipe_ctx *primary_pipe) 2447 { 2448 int i; 2449 struct pipe_ctx *secondary_pipe = NULL; 2450 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2451 int primary_index, preferred_pipe_idx; 2452 struct pipe_ctx *old_primary_pipe = NULL; 2453 2454 /* 2455 * Modified from find_idle_secondary_pipe 2456 * With windowed MPO and ODM, we want to avoid the case where we want a 2457 * free pipe for the left side but the free pipe is being used on the 2458 * right side. 2459 * Add check on current_state if the primary_pipe is the left side, 2460 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2461 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2462 * - If so, then don't use this pipe 2463 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2464 * - in this case, the primary pipe has already gotten a free pipe for the 2465 * MPO window in the left 2466 * - when it tries to get a free pipe for the MPO window on the right, 2467 * it will see that it is already assigned to the right side 2468 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2469 * free pipe, since it will be for the right side. So add an 2470 * additional condition, that skipping the free pipe on the right only 2471 * applies if the primary pipe has no bottom pipe currently assigned 2472 */ 2473 if (primary_pipe) { 2474 primary_index = primary_pipe->pipe_idx; 2475 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2476 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2477 && (!primary_pipe->bottom_pipe)) 2478 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2479 2480 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2481 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2482 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2483 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2484 secondary_pipe->pipe_idx = preferred_pipe_idx; 2485 } 2486 } 2487 2488 /* 2489 * search backwards for the second pipe to keep pipe 2490 * assignment more consistent 2491 */ 2492 if (!secondary_pipe) 2493 for (i = pool->pipe_count - 1; i >= 0; i--) { 2494 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2495 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2496 secondary_pipe = &res_ctx->pipe_ctx[i]; 2497 secondary_pipe->pipe_idx = i; 2498 break; 2499 } 2500 } 2501 2502 return secondary_pipe; 2503 } 2504 2505 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2506 struct dc_state *state, 2507 const struct resource_pool *pool, 2508 struct dc_stream_state *stream, 2509 struct pipe_ctx *head_pipe) 2510 { 2511 struct resource_context *res_ctx = &state->res_ctx; 2512 struct pipe_ctx *idle_pipe, *pipe; 2513 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2514 int head_index; 2515 2516 if (!head_pipe) 2517 ASSERT(0); 2518 2519 /* 2520 * Modified from dcn20_acquire_idle_pipe_for_layer 2521 * Check if head_pipe in old_context already has bottom_pipe allocated. 2522 * - If so, check if that pipe is available in the current context. 2523 * -- If so, reuse pipe from old_context 2524 */ 2525 head_index = head_pipe->pipe_idx; 2526 pipe = &old_ctx->pipe_ctx[head_index]; 2527 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2528 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2529 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2530 } else { 2531 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2532 if (!idle_pipe) 2533 return NULL; 2534 } 2535 2536 idle_pipe->stream = head_pipe->stream; 2537 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2538 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2539 2540 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2541 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2542 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2543 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2544 2545 return idle_pipe; 2546 } 2547