1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dcn31/dcn31_apg.h" 61 #include "dcn31/dcn31_dio_link_encoder.h" 62 #include "dcn32/dcn32_dio_link_encoder.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn32/dcn32_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "link.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn32/dcn32_mmhubbub.h" 76 77 #include "dcn/dcn_3_2_0_offset.h" 78 #include "dcn/dcn_3_2_0_sh_mask.h" 79 #include "nbio/nbio_4_3_0_offset.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/display_mode_vba_30.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dml/dcn32/dcn32_fpu.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 enum dcn32_clk_src_array_id { 95 DCN32_CLK_SRC_PLL0, 96 DCN32_CLK_SRC_PLL1, 97 DCN32_CLK_SRC_PLL2, 98 DCN32_CLK_SRC_PLL3, 99 DCN32_CLK_SRC_PLL4, 100 DCN32_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 109 110 #define BASE(seg) BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 114 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 117 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name = value 120 121 #define SRI(reg_name, block, id)\ 122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 reg ## block ## id ## _ ## reg_name 124 125 #define SRI_ARR(reg_name, block, id)\ 126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SR_ARR_I2C(reg_name, id) \ 130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 131 132 #define SRI_ARR_I2C(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI2(reg_name, block, id)\ 141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 142 reg ## reg_name 143 #define SRI2_ARR(reg_name, block, id)\ 144 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRIR(var_name, reg_name, block, id)\ 148 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRII(reg_name, block, id)\ 152 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII_ARR_2(reg_name, block, id, inst)\ 156 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_MPC_RMU(reg_name, block, id)\ 160 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_DWB(reg_name, temp_name, block, id)\ 164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## temp_name 166 167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 //DPCS_DCN31_MASK_SH_LIST(_MASK) 328 }; 329 330 #define hpo_dp_stream_encoder_reg_init(id)\ 331 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 332 333 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 334 335 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 336 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 337 }; 338 339 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 341 }; 342 343 344 #define hpo_dp_link_encoder_reg_init(id)\ 345 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 346 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 347 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 350 351 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 352 353 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 354 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 355 }; 356 357 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 359 }; 360 361 #define dpp_regs_init(id)\ 362 DPP_REG_LIST_DCN30_COMMON_RI(id) 363 364 static struct dcn3_dpp_registers dpp_regs[4]; 365 366 static const struct dcn3_dpp_shift tf_shift = { 367 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 368 }; 369 370 static const struct dcn3_dpp_mask tf_mask = { 371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 372 }; 373 374 375 #define opp_regs_init(id)\ 376 OPP_REG_LIST_DCN30_RI(id) 377 378 static struct dcn20_opp_registers opp_regs[4]; 379 380 static const struct dcn20_opp_shift opp_shift = { 381 OPP_MASK_SH_LIST_DCN20(__SHIFT) 382 }; 383 384 static const struct dcn20_opp_mask opp_mask = { 385 OPP_MASK_SH_LIST_DCN20(_MASK) 386 }; 387 388 #define aux_engine_regs_init(id)\ 389 ( \ 390 AUX_COMMON_REG_LIST0_RI(id), \ 391 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 392 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 395 ) 396 397 static struct dce110_aux_registers aux_engine_regs[5]; 398 399 static const struct dce110_aux_registers_shift aux_shift = { 400 DCN_AUX_MASK_SH_LIST(__SHIFT) 401 }; 402 403 static const struct dce110_aux_registers_mask aux_mask = { 404 DCN_AUX_MASK_SH_LIST(_MASK) 405 }; 406 407 #define dwbc_regs_dcn3_init(id)\ 408 DWBC_COMMON_REG_LIST_DCN30_RI(id) 409 410 static struct dcn30_dwbc_registers dwbc30_regs[1]; 411 412 static const struct dcn30_dwbc_shift dwbc30_shift = { 413 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 414 }; 415 416 static const struct dcn30_dwbc_mask dwbc30_mask = { 417 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 418 }; 419 420 #define mcif_wb_regs_dcn3_init(id)\ 421 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 422 423 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 424 425 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 426 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 427 }; 428 429 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 430 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 431 }; 432 433 #define dsc_regsDCN20_init(id)\ 434 DSC_REG_LIST_DCN20_RI(id) 435 436 static struct dcn20_dsc_registers dsc_regs[4]; 437 438 static const struct dcn20_dsc_shift dsc_shift = { 439 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 440 }; 441 442 static const struct dcn20_dsc_mask dsc_mask = { 443 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 444 }; 445 446 static struct dcn30_mpc_registers mpc_regs; 447 448 #define dcn_mpc_regs_init() \ 449 MPC_REG_LIST_DCN3_2_RI(0),\ 450 MPC_REG_LIST_DCN3_2_RI(1),\ 451 MPC_REG_LIST_DCN3_2_RI(2),\ 452 MPC_REG_LIST_DCN3_2_RI(3),\ 453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 458 459 static const struct dcn30_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 461 }; 462 463 static const struct dcn30_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 465 }; 466 467 #define optc_regs_init(id)\ 468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 469 470 static struct dcn_optc_registers optc_regs[4]; 471 472 static const struct dcn_optc_shift optc_shift = { 473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 474 }; 475 476 static const struct dcn_optc_mask optc_mask = { 477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 478 }; 479 480 #define hubp_regs_init(id)\ 481 HUBP_REG_LIST_DCN32_RI(id) 482 483 static struct dcn_hubp2_registers hubp_regs[4]; 484 485 486 static const struct dcn_hubp2_shift hubp_shift = { 487 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 488 }; 489 490 static const struct dcn_hubp2_mask hubp_mask = { 491 HUBP_MASK_SH_LIST_DCN32(_MASK) 492 }; 493 494 static struct dcn_hubbub_registers hubbub_reg; 495 #define hubbub_reg_init()\ 496 HUBBUB_REG_LIST_DCN32_RI(0) 497 498 static const struct dcn_hubbub_shift hubbub_shift = { 499 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 500 }; 501 502 static const struct dcn_hubbub_mask hubbub_mask = { 503 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 504 }; 505 506 static struct dccg_registers dccg_regs; 507 508 #define dccg_regs_init()\ 509 DCCG_REG_LIST_DCN32_RI() 510 511 static const struct dccg_shift dccg_shift = { 512 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 513 }; 514 515 static const struct dccg_mask dccg_mask = { 516 DCCG_MASK_SH_LIST_DCN32(_MASK) 517 }; 518 519 520 #define SRII2(reg_name_pre, reg_name_post, id)\ 521 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 522 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 523 reg ## reg_name_pre ## id ## _ ## reg_name_post 524 525 526 #define HWSEQ_DCN32_REG_LIST()\ 527 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 528 SR(DIO_MEM_PWR_CTRL), \ 529 SR(ODM_MEM_PWR_CTRL3), \ 530 SR(MMHUBBUB_MEM_PWR_CNTL), \ 531 SR(DCCG_GATE_DISABLE_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL2), \ 533 SR(DCFCLK_CNTL),\ 534 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 535 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 537 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 543 SR(MICROSECOND_TIME_BASE_DIV), \ 544 SR(MILLISECOND_TIME_BASE_DIV), \ 545 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 546 SR(RBBMIF_TIMEOUT_DIS), \ 547 SR(RBBMIF_TIMEOUT_DIS_2), \ 548 SR(DCHUBBUB_CRC_CTRL), \ 549 SR(DPP_TOP0_DPP_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 552 SR(MPC_CRC_CTRL), \ 553 SR(MPC_CRC_RESULT_GB), \ 554 SR(MPC_CRC_RESULT_C), \ 555 SR(MPC_CRC_RESULT_AR), \ 556 SR(DOMAIN0_PG_CONFIG), \ 557 SR(DOMAIN1_PG_CONFIG), \ 558 SR(DOMAIN2_PG_CONFIG), \ 559 SR(DOMAIN3_PG_CONFIG), \ 560 SR(DOMAIN16_PG_CONFIG), \ 561 SR(DOMAIN17_PG_CONFIG), \ 562 SR(DOMAIN18_PG_CONFIG), \ 563 SR(DOMAIN19_PG_CONFIG), \ 564 SR(DOMAIN0_PG_STATUS), \ 565 SR(DOMAIN1_PG_STATUS), \ 566 SR(DOMAIN2_PG_STATUS), \ 567 SR(DOMAIN3_PG_STATUS), \ 568 SR(DOMAIN16_PG_STATUS), \ 569 SR(DOMAIN17_PG_STATUS), \ 570 SR(DOMAIN18_PG_STATUS), \ 571 SR(DOMAIN19_PG_STATUS), \ 572 SR(D1VGA_CONTROL), \ 573 SR(D2VGA_CONTROL), \ 574 SR(D3VGA_CONTROL), \ 575 SR(D4VGA_CONTROL), \ 576 SR(D5VGA_CONTROL), \ 577 SR(D6VGA_CONTROL), \ 578 SR(DC_IP_REQUEST_CNTL), \ 579 SR(AZALIA_AUDIO_DTO), \ 580 SR(AZALIA_CONTROLLER_CLOCK_GATING) 581 582 static struct dce_hwseq_registers hwseq_reg; 583 584 #define hwseq_reg_init()\ 585 HWSEQ_DCN32_REG_LIST() 586 587 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 588 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 589 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 607 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 615 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 616 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 619 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 620 621 static const struct dce_hwseq_shift hwseq_shift = { 622 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 623 }; 624 625 static const struct dce_hwseq_mask hwseq_mask = { 626 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 627 }; 628 #define vmid_regs_init(id)\ 629 DCN20_VMID_REG_LIST_RI(id) 630 631 static struct dcn_vmid_registers vmid_regs[16]; 632 633 static const struct dcn20_vmid_shift vmid_shifts = { 634 DCN20_VMID_MASK_SH_LIST(__SHIFT) 635 }; 636 637 static const struct dcn20_vmid_mask vmid_masks = { 638 DCN20_VMID_MASK_SH_LIST(_MASK) 639 }; 640 641 static const struct resource_caps res_cap_dcn32 = { 642 .num_timing_generator = 4, 643 .num_opp = 4, 644 .num_video_plane = 4, 645 .num_audio = 5, 646 .num_stream_encoder = 5, 647 .num_hpo_dp_stream_encoder = 4, 648 .num_hpo_dp_link_encoder = 2, 649 .num_pll = 5, 650 .num_dwb = 1, 651 .num_ddc = 5, 652 .num_vmid = 16, 653 .num_mpc_3dlut = 4, 654 .num_dsc = 4, 655 }; 656 657 static const struct dc_plane_cap plane_cap = { 658 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 659 .per_pixel_alpha = true, 660 661 .pixel_format_support = { 662 .argb8888 = true, 663 .nv12 = true, 664 .fp16 = true, 665 .p010 = true, 666 .ayuv = false, 667 }, 668 669 .max_upscale_factor = { 670 .argb8888 = 16000, 671 .nv12 = 16000, 672 .fp16 = 16000 673 }, 674 675 // 6:1 downscaling ratio: 1000/6 = 166.666 676 .max_downscale_factor = { 677 .argb8888 = 167, 678 .nv12 = 167, 679 .fp16 = 167 680 }, 681 64, 682 64 683 }; 684 685 static const struct dc_debug_options debug_defaults_drv = { 686 .disable_dmcu = true, 687 .force_abm_enable = false, 688 .timing_trace = false, 689 .clock_trace = true, 690 .disable_pplib_clock_request = false, 691 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 692 .force_single_disp_pipe_split = false, 693 .disable_dcc = DCC_ENABLE, 694 .vsr_support = true, 695 .performance_trace = false, 696 .max_downscale_src_width = 7680,/*upto 8K*/ 697 .disable_pplib_wm_range = false, 698 .scl_reset_length10 = true, 699 .sanity_checks = false, 700 .underflow_assert_delay_us = 0xFFFFFFFF, 701 .dwb_fi_phase = -1, // -1 = disable, 702 .dmub_command_table = true, 703 .enable_mem_low_power = { 704 .bits = { 705 .vga = false, 706 .i2c = false, 707 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 708 .dscl = false, 709 .cm = false, 710 .mpc = false, 711 .optc = true, 712 } 713 }, 714 .use_max_lb = true, 715 .force_disable_subvp = false, 716 .exit_idle_opt_for_cursor_updates = true, 717 .enable_single_display_2to1_odm_policy = true, 718 719 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 720 .enable_double_buffered_dsc_pg_support = true, 721 .enable_dp_dig_pixel_rate_div_policy = 1, 722 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 723 .alloc_extra_way_for_cursor = true, 724 .min_prefetch_in_strobe_ns = 60000, // 60us 725 .disable_unbounded_requesting = false, 726 .override_dispclk_programming = true, 727 .disable_fpo_optimizations = false, 728 .fpo_vactive_margin_us = 2000, // 2000us 729 .disable_fpo_vactive = true, 730 .disable_boot_optimizations = false, 731 }; 732 733 static const struct dc_debug_options debug_defaults_diags = { 734 .disable_dmcu = true, 735 .force_abm_enable = false, 736 .timing_trace = true, 737 .clock_trace = true, 738 .disable_dpp_power_gate = true, 739 .disable_hubp_power_gate = true, 740 .disable_dsc_power_gate = true, 741 .disable_clock_gate = true, 742 .disable_pplib_clock_request = true, 743 .disable_pplib_wm_range = true, 744 .disable_stutter = false, 745 .scl_reset_length10 = true, 746 .dwb_fi_phase = -1, // -1 = disable 747 .dmub_command_table = true, 748 .enable_tri_buf = true, 749 .use_max_lb = true, 750 .force_disable_subvp = true 751 }; 752 753 static struct dce_aux *dcn32_aux_engine_create( 754 struct dc_context *ctx, 755 uint32_t inst) 756 { 757 struct aux_engine_dce110 *aux_engine = 758 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 759 760 if (!aux_engine) 761 return NULL; 762 763 #undef REG_STRUCT 764 #define REG_STRUCT aux_engine_regs 765 aux_engine_regs_init(0), 766 aux_engine_regs_init(1), 767 aux_engine_regs_init(2), 768 aux_engine_regs_init(3), 769 aux_engine_regs_init(4); 770 771 dce110_aux_engine_construct(aux_engine, ctx, inst, 772 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 773 &aux_engine_regs[inst], 774 &aux_mask, 775 &aux_shift, 776 ctx->dc->caps.extended_aux_timeout_support); 777 778 return &aux_engine->base; 779 } 780 #define i2c_inst_regs_init(id)\ 781 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 782 783 static struct dce_i2c_registers i2c_hw_regs[5]; 784 785 static const struct dce_i2c_shift i2c_shifts = { 786 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 787 }; 788 789 static const struct dce_i2c_mask i2c_masks = { 790 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 791 }; 792 793 static struct dce_i2c_hw *dcn32_i2c_hw_create( 794 struct dc_context *ctx, 795 uint32_t inst) 796 { 797 struct dce_i2c_hw *dce_i2c_hw = 798 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 799 800 if (!dce_i2c_hw) 801 return NULL; 802 803 #undef REG_STRUCT 804 #define REG_STRUCT i2c_hw_regs 805 i2c_inst_regs_init(1), 806 i2c_inst_regs_init(2), 807 i2c_inst_regs_init(3), 808 i2c_inst_regs_init(4), 809 i2c_inst_regs_init(5); 810 811 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 812 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 813 814 return dce_i2c_hw; 815 } 816 817 static struct clock_source *dcn32_clock_source_create( 818 struct dc_context *ctx, 819 struct dc_bios *bios, 820 enum clock_source_id id, 821 const struct dce110_clk_src_regs *regs, 822 bool dp_clk_src) 823 { 824 struct dce110_clk_src *clk_src = 825 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 826 827 if (!clk_src) 828 return NULL; 829 830 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 831 regs, &cs_shift, &cs_mask)) { 832 clk_src->base.dp_clk_src = dp_clk_src; 833 return &clk_src->base; 834 } 835 836 kfree(clk_src); 837 BREAK_TO_DEBUGGER(); 838 return NULL; 839 } 840 841 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 842 { 843 int i; 844 845 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 846 GFP_KERNEL); 847 848 if (!hubbub2) 849 return NULL; 850 851 #undef REG_STRUCT 852 #define REG_STRUCT hubbub_reg 853 hubbub_reg_init(); 854 855 #undef REG_STRUCT 856 #define REG_STRUCT vmid_regs 857 vmid_regs_init(0), 858 vmid_regs_init(1), 859 vmid_regs_init(2), 860 vmid_regs_init(3), 861 vmid_regs_init(4), 862 vmid_regs_init(5), 863 vmid_regs_init(6), 864 vmid_regs_init(7), 865 vmid_regs_init(8), 866 vmid_regs_init(9), 867 vmid_regs_init(10), 868 vmid_regs_init(11), 869 vmid_regs_init(12), 870 vmid_regs_init(13), 871 vmid_regs_init(14), 872 vmid_regs_init(15); 873 874 hubbub32_construct(hubbub2, ctx, 875 &hubbub_reg, 876 &hubbub_shift, 877 &hubbub_mask, 878 ctx->dc->dml.ip.det_buffer_size_kbytes, 879 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 880 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 881 882 883 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 884 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 885 886 vmid->ctx = ctx; 887 888 vmid->regs = &vmid_regs[i]; 889 vmid->shifts = &vmid_shifts; 890 vmid->masks = &vmid_masks; 891 } 892 893 return &hubbub2->base; 894 } 895 896 static struct hubp *dcn32_hubp_create( 897 struct dc_context *ctx, 898 uint32_t inst) 899 { 900 struct dcn20_hubp *hubp2 = 901 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 902 903 if (!hubp2) 904 return NULL; 905 906 #undef REG_STRUCT 907 #define REG_STRUCT hubp_regs 908 hubp_regs_init(0), 909 hubp_regs_init(1), 910 hubp_regs_init(2), 911 hubp_regs_init(3); 912 913 if (hubp32_construct(hubp2, ctx, inst, 914 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 915 return &hubp2->base; 916 917 BREAK_TO_DEBUGGER(); 918 kfree(hubp2); 919 return NULL; 920 } 921 922 static void dcn32_dpp_destroy(struct dpp **dpp) 923 { 924 kfree(TO_DCN30_DPP(*dpp)); 925 *dpp = NULL; 926 } 927 928 static struct dpp *dcn32_dpp_create( 929 struct dc_context *ctx, 930 uint32_t inst) 931 { 932 struct dcn3_dpp *dpp3 = 933 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 934 935 if (!dpp3) 936 return NULL; 937 938 #undef REG_STRUCT 939 #define REG_STRUCT dpp_regs 940 dpp_regs_init(0), 941 dpp_regs_init(1), 942 dpp_regs_init(2), 943 dpp_regs_init(3); 944 945 if (dpp32_construct(dpp3, ctx, inst, 946 &dpp_regs[inst], &tf_shift, &tf_mask)) 947 return &dpp3->base; 948 949 BREAK_TO_DEBUGGER(); 950 kfree(dpp3); 951 return NULL; 952 } 953 954 static struct mpc *dcn32_mpc_create( 955 struct dc_context *ctx, 956 int num_mpcc, 957 int num_rmu) 958 { 959 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 960 GFP_KERNEL); 961 962 if (!mpc30) 963 return NULL; 964 965 #undef REG_STRUCT 966 #define REG_STRUCT mpc_regs 967 dcn_mpc_regs_init(); 968 969 dcn32_mpc_construct(mpc30, ctx, 970 &mpc_regs, 971 &mpc_shift, 972 &mpc_mask, 973 num_mpcc, 974 num_rmu); 975 976 return &mpc30->base; 977 } 978 979 static struct output_pixel_processor *dcn32_opp_create( 980 struct dc_context *ctx, uint32_t inst) 981 { 982 struct dcn20_opp *opp2 = 983 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 984 985 if (!opp2) { 986 BREAK_TO_DEBUGGER(); 987 return NULL; 988 } 989 990 #undef REG_STRUCT 991 #define REG_STRUCT opp_regs 992 opp_regs_init(0), 993 opp_regs_init(1), 994 opp_regs_init(2), 995 opp_regs_init(3); 996 997 dcn20_opp_construct(opp2, ctx, inst, 998 &opp_regs[inst], &opp_shift, &opp_mask); 999 return &opp2->base; 1000 } 1001 1002 1003 static struct timing_generator *dcn32_timing_generator_create( 1004 struct dc_context *ctx, 1005 uint32_t instance) 1006 { 1007 struct optc *tgn10 = 1008 kzalloc(sizeof(struct optc), GFP_KERNEL); 1009 1010 if (!tgn10) 1011 return NULL; 1012 1013 #undef REG_STRUCT 1014 #define REG_STRUCT optc_regs 1015 optc_regs_init(0), 1016 optc_regs_init(1), 1017 optc_regs_init(2), 1018 optc_regs_init(3); 1019 1020 tgn10->base.inst = instance; 1021 tgn10->base.ctx = ctx; 1022 1023 tgn10->tg_regs = &optc_regs[instance]; 1024 tgn10->tg_shift = &optc_shift; 1025 tgn10->tg_mask = &optc_mask; 1026 1027 dcn32_timing_generator_init(tgn10); 1028 1029 return &tgn10->base; 1030 } 1031 1032 static const struct encoder_feature_support link_enc_feature = { 1033 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1034 .max_hdmi_pixel_clock = 600000, 1035 .hdmi_ycbcr420_supported = true, 1036 .dp_ycbcr420_supported = true, 1037 .fec_supported = true, 1038 .flags.bits.IS_HBR2_CAPABLE = true, 1039 .flags.bits.IS_HBR3_CAPABLE = true, 1040 .flags.bits.IS_TPS3_CAPABLE = true, 1041 .flags.bits.IS_TPS4_CAPABLE = true 1042 }; 1043 1044 static struct link_encoder *dcn32_link_encoder_create( 1045 struct dc_context *ctx, 1046 const struct encoder_init_data *enc_init_data) 1047 { 1048 struct dcn20_link_encoder *enc20 = 1049 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1050 1051 if (!enc20) 1052 return NULL; 1053 1054 #undef REG_STRUCT 1055 #define REG_STRUCT link_enc_aux_regs 1056 aux_regs_init(0), 1057 aux_regs_init(1), 1058 aux_regs_init(2), 1059 aux_regs_init(3), 1060 aux_regs_init(4); 1061 1062 #undef REG_STRUCT 1063 #define REG_STRUCT link_enc_hpd_regs 1064 hpd_regs_init(0), 1065 hpd_regs_init(1), 1066 hpd_regs_init(2), 1067 hpd_regs_init(3), 1068 hpd_regs_init(4); 1069 1070 #undef REG_STRUCT 1071 #define REG_STRUCT link_enc_regs 1072 link_regs_init(0, A), 1073 link_regs_init(1, B), 1074 link_regs_init(2, C), 1075 link_regs_init(3, D), 1076 link_regs_init(4, E); 1077 1078 dcn32_link_encoder_construct(enc20, 1079 enc_init_data, 1080 &link_enc_feature, 1081 &link_enc_regs[enc_init_data->transmitter], 1082 &link_enc_aux_regs[enc_init_data->channel - 1], 1083 &link_enc_hpd_regs[enc_init_data->hpd_source], 1084 &le_shift, 1085 &le_mask); 1086 1087 return &enc20->enc10.base; 1088 } 1089 1090 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1091 { 1092 struct dcn31_panel_cntl *panel_cntl = 1093 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1094 1095 if (!panel_cntl) 1096 return NULL; 1097 1098 dcn31_panel_cntl_construct(panel_cntl, init_data); 1099 1100 return &panel_cntl->base; 1101 } 1102 1103 static void read_dce_straps( 1104 struct dc_context *ctx, 1105 struct resource_straps *straps) 1106 { 1107 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1108 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1109 1110 } 1111 1112 static struct audio *dcn32_create_audio( 1113 struct dc_context *ctx, unsigned int inst) 1114 { 1115 1116 #undef REG_STRUCT 1117 #define REG_STRUCT audio_regs 1118 audio_regs_init(0), 1119 audio_regs_init(1), 1120 audio_regs_init(2), 1121 audio_regs_init(3), 1122 audio_regs_init(4); 1123 1124 return dce_audio_create(ctx, inst, 1125 &audio_regs[inst], &audio_shift, &audio_mask); 1126 } 1127 1128 static struct vpg *dcn32_vpg_create( 1129 struct dc_context *ctx, 1130 uint32_t inst) 1131 { 1132 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1133 1134 if (!vpg3) 1135 return NULL; 1136 1137 #undef REG_STRUCT 1138 #define REG_STRUCT vpg_regs 1139 vpg_regs_init(0), 1140 vpg_regs_init(1), 1141 vpg_regs_init(2), 1142 vpg_regs_init(3), 1143 vpg_regs_init(4), 1144 vpg_regs_init(5), 1145 vpg_regs_init(6), 1146 vpg_regs_init(7), 1147 vpg_regs_init(8), 1148 vpg_regs_init(9); 1149 1150 vpg3_construct(vpg3, ctx, inst, 1151 &vpg_regs[inst], 1152 &vpg_shift, 1153 &vpg_mask); 1154 1155 return &vpg3->base; 1156 } 1157 1158 static struct afmt *dcn32_afmt_create( 1159 struct dc_context *ctx, 1160 uint32_t inst) 1161 { 1162 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1163 1164 if (!afmt3) 1165 return NULL; 1166 1167 #undef REG_STRUCT 1168 #define REG_STRUCT afmt_regs 1169 afmt_regs_init(0), 1170 afmt_regs_init(1), 1171 afmt_regs_init(2), 1172 afmt_regs_init(3), 1173 afmt_regs_init(4), 1174 afmt_regs_init(5); 1175 1176 afmt3_construct(afmt3, ctx, inst, 1177 &afmt_regs[inst], 1178 &afmt_shift, 1179 &afmt_mask); 1180 1181 return &afmt3->base; 1182 } 1183 1184 static struct apg *dcn31_apg_create( 1185 struct dc_context *ctx, 1186 uint32_t inst) 1187 { 1188 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1189 1190 if (!apg31) 1191 return NULL; 1192 1193 #undef REG_STRUCT 1194 #define REG_STRUCT apg_regs 1195 apg_regs_init(0), 1196 apg_regs_init(1), 1197 apg_regs_init(2), 1198 apg_regs_init(3); 1199 1200 apg31_construct(apg31, ctx, inst, 1201 &apg_regs[inst], 1202 &apg_shift, 1203 &apg_mask); 1204 1205 return &apg31->base; 1206 } 1207 1208 static struct stream_encoder *dcn32_stream_encoder_create( 1209 enum engine_id eng_id, 1210 struct dc_context *ctx) 1211 { 1212 struct dcn10_stream_encoder *enc1; 1213 struct vpg *vpg; 1214 struct afmt *afmt; 1215 int vpg_inst; 1216 int afmt_inst; 1217 1218 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1219 if (eng_id <= ENGINE_ID_DIGF) { 1220 vpg_inst = eng_id; 1221 afmt_inst = eng_id; 1222 } else 1223 return NULL; 1224 1225 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1226 vpg = dcn32_vpg_create(ctx, vpg_inst); 1227 afmt = dcn32_afmt_create(ctx, afmt_inst); 1228 1229 if (!enc1 || !vpg || !afmt) { 1230 kfree(enc1); 1231 kfree(vpg); 1232 kfree(afmt); 1233 return NULL; 1234 } 1235 1236 #undef REG_STRUCT 1237 #define REG_STRUCT stream_enc_regs 1238 stream_enc_regs_init(0), 1239 stream_enc_regs_init(1), 1240 stream_enc_regs_init(2), 1241 stream_enc_regs_init(3), 1242 stream_enc_regs_init(4); 1243 1244 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1245 eng_id, vpg, afmt, 1246 &stream_enc_regs[eng_id], 1247 &se_shift, &se_mask); 1248 1249 return &enc1->base; 1250 } 1251 1252 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1253 enum engine_id eng_id, 1254 struct dc_context *ctx) 1255 { 1256 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1257 struct vpg *vpg; 1258 struct apg *apg; 1259 uint32_t hpo_dp_inst; 1260 uint32_t vpg_inst; 1261 uint32_t apg_inst; 1262 1263 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1264 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1265 1266 /* Mapping of VPG register blocks to HPO DP block instance: 1267 * VPG[6] -> HPO_DP[0] 1268 * VPG[7] -> HPO_DP[1] 1269 * VPG[8] -> HPO_DP[2] 1270 * VPG[9] -> HPO_DP[3] 1271 */ 1272 vpg_inst = hpo_dp_inst + 6; 1273 1274 /* Mapping of APG register blocks to HPO DP block instance: 1275 * APG[0] -> HPO_DP[0] 1276 * APG[1] -> HPO_DP[1] 1277 * APG[2] -> HPO_DP[2] 1278 * APG[3] -> HPO_DP[3] 1279 */ 1280 apg_inst = hpo_dp_inst; 1281 1282 /* allocate HPO stream encoder and create VPG sub-block */ 1283 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1284 vpg = dcn32_vpg_create(ctx, vpg_inst); 1285 apg = dcn31_apg_create(ctx, apg_inst); 1286 1287 if (!hpo_dp_enc31 || !vpg || !apg) { 1288 kfree(hpo_dp_enc31); 1289 kfree(vpg); 1290 kfree(apg); 1291 return NULL; 1292 } 1293 1294 #undef REG_STRUCT 1295 #define REG_STRUCT hpo_dp_stream_enc_regs 1296 hpo_dp_stream_encoder_reg_init(0), 1297 hpo_dp_stream_encoder_reg_init(1), 1298 hpo_dp_stream_encoder_reg_init(2), 1299 hpo_dp_stream_encoder_reg_init(3); 1300 1301 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1302 hpo_dp_inst, eng_id, vpg, apg, 1303 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1304 &hpo_dp_se_shift, &hpo_dp_se_mask); 1305 1306 return &hpo_dp_enc31->base; 1307 } 1308 1309 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1310 uint8_t inst, 1311 struct dc_context *ctx) 1312 { 1313 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1314 1315 /* allocate HPO link encoder */ 1316 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1317 1318 #undef REG_STRUCT 1319 #define REG_STRUCT hpo_dp_link_enc_regs 1320 hpo_dp_link_encoder_reg_init(0), 1321 hpo_dp_link_encoder_reg_init(1); 1322 1323 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1324 &hpo_dp_link_enc_regs[inst], 1325 &hpo_dp_le_shift, &hpo_dp_le_mask); 1326 1327 return &hpo_dp_enc31->base; 1328 } 1329 1330 static struct dce_hwseq *dcn32_hwseq_create( 1331 struct dc_context *ctx) 1332 { 1333 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1334 1335 #undef REG_STRUCT 1336 #define REG_STRUCT hwseq_reg 1337 hwseq_reg_init(); 1338 1339 if (hws) { 1340 hws->ctx = ctx; 1341 hws->regs = &hwseq_reg; 1342 hws->shifts = &hwseq_shift; 1343 hws->masks = &hwseq_mask; 1344 } 1345 return hws; 1346 } 1347 static const struct resource_create_funcs res_create_funcs = { 1348 .read_dce_straps = read_dce_straps, 1349 .create_audio = dcn32_create_audio, 1350 .create_stream_encoder = dcn32_stream_encoder_create, 1351 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1352 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1353 .create_hwseq = dcn32_hwseq_create, 1354 }; 1355 1356 static const struct resource_create_funcs res_create_maximus_funcs = { 1357 .read_dce_straps = NULL, 1358 .create_audio = NULL, 1359 .create_stream_encoder = NULL, 1360 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1361 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1362 .create_hwseq = dcn32_hwseq_create, 1363 }; 1364 1365 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1366 { 1367 unsigned int i; 1368 1369 for (i = 0; i < pool->base.stream_enc_count; i++) { 1370 if (pool->base.stream_enc[i] != NULL) { 1371 if (pool->base.stream_enc[i]->vpg != NULL) { 1372 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1373 pool->base.stream_enc[i]->vpg = NULL; 1374 } 1375 if (pool->base.stream_enc[i]->afmt != NULL) { 1376 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1377 pool->base.stream_enc[i]->afmt = NULL; 1378 } 1379 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1380 pool->base.stream_enc[i] = NULL; 1381 } 1382 } 1383 1384 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1385 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1386 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1387 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1388 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1389 } 1390 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1391 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1392 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1393 } 1394 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1395 pool->base.hpo_dp_stream_enc[i] = NULL; 1396 } 1397 } 1398 1399 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1400 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1401 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1402 pool->base.hpo_dp_link_enc[i] = NULL; 1403 } 1404 } 1405 1406 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1407 if (pool->base.dscs[i] != NULL) 1408 dcn20_dsc_destroy(&pool->base.dscs[i]); 1409 } 1410 1411 if (pool->base.mpc != NULL) { 1412 kfree(TO_DCN20_MPC(pool->base.mpc)); 1413 pool->base.mpc = NULL; 1414 } 1415 if (pool->base.hubbub != NULL) { 1416 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1417 pool->base.hubbub = NULL; 1418 } 1419 for (i = 0; i < pool->base.pipe_count; i++) { 1420 if (pool->base.dpps[i] != NULL) 1421 dcn32_dpp_destroy(&pool->base.dpps[i]); 1422 1423 if (pool->base.ipps[i] != NULL) 1424 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1425 1426 if (pool->base.hubps[i] != NULL) { 1427 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1428 pool->base.hubps[i] = NULL; 1429 } 1430 1431 if (pool->base.irqs != NULL) { 1432 dal_irq_service_destroy(&pool->base.irqs); 1433 } 1434 } 1435 1436 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1437 if (pool->base.engines[i] != NULL) 1438 dce110_engine_destroy(&pool->base.engines[i]); 1439 if (pool->base.hw_i2cs[i] != NULL) { 1440 kfree(pool->base.hw_i2cs[i]); 1441 pool->base.hw_i2cs[i] = NULL; 1442 } 1443 if (pool->base.sw_i2cs[i] != NULL) { 1444 kfree(pool->base.sw_i2cs[i]); 1445 pool->base.sw_i2cs[i] = NULL; 1446 } 1447 } 1448 1449 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1450 if (pool->base.opps[i] != NULL) 1451 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1452 } 1453 1454 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1455 if (pool->base.timing_generators[i] != NULL) { 1456 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1457 pool->base.timing_generators[i] = NULL; 1458 } 1459 } 1460 1461 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1462 if (pool->base.dwbc[i] != NULL) { 1463 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1464 pool->base.dwbc[i] = NULL; 1465 } 1466 if (pool->base.mcif_wb[i] != NULL) { 1467 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1468 pool->base.mcif_wb[i] = NULL; 1469 } 1470 } 1471 1472 for (i = 0; i < pool->base.audio_count; i++) { 1473 if (pool->base.audios[i]) 1474 dce_aud_destroy(&pool->base.audios[i]); 1475 } 1476 1477 for (i = 0; i < pool->base.clk_src_count; i++) { 1478 if (pool->base.clock_sources[i] != NULL) { 1479 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1480 pool->base.clock_sources[i] = NULL; 1481 } 1482 } 1483 1484 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1485 if (pool->base.mpc_lut[i] != NULL) { 1486 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1487 pool->base.mpc_lut[i] = NULL; 1488 } 1489 if (pool->base.mpc_shaper[i] != NULL) { 1490 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1491 pool->base.mpc_shaper[i] = NULL; 1492 } 1493 } 1494 1495 if (pool->base.dp_clock_source != NULL) { 1496 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1497 pool->base.dp_clock_source = NULL; 1498 } 1499 1500 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1501 if (pool->base.multiple_abms[i] != NULL) 1502 dce_abm_destroy(&pool->base.multiple_abms[i]); 1503 } 1504 1505 if (pool->base.psr != NULL) 1506 dmub_psr_destroy(&pool->base.psr); 1507 1508 if (pool->base.dccg != NULL) 1509 dcn_dccg_destroy(&pool->base.dccg); 1510 1511 if (pool->base.oem_device != NULL) { 1512 struct dc *dc = pool->base.oem_device->ctx->dc; 1513 1514 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1515 } 1516 } 1517 1518 1519 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1520 { 1521 int i; 1522 uint32_t dwb_count = pool->res_cap->num_dwb; 1523 1524 for (i = 0; i < dwb_count; i++) { 1525 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1526 GFP_KERNEL); 1527 1528 if (!dwbc30) { 1529 dm_error("DC: failed to create dwbc30!\n"); 1530 return false; 1531 } 1532 1533 #undef REG_STRUCT 1534 #define REG_STRUCT dwbc30_regs 1535 dwbc_regs_dcn3_init(0); 1536 1537 dcn30_dwbc_construct(dwbc30, ctx, 1538 &dwbc30_regs[i], 1539 &dwbc30_shift, 1540 &dwbc30_mask, 1541 i); 1542 1543 pool->dwbc[i] = &dwbc30->base; 1544 } 1545 return true; 1546 } 1547 1548 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1549 { 1550 int i; 1551 uint32_t dwb_count = pool->res_cap->num_dwb; 1552 1553 for (i = 0; i < dwb_count; i++) { 1554 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1555 GFP_KERNEL); 1556 1557 if (!mcif_wb30) { 1558 dm_error("DC: failed to create mcif_wb30!\n"); 1559 return false; 1560 } 1561 1562 #undef REG_STRUCT 1563 #define REG_STRUCT mcif_wb30_regs 1564 mcif_wb_regs_dcn3_init(0); 1565 1566 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1567 &mcif_wb30_regs[i], 1568 &mcif_wb30_shift, 1569 &mcif_wb30_mask, 1570 i); 1571 1572 pool->mcif_wb[i] = &mcif_wb30->base; 1573 } 1574 return true; 1575 } 1576 1577 static struct display_stream_compressor *dcn32_dsc_create( 1578 struct dc_context *ctx, uint32_t inst) 1579 { 1580 struct dcn20_dsc *dsc = 1581 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1582 1583 if (!dsc) { 1584 BREAK_TO_DEBUGGER(); 1585 return NULL; 1586 } 1587 1588 #undef REG_STRUCT 1589 #define REG_STRUCT dsc_regs 1590 dsc_regsDCN20_init(0), 1591 dsc_regsDCN20_init(1), 1592 dsc_regsDCN20_init(2), 1593 dsc_regsDCN20_init(3); 1594 1595 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1596 1597 dsc->max_image_width = 6016; 1598 1599 return &dsc->base; 1600 } 1601 1602 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1603 { 1604 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1605 1606 dcn32_resource_destruct(dcn32_pool); 1607 kfree(dcn32_pool); 1608 *pool = NULL; 1609 } 1610 1611 bool dcn32_acquire_post_bldn_3dlut( 1612 struct resource_context *res_ctx, 1613 const struct resource_pool *pool, 1614 int mpcc_id, 1615 struct dc_3dlut **lut, 1616 struct dc_transfer_func **shaper) 1617 { 1618 bool ret = false; 1619 1620 ASSERT(*lut == NULL && *shaper == NULL); 1621 *lut = NULL; 1622 *shaper = NULL; 1623 1624 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1625 *lut = pool->mpc_lut[mpcc_id]; 1626 *shaper = pool->mpc_shaper[mpcc_id]; 1627 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1628 ret = true; 1629 } 1630 return ret; 1631 } 1632 1633 bool dcn32_release_post_bldn_3dlut( 1634 struct resource_context *res_ctx, 1635 const struct resource_pool *pool, 1636 struct dc_3dlut **lut, 1637 struct dc_transfer_func **shaper) 1638 { 1639 int i; 1640 bool ret = false; 1641 1642 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1643 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1644 res_ctx->is_mpc_3dlut_acquired[i] = false; 1645 pool->mpc_lut[i]->state.raw = 0; 1646 *lut = NULL; 1647 *shaper = NULL; 1648 ret = true; 1649 break; 1650 } 1651 } 1652 return ret; 1653 } 1654 1655 static void dcn32_enable_phantom_plane(struct dc *dc, 1656 struct dc_state *context, 1657 struct dc_stream_state *phantom_stream, 1658 unsigned int dc_pipe_idx) 1659 { 1660 struct dc_plane_state *phantom_plane = NULL; 1661 struct dc_plane_state *prev_phantom_plane = NULL; 1662 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1663 1664 while (curr_pipe) { 1665 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1666 phantom_plane = prev_phantom_plane; 1667 else 1668 phantom_plane = dc_create_plane_state(dc); 1669 1670 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1671 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1672 sizeof(phantom_plane->scaling_quality)); 1673 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1674 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1675 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1676 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1677 sizeof(phantom_plane->plane_size)); 1678 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1679 sizeof(phantom_plane->tiling_info)); 1680 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1681 phantom_plane->format = curr_pipe->plane_state->format; 1682 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1683 phantom_plane->visible = curr_pipe->plane_state->visible; 1684 1685 /* Shadow pipe has small viewport. */ 1686 phantom_plane->clip_rect.y = 0; 1687 phantom_plane->clip_rect.height = phantom_stream->src.height; 1688 1689 phantom_plane->is_phantom = true; 1690 1691 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1692 1693 curr_pipe = curr_pipe->bottom_pipe; 1694 prev_phantom_plane = phantom_plane; 1695 } 1696 } 1697 1698 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1699 struct dc_state *context, 1700 display_e2e_pipe_params_st *pipes, 1701 unsigned int pipe_cnt, 1702 unsigned int dc_pipe_idx) 1703 { 1704 struct dc_stream_state *phantom_stream = NULL; 1705 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1706 1707 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1708 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1709 phantom_stream->dpms_off = true; 1710 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1711 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1712 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1713 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1714 1715 /* stream has limited viewport and small timing */ 1716 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1717 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1718 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1719 DC_FP_START(); 1720 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1721 DC_FP_END(); 1722 1723 dc_add_stream_to_ctx(dc, context, phantom_stream); 1724 return phantom_stream; 1725 } 1726 1727 void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) 1728 { 1729 int i; 1730 struct dc_plane_state *phantom_plane = NULL; 1731 struct dc_stream_state *phantom_stream = NULL; 1732 1733 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1734 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1735 1736 if (!pipe->top_pipe && !pipe->prev_odm_pipe && 1737 pipe->plane_state && pipe->stream && 1738 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1739 phantom_plane = pipe->plane_state; 1740 phantom_stream = pipe->stream; 1741 1742 dc_plane_state_retain(phantom_plane); 1743 dc_stream_retain(phantom_stream); 1744 } 1745 } 1746 } 1747 1748 // return true if removed piped from ctx, false otherwise 1749 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update) 1750 { 1751 int i; 1752 bool removed_pipe = false; 1753 struct dc_plane_state *phantom_plane = NULL; 1754 struct dc_stream_state *phantom_stream = NULL; 1755 1756 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1757 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1758 // build scaling params for phantom pipes 1759 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1760 phantom_plane = pipe->plane_state; 1761 phantom_stream = pipe->stream; 1762 1763 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1764 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1765 1766 /* Ref count is incremented on allocation and also when added to the context. 1767 * Therefore we must call release for the the phantom plane and stream once 1768 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1769 */ 1770 dc_plane_state_release(phantom_plane); 1771 dc_stream_release(phantom_stream); 1772 1773 removed_pipe = true; 1774 } 1775 1776 /* For non-full updates, a shallow copy of the current state 1777 * is created. In this case we don't want to erase the current 1778 * state (there can be 2 HIRQL threads, one in flip, and one in 1779 * checkMPO) that can cause a race condition. 1780 * 1781 * This is just a workaround, needs a proper fix. 1782 */ 1783 if (!fast_update) { 1784 // Clear all phantom stream info 1785 if (pipe->stream) { 1786 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1787 pipe->stream->mall_stream_config.paired_stream = NULL; 1788 } 1789 1790 if (pipe->plane_state) { 1791 pipe->plane_state->is_phantom = false; 1792 } 1793 } 1794 } 1795 return removed_pipe; 1796 } 1797 1798 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1799 * require a phantom pipe / stream 1800 */ 1801 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1802 display_e2e_pipe_params_st *pipes, 1803 unsigned int pipe_cnt, 1804 unsigned int index) 1805 { 1806 struct dc_stream_state *phantom_stream = NULL; 1807 unsigned int i; 1808 1809 // The index of the DC pipe passed into this function is guarenteed to 1810 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1811 // already have phantom pipe assigned, etc.) by previous checks. 1812 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1813 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1814 1815 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1816 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1817 1818 // Build scaling params for phantom pipes which were newly added. 1819 // We determine which phantom pipes were added by comparing with 1820 // the phantom stream. 1821 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1822 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1823 pipe->stream->use_dynamic_meta = false; 1824 pipe->plane_state->flip_immediate = false; 1825 if (!resource_build_scaling_params(pipe)) { 1826 // Log / remove phantom pipes since failed to build scaling params 1827 } 1828 } 1829 } 1830 } 1831 1832 bool dcn32_validate_bandwidth(struct dc *dc, 1833 struct dc_state *context, 1834 bool fast_validate) 1835 { 1836 bool out = false; 1837 1838 BW_VAL_TRACE_SETUP(); 1839 1840 int vlevel = 0; 1841 int pipe_cnt = 0; 1842 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1843 struct mall_temp_config mall_temp_config; 1844 1845 /* To handle Freesync properly, setting FreeSync DML parameters 1846 * to its default state for the first stage of validation 1847 */ 1848 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1849 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1850 1851 DC_LOGGER_INIT(dc->ctx->logger); 1852 1853 /* For fast validation, there are situations where a shallow copy of 1854 * of the dc->current_state is created for the validation. In this case 1855 * we want to save and restore the mall config because we always 1856 * teardown subvp at the beginning of validation (and don't attempt 1857 * to add it back if it's fast validation). If we don't restore the 1858 * subvp config in cases of fast validation + shallow copy of the 1859 * dc->current_state, the dc->current_state will have a partially 1860 * removed subvp state when we did not intend to remove it. 1861 */ 1862 if (fast_validate) { 1863 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1864 dcn32_save_mall_state(dc, context, &mall_temp_config); 1865 } 1866 1867 BW_VAL_TRACE_COUNT(); 1868 1869 DC_FP_START(); 1870 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1871 DC_FP_END(); 1872 1873 if (fast_validate) 1874 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1875 1876 if (pipe_cnt == 0) 1877 goto validate_out; 1878 1879 if (!out) 1880 goto validate_fail; 1881 1882 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1883 1884 if (fast_validate) { 1885 BW_VAL_TRACE_SKIP(fast); 1886 goto validate_out; 1887 } 1888 1889 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1890 1891 BW_VAL_TRACE_END_WATERMARKS(); 1892 1893 goto validate_out; 1894 1895 validate_fail: 1896 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1897 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1898 1899 BW_VAL_TRACE_SKIP(fail); 1900 out = false; 1901 1902 validate_out: 1903 kfree(pipes); 1904 1905 BW_VAL_TRACE_FINISH(); 1906 1907 return out; 1908 } 1909 1910 int dcn32_populate_dml_pipes_from_context( 1911 struct dc *dc, struct dc_state *context, 1912 display_e2e_pipe_params_st *pipes, 1913 bool fast_validate) 1914 { 1915 int i, pipe_cnt; 1916 struct resource_context *res_ctx = &context->res_ctx; 1917 struct pipe_ctx *pipe; 1918 bool subvp_in_use = false; 1919 struct dc_crtc_timing *timing; 1920 bool vsr_odm_support = false; 1921 1922 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1923 1924 /* Determine whether we will apply ODM 2to1 policy: 1925 * Applies to single display and where the number of planes is less than 3. 1926 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1927 * 1928 * Apply pipe split policy first so we can predict the pipe split correctly 1929 * (dcn32_predict_pipe_split). 1930 */ 1931 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1932 if (!res_ctx->pipe_ctx[i].stream) 1933 continue; 1934 pipe = &res_ctx->pipe_ctx[i]; 1935 timing = &pipe->stream->timing; 1936 1937 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1938 vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 && 1939 res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width); 1940 if (context->stream_count == 1 && 1941 context->stream_status[0].plane_count == 1 && 1942 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1943 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1944 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1945 dc->debug.enable_single_display_2to1_odm_policy && 1946 !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr 1947 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1948 } 1949 pipe_cnt++; 1950 } 1951 1952 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1953 1954 if (!res_ctx->pipe_ctx[i].stream) 1955 continue; 1956 pipe = &res_ctx->pipe_ctx[i]; 1957 timing = &pipe->stream->timing; 1958 1959 pipes[pipe_cnt].pipe.src.gpuvm = true; 1960 DC_FP_START(); 1961 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1962 DC_FP_END(); 1963 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1964 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1965 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1966 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1967 1968 /* Only populate DML input with subvp info for full updates. 1969 * This is just a workaround -- needs a proper fix. 1970 */ 1971 if (!fast_validate) { 1972 switch (pipe->stream->mall_stream_config.type) { 1973 case SUBVP_MAIN: 1974 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1975 subvp_in_use = true; 1976 break; 1977 case SUBVP_PHANTOM: 1978 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1979 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1980 // Disallow unbounded req for SubVP according to DCHUB programming guide 1981 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1982 break; 1983 case SUBVP_NONE: 1984 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1985 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1986 break; 1987 default: 1988 break; 1989 } 1990 } 1991 1992 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1993 if (pipes[pipe_cnt].dout.dsc_enable) { 1994 switch (timing->display_color_depth) { 1995 case COLOR_DEPTH_888: 1996 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1997 break; 1998 case COLOR_DEPTH_101010: 1999 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 2000 break; 2001 case COLOR_DEPTH_121212: 2002 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2003 break; 2004 default: 2005 ASSERT(0); 2006 break; 2007 } 2008 } 2009 2010 DC_FP_START(); 2011 dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 2012 DC_FP_END(); 2013 2014 pipe_cnt++; 2015 } 2016 2017 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2018 * the DET available for each pipe). Use the DET override input to maintain our driver 2019 * policy. 2020 */ 2021 dcn32_set_det_allocations(dc, context, pipes); 2022 2023 // In general cases we want to keep the dram clock change requirement 2024 // (prefer configs that support MCLK switch). Only override to false 2025 // for SubVP 2026 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) 2027 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2028 else 2029 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2030 2031 return pipe_cnt; 2032 } 2033 2034 static struct dc_cap_funcs cap_funcs = { 2035 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2036 }; 2037 2038 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2039 display_e2e_pipe_params_st *pipes, 2040 int pipe_cnt, 2041 int vlevel) 2042 { 2043 DC_FP_START(); 2044 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2045 DC_FP_END(); 2046 } 2047 2048 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2049 { 2050 DC_FP_START(); 2051 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2052 DC_FP_END(); 2053 } 2054 2055 static struct resource_funcs dcn32_res_pool_funcs = { 2056 .destroy = dcn32_destroy_resource_pool, 2057 .link_enc_create = dcn32_link_encoder_create, 2058 .link_enc_create_minimal = NULL, 2059 .panel_cntl_create = dcn32_panel_cntl_create, 2060 .validate_bandwidth = dcn32_validate_bandwidth, 2061 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2062 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2063 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2064 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2065 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2066 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2067 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2068 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2069 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2070 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2071 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2072 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2073 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2074 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2075 .add_phantom_pipes = dcn32_add_phantom_pipes, 2076 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2077 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 2078 .save_mall_state = dcn32_save_mall_state, 2079 .restore_mall_state = dcn32_restore_mall_state, 2080 }; 2081 2082 static uint32_t read_pipe_fuses(struct dc_context *ctx) 2083 { 2084 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2085 /* DCN32 support max 4 pipes */ 2086 value = value & 0xf; 2087 return value; 2088 } 2089 2090 2091 static bool dcn32_resource_construct( 2092 uint8_t num_virtual_links, 2093 struct dc *dc, 2094 struct dcn32_resource_pool *pool) 2095 { 2096 int i, j; 2097 struct dc_context *ctx = dc->ctx; 2098 struct irq_service_init_data init_data; 2099 struct ddc_service_init_data ddc_init_data = {0}; 2100 uint32_t pipe_fuses = 0; 2101 uint32_t num_pipes = 4; 2102 2103 #undef REG_STRUCT 2104 #define REG_STRUCT bios_regs 2105 bios_regs_init(); 2106 2107 #undef REG_STRUCT 2108 #define REG_STRUCT clk_src_regs 2109 clk_src_regs_init(0, A), 2110 clk_src_regs_init(1, B), 2111 clk_src_regs_init(2, C), 2112 clk_src_regs_init(3, D), 2113 clk_src_regs_init(4, E); 2114 2115 #undef REG_STRUCT 2116 #define REG_STRUCT abm_regs 2117 abm_regs_init(0), 2118 abm_regs_init(1), 2119 abm_regs_init(2), 2120 abm_regs_init(3); 2121 2122 #undef REG_STRUCT 2123 #define REG_STRUCT dccg_regs 2124 dccg_regs_init(); 2125 2126 DC_FP_START(); 2127 2128 ctx->dc_bios->regs = &bios_regs; 2129 2130 pool->base.res_cap = &res_cap_dcn32; 2131 /* max number of pipes for ASIC before checking for pipe fuses */ 2132 num_pipes = pool->base.res_cap->num_timing_generator; 2133 pipe_fuses = read_pipe_fuses(ctx); 2134 2135 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2136 if (pipe_fuses & 1 << i) 2137 num_pipes--; 2138 2139 if (pipe_fuses & 1) 2140 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2141 2142 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2143 ASSERT(0); //Entire DCN is harvested! 2144 2145 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2146 * value will be changed, update max_num_dpp and max_num_otg for dml. 2147 */ 2148 dcn3_2_ip.max_num_dpp = num_pipes; 2149 dcn3_2_ip.max_num_otg = num_pipes; 2150 2151 pool->base.funcs = &dcn32_res_pool_funcs; 2152 2153 /************************************************* 2154 * Resource + asic cap harcoding * 2155 *************************************************/ 2156 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2157 pool->base.timing_generator_count = num_pipes; 2158 pool->base.pipe_count = num_pipes; 2159 pool->base.mpcc_count = num_pipes; 2160 dc->caps.max_downscale_ratio = 600; 2161 dc->caps.i2c_speed_in_khz = 100; 2162 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2163 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2164 dc->caps.max_cursor_size = 64; 2165 dc->caps.min_horizontal_blanking_period = 80; 2166 dc->caps.dmdata_alloc_size = 2048; 2167 dc->caps.mall_size_per_mem_channel = 4; 2168 dc->caps.mall_size_total = 0; 2169 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2170 2171 dc->caps.cache_line_size = 64; 2172 dc->caps.cache_num_ways = 16; 2173 2174 /* Calculate the available MALL space */ 2175 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2176 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2177 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2178 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2179 2180 dc->caps.subvp_fw_processing_delay_us = 15; 2181 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2182 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2183 dc->caps.subvp_swath_height_margin_lines = 16; 2184 dc->caps.subvp_pstate_allow_width_us = 20; 2185 dc->caps.subvp_vertical_int_margin_us = 30; 2186 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2187 2188 dc->caps.max_slave_planes = 2; 2189 dc->caps.max_slave_yuv_planes = 2; 2190 dc->caps.max_slave_rgb_planes = 2; 2191 dc->caps.post_blend_color_processing = true; 2192 dc->caps.force_dp_tps4_for_cp2520 = true; 2193 if (dc->config.forceHBR2CP2520) 2194 dc->caps.force_dp_tps4_for_cp2520 = false; 2195 dc->caps.dp_hpo = true; 2196 dc->caps.dp_hdmi21_pcon_support = true; 2197 dc->caps.edp_dsc_support = true; 2198 dc->caps.extended_aux_timeout_support = true; 2199 dc->caps.dmcub_support = true; 2200 dc->caps.seamless_odm = true; 2201 2202 /* Color pipeline capabilities */ 2203 dc->caps.color.dpp.dcn_arch = 1; 2204 dc->caps.color.dpp.input_lut_shared = 0; 2205 dc->caps.color.dpp.icsc = 1; 2206 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2207 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2208 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2209 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2210 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2211 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2212 dc->caps.color.dpp.post_csc = 1; 2213 dc->caps.color.dpp.gamma_corr = 1; 2214 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2215 2216 dc->caps.color.dpp.hw_3d_lut = 1; 2217 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2218 // no OGAM ROM on DCN2 and later ASICs 2219 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2220 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2221 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2222 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2223 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2224 dc->caps.color.dpp.ocsc = 0; 2225 2226 dc->caps.color.mpc.gamut_remap = 1; 2227 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2228 dc->caps.color.mpc.ogam_ram = 1; 2229 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2230 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2231 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2232 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2233 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2234 dc->caps.color.mpc.ocsc = 1; 2235 2236 /* Use pipe context based otg sync logic */ 2237 dc->config.use_pipe_ctx_sync_logic = true; 2238 2239 /* read VBIOS LTTPR caps */ 2240 { 2241 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2242 enum bp_result bp_query_result; 2243 uint8_t is_vbios_lttpr_enable = 0; 2244 2245 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2246 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2247 } 2248 2249 /* interop bit is implicit */ 2250 { 2251 dc->caps.vbios_lttpr_aware = true; 2252 } 2253 } 2254 2255 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2256 dc->debug = debug_defaults_drv; 2257 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2258 dc->debug = debug_defaults_diags; 2259 } else 2260 dc->debug = debug_defaults_diags; 2261 // Init the vm_helper 2262 if (dc->vm_helper) 2263 vm_helper_init(dc->vm_helper, 16); 2264 2265 /************************************************* 2266 * Create resources * 2267 *************************************************/ 2268 2269 /* Clock Sources for Pixel Clock*/ 2270 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2271 dcn32_clock_source_create(ctx, ctx->dc_bios, 2272 CLOCK_SOURCE_COMBO_PHY_PLL0, 2273 &clk_src_regs[0], false); 2274 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2275 dcn32_clock_source_create(ctx, ctx->dc_bios, 2276 CLOCK_SOURCE_COMBO_PHY_PLL1, 2277 &clk_src_regs[1], false); 2278 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2279 dcn32_clock_source_create(ctx, ctx->dc_bios, 2280 CLOCK_SOURCE_COMBO_PHY_PLL2, 2281 &clk_src_regs[2], false); 2282 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2283 dcn32_clock_source_create(ctx, ctx->dc_bios, 2284 CLOCK_SOURCE_COMBO_PHY_PLL3, 2285 &clk_src_regs[3], false); 2286 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2287 dcn32_clock_source_create(ctx, ctx->dc_bios, 2288 CLOCK_SOURCE_COMBO_PHY_PLL4, 2289 &clk_src_regs[4], false); 2290 2291 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2292 2293 /* todo: not reuse phy_pll registers */ 2294 pool->base.dp_clock_source = 2295 dcn32_clock_source_create(ctx, ctx->dc_bios, 2296 CLOCK_SOURCE_ID_DP_DTO, 2297 &clk_src_regs[0], true); 2298 2299 for (i = 0; i < pool->base.clk_src_count; i++) { 2300 if (pool->base.clock_sources[i] == NULL) { 2301 dm_error("DC: failed to create clock sources!\n"); 2302 BREAK_TO_DEBUGGER(); 2303 goto create_fail; 2304 } 2305 } 2306 2307 /* DCCG */ 2308 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2309 if (pool->base.dccg == NULL) { 2310 dm_error("DC: failed to create dccg!\n"); 2311 BREAK_TO_DEBUGGER(); 2312 goto create_fail; 2313 } 2314 2315 /* DML */ 2316 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2317 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2318 2319 /* IRQ Service */ 2320 init_data.ctx = dc->ctx; 2321 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2322 if (!pool->base.irqs) 2323 goto create_fail; 2324 2325 /* HUBBUB */ 2326 pool->base.hubbub = dcn32_hubbub_create(ctx); 2327 if (pool->base.hubbub == NULL) { 2328 BREAK_TO_DEBUGGER(); 2329 dm_error("DC: failed to create hubbub!\n"); 2330 goto create_fail; 2331 } 2332 2333 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2334 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2335 2336 /* if pipe is disabled, skip instance of HW pipe, 2337 * i.e, skip ASIC register instance 2338 */ 2339 if (pipe_fuses & 1 << i) 2340 continue; 2341 2342 /* HUBPs */ 2343 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2344 if (pool->base.hubps[j] == NULL) { 2345 BREAK_TO_DEBUGGER(); 2346 dm_error( 2347 "DC: failed to create hubps!\n"); 2348 goto create_fail; 2349 } 2350 2351 /* DPPs */ 2352 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2353 if (pool->base.dpps[j] == NULL) { 2354 BREAK_TO_DEBUGGER(); 2355 dm_error( 2356 "DC: failed to create dpps!\n"); 2357 goto create_fail; 2358 } 2359 2360 /* OPPs */ 2361 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2362 if (pool->base.opps[j] == NULL) { 2363 BREAK_TO_DEBUGGER(); 2364 dm_error( 2365 "DC: failed to create output pixel processor!\n"); 2366 goto create_fail; 2367 } 2368 2369 /* TGs */ 2370 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2371 ctx, i); 2372 if (pool->base.timing_generators[j] == NULL) { 2373 BREAK_TO_DEBUGGER(); 2374 dm_error("DC: failed to create tg!\n"); 2375 goto create_fail; 2376 } 2377 2378 /* ABMs */ 2379 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2380 &abm_regs[i], 2381 &abm_shift, 2382 &abm_mask); 2383 if (pool->base.multiple_abms[j] == NULL) { 2384 dm_error("DC: failed to create abm for pipe %d!\n", i); 2385 BREAK_TO_DEBUGGER(); 2386 goto create_fail; 2387 } 2388 2389 /* index for resource pool arrays for next valid pipe */ 2390 j++; 2391 } 2392 2393 /* PSR */ 2394 pool->base.psr = dmub_psr_create(ctx); 2395 if (pool->base.psr == NULL) { 2396 dm_error("DC: failed to create psr obj!\n"); 2397 BREAK_TO_DEBUGGER(); 2398 goto create_fail; 2399 } 2400 2401 /* MPCCs */ 2402 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2403 if (pool->base.mpc == NULL) { 2404 BREAK_TO_DEBUGGER(); 2405 dm_error("DC: failed to create mpc!\n"); 2406 goto create_fail; 2407 } 2408 2409 /* DSCs */ 2410 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2411 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2412 if (pool->base.dscs[i] == NULL) { 2413 BREAK_TO_DEBUGGER(); 2414 dm_error("DC: failed to create display stream compressor %d!\n", i); 2415 goto create_fail; 2416 } 2417 } 2418 2419 /* DWB */ 2420 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2421 BREAK_TO_DEBUGGER(); 2422 dm_error("DC: failed to create dwbc!\n"); 2423 goto create_fail; 2424 } 2425 2426 /* MMHUBBUB */ 2427 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2428 BREAK_TO_DEBUGGER(); 2429 dm_error("DC: failed to create mcif_wb!\n"); 2430 goto create_fail; 2431 } 2432 2433 /* AUX and I2C */ 2434 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2435 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2436 if (pool->base.engines[i] == NULL) { 2437 BREAK_TO_DEBUGGER(); 2438 dm_error( 2439 "DC:failed to create aux engine!!\n"); 2440 goto create_fail; 2441 } 2442 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2443 if (pool->base.hw_i2cs[i] == NULL) { 2444 BREAK_TO_DEBUGGER(); 2445 dm_error( 2446 "DC:failed to create hw i2c!!\n"); 2447 goto create_fail; 2448 } 2449 pool->base.sw_i2cs[i] = NULL; 2450 } 2451 2452 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2453 if (!resource_construct(num_virtual_links, dc, &pool->base, 2454 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2455 &res_create_funcs : &res_create_maximus_funcs))) 2456 goto create_fail; 2457 2458 /* HW Sequencer init functions and Plane caps */ 2459 dcn32_hw_sequencer_init_functions(dc); 2460 2461 dc->caps.max_planes = pool->base.pipe_count; 2462 2463 for (i = 0; i < dc->caps.max_planes; ++i) 2464 dc->caps.planes[i] = plane_cap; 2465 2466 dc->cap_funcs = cap_funcs; 2467 2468 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2469 ddc_init_data.ctx = dc->ctx; 2470 ddc_init_data.link = NULL; 2471 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2472 ddc_init_data.id.enum_id = 0; 2473 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2474 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2475 } else { 2476 pool->base.oem_device = NULL; 2477 } 2478 2479 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2480 dc->config.sdpif_request_limit_words_per_umc = 16; 2481 2482 DC_FP_END(); 2483 2484 return true; 2485 2486 create_fail: 2487 2488 DC_FP_END(); 2489 2490 dcn32_resource_destruct(pool); 2491 2492 return false; 2493 } 2494 2495 struct resource_pool *dcn32_create_resource_pool( 2496 const struct dc_init_data *init_data, 2497 struct dc *dc) 2498 { 2499 struct dcn32_resource_pool *pool = 2500 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2501 2502 if (!pool) 2503 return NULL; 2504 2505 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2506 return &pool->base; 2507 2508 BREAK_TO_DEBUGGER(); 2509 kfree(pool); 2510 return NULL; 2511 } 2512 2513 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2514 struct resource_context *res_ctx, 2515 const struct resource_pool *pool, 2516 const struct pipe_ctx *primary_pipe) 2517 { 2518 int i; 2519 struct pipe_ctx *secondary_pipe = NULL; 2520 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2521 int primary_index, preferred_pipe_idx; 2522 struct pipe_ctx *old_primary_pipe = NULL; 2523 2524 /* 2525 * Modified from find_idle_secondary_pipe 2526 * With windowed MPO and ODM, we want to avoid the case where we want a 2527 * free pipe for the left side but the free pipe is being used on the 2528 * right side. 2529 * Add check on current_state if the primary_pipe is the left side, 2530 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2531 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2532 * - If so, then don't use this pipe 2533 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2534 * - in this case, the primary pipe has already gotten a free pipe for the 2535 * MPO window in the left 2536 * - when it tries to get a free pipe for the MPO window on the right, 2537 * it will see that it is already assigned to the right side 2538 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2539 * free pipe, since it will be for the right side. So add an 2540 * additional condition, that skipping the free pipe on the right only 2541 * applies if the primary pipe has no bottom pipe currently assigned 2542 */ 2543 if (primary_pipe) { 2544 primary_index = primary_pipe->pipe_idx; 2545 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2546 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2547 && (!primary_pipe->bottom_pipe)) 2548 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2549 2550 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2551 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2552 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2553 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2554 secondary_pipe->pipe_idx = preferred_pipe_idx; 2555 } 2556 } 2557 2558 /* 2559 * search backwards for the second pipe to keep pipe 2560 * assignment more consistent 2561 */ 2562 if (!secondary_pipe) 2563 for (i = pool->pipe_count - 1; i >= 0; i--) { 2564 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2565 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2566 secondary_pipe = &res_ctx->pipe_ctx[i]; 2567 secondary_pipe->pipe_idx = i; 2568 break; 2569 } 2570 } 2571 2572 return secondary_pipe; 2573 } 2574 2575 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2576 struct dc_state *state, 2577 const struct resource_pool *pool, 2578 struct dc_stream_state *stream, 2579 struct pipe_ctx *head_pipe) 2580 { 2581 struct resource_context *res_ctx = &state->res_ctx; 2582 struct pipe_ctx *idle_pipe, *pipe; 2583 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2584 int head_index; 2585 2586 if (!head_pipe) 2587 ASSERT(0); 2588 2589 /* 2590 * Modified from dcn20_acquire_idle_pipe_for_layer 2591 * Check if head_pipe in old_context already has bottom_pipe allocated. 2592 * - If so, check if that pipe is available in the current context. 2593 * -- If so, reuse pipe from old_context 2594 */ 2595 head_index = head_pipe->pipe_idx; 2596 pipe = &old_ctx->pipe_ctx[head_index]; 2597 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2598 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2599 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2600 } else { 2601 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2602 if (!idle_pipe) 2603 return NULL; 2604 } 2605 2606 idle_pipe->stream = head_pipe->stream; 2607 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2608 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2609 2610 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2611 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2612 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2613 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2614 2615 return idle_pipe; 2616 } 2617 2618 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2619 { 2620 /* 2621 * DCN32 and DCN321 SKUs may have different sizes for MALL 2622 * but we may not be able to access all the MALL space. 2623 * If the num_chans is power of 2, then we can access all 2624 * of the available MALL space. Otherwise, we can only 2625 * access: 2626 * 2627 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2628 * ((2^floor(log2(num_chans)))/num_chans) 2629 * 2630 * Calculating the MALL sizes for all available SKUs, we 2631 * have come up with the follow simplified check. 2632 * - we have max_chans which provides the max MALL size. 2633 * Each chans supports 4MB of MALL so: 2634 * 2635 * total_cache_size_in_bytes = max_chans * 4 MB 2636 * 2637 * - we have avail_chans which shows the number of channels 2638 * we can use if we can't access the entire MALL space. 2639 * It is generally half of max_chans 2640 * - so we use the following checks: 2641 * 2642 * if (num_chans == max_chans), return max_chans 2643 * if (num_chans < max_chans), return avail_chans 2644 * 2645 * - exception is GC_11_0_0 where we can't access max_chans, 2646 * so we define max_avail_chans as the maximum available 2647 * MALL space 2648 * 2649 */ 2650 int gc_11_0_0_max_chans = 48; 2651 int gc_11_0_0_max_avail_chans = 32; 2652 int gc_11_0_0_avail_chans = 16; 2653 int gc_11_0_3_max_chans = 16; 2654 int gc_11_0_3_avail_chans = 8; 2655 int gc_11_0_2_max_chans = 8; 2656 int gc_11_0_2_avail_chans = 4; 2657 2658 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2659 return (num_chans == gc_11_0_0_max_chans) ? 2660 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2661 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2662 return (num_chans == gc_11_0_2_max_chans) ? 2663 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2664 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2665 return (num_chans == gc_11_0_3_max_chans) ? 2666 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2667 } 2668 } 2669