1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dc_link_dp.h" 61 #include "dcn31/dcn31_apg.h" 62 #include "dcn31/dcn31_dio_link_encoder.h" 63 #include "dcn32/dcn32_dio_link_encoder.h" 64 #include "dce/dce_clock_source.h" 65 #include "dce/dce_audio.h" 66 #include "dce/dce_hwseq.h" 67 #include "clk_mgr.h" 68 #include "virtual/virtual_stream_encoder.h" 69 #include "dml/display_mode_vba.h" 70 #include "dcn32/dcn32_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dc_link_ddc.h" 73 #include "dcn31/dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn32/dcn32_mmhubbub.h" 77 78 #include "dcn/dcn_3_2_0_offset.h" 79 #include "dcn/dcn_3_2_0_sh_mask.h" 80 #include "nbio/nbio_4_3_0_offset.h" 81 82 #include "reg_helper.h" 83 #include "dce/dmub_abm.h" 84 #include "dce/dmub_psr.h" 85 #include "dce/dce_aux.h" 86 #include "dce/dce_i2c.h" 87 88 #include "dml/dcn30/display_mode_vba_30.h" 89 #include "vm_helper.h" 90 #include "dcn20/dcn20_vmid.h" 91 #include "dml/dcn32/dcn32_fpu.h" 92 93 #define DCN_BASE__INST0_SEG1 0x000000C0 94 #define DCN_BASE__INST0_SEG2 0x000034C0 95 #define DCN_BASE__INST0_SEG3 0x00009000 96 #define NBIO_BASE__INST0_SEG1 0x00000014 97 98 #define MAX_INSTANCE 6 99 #define MAX_SEGMENT 6 100 101 struct IP_BASE_INSTANCE { 102 unsigned int segment[MAX_SEGMENT]; 103 }; 104 105 struct IP_BASE { 106 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 107 }; 108 109 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } } } }; 115 116 #define DC_LOGGER_INIT(logger) 117 118 enum dcn32_clk_src_array_id { 119 DCN32_CLK_SRC_PLL0, 120 DCN32_CLK_SRC_PLL1, 121 DCN32_CLK_SRC_PLL2, 122 DCN32_CLK_SRC_PLL3, 123 DCN32_CLK_SRC_PLL4, 124 DCN32_CLK_SRC_TOTAL 125 }; 126 127 /* begin ********************* 128 * macros to expend register list macro defined in HW object header file 129 */ 130 131 /* DCN */ 132 /* TODO awful hack. fixup dcn20_dwb.h */ 133 #undef BASE_INNER 134 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 135 136 #define BASE(seg) BASE_INNER(seg) 137 138 #define SR(reg_name)\ 139 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 140 reg ## reg_name 141 142 #define SRI(reg_name, block, id)\ 143 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 reg ## block ## id ## _ ## reg_name 145 146 #define SRI2(reg_name, block, id)\ 147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 150 #define SRIR(var_name, reg_name, block, id)\ 151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## reg_name 153 154 #define SRII(reg_name, block, id)\ 155 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII_MPC_RMU(reg_name, block, id)\ 159 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_DWB(reg_name, temp_name, block, id)\ 163 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## temp_name 165 166 #define DCCG_SRII(reg_name, block, id)\ 167 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## reg_name 169 170 #define VUPDATE_SRII(reg_name, block, id)\ 171 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 172 reg ## reg_name ## _ ## block ## id 173 174 /* NBIO */ 175 #define NBIO_BASE_INNER(seg) \ 176 NBIO_BASE__INST0_SEG ## seg 177 178 #define NBIO_BASE(seg) \ 179 NBIO_BASE_INNER(seg) 180 181 #define NBIO_SR(reg_name)\ 182 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 183 regBIF_BX0_ ## reg_name 184 185 #undef CTX 186 #define CTX ctx 187 #define REG(reg_name) \ 188 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 189 190 static const struct bios_registers bios_regs = { 191 NBIO_SR(BIOS_SCRATCH_3), 192 NBIO_SR(BIOS_SCRATCH_6) 193 }; 194 195 #define clk_src_regs(index, pllid)\ 196 [index] = {\ 197 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 198 } 199 200 static const struct dce110_clk_src_regs clk_src_regs[] = { 201 clk_src_regs(0, A), 202 clk_src_regs(1, B), 203 clk_src_regs(2, C), 204 clk_src_regs(3, D), 205 clk_src_regs(4, E) 206 }; 207 208 static const struct dce110_clk_src_shift cs_shift = { 209 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 210 }; 211 212 static const struct dce110_clk_src_mask cs_mask = { 213 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 214 }; 215 216 #define abm_regs(id)\ 217 [id] = {\ 218 ABM_DCN32_REG_LIST(id)\ 219 } 220 221 static const struct dce_abm_registers abm_regs[] = { 222 abm_regs(0), 223 abm_regs(1), 224 abm_regs(2), 225 abm_regs(3), 226 }; 227 228 static const struct dce_abm_shift abm_shift = { 229 ABM_MASK_SH_LIST_DCN32(__SHIFT) 230 }; 231 232 static const struct dce_abm_mask abm_mask = { 233 ABM_MASK_SH_LIST_DCN32(_MASK) 234 }; 235 236 #define audio_regs(id)\ 237 [id] = {\ 238 AUD_COMMON_REG_LIST(id)\ 239 } 240 241 static const struct dce_audio_registers audio_regs[] = { 242 audio_regs(0), 243 audio_regs(1), 244 audio_regs(2), 245 audio_regs(3), 246 audio_regs(4) 247 }; 248 249 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 250 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 251 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 252 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 253 254 static const struct dce_audio_shift audio_shift = { 255 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 256 }; 257 258 static const struct dce_audio_mask audio_mask = { 259 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 260 }; 261 262 #define vpg_regs(id)\ 263 [id] = {\ 264 VPG_DCN3_REG_LIST(id)\ 265 } 266 267 static const struct dcn30_vpg_registers vpg_regs[] = { 268 vpg_regs(0), 269 vpg_regs(1), 270 vpg_regs(2), 271 vpg_regs(3), 272 vpg_regs(4), 273 vpg_regs(5), 274 vpg_regs(6), 275 vpg_regs(7), 276 vpg_regs(8), 277 vpg_regs(9), 278 }; 279 280 static const struct dcn30_vpg_shift vpg_shift = { 281 DCN3_VPG_MASK_SH_LIST(__SHIFT) 282 }; 283 284 static const struct dcn30_vpg_mask vpg_mask = { 285 DCN3_VPG_MASK_SH_LIST(_MASK) 286 }; 287 288 #define afmt_regs(id)\ 289 [id] = {\ 290 AFMT_DCN3_REG_LIST(id)\ 291 } 292 293 static const struct dcn30_afmt_registers afmt_regs[] = { 294 afmt_regs(0), 295 afmt_regs(1), 296 afmt_regs(2), 297 afmt_regs(3), 298 afmt_regs(4), 299 afmt_regs(5) 300 }; 301 302 static const struct dcn30_afmt_shift afmt_shift = { 303 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 304 }; 305 306 static const struct dcn30_afmt_mask afmt_mask = { 307 DCN3_AFMT_MASK_SH_LIST(_MASK) 308 }; 309 310 #define apg_regs(id)\ 311 [id] = {\ 312 APG_DCN31_REG_LIST(id)\ 313 } 314 315 static const struct dcn31_apg_registers apg_regs[] = { 316 apg_regs(0), 317 apg_regs(1), 318 apg_regs(2), 319 apg_regs(3) 320 }; 321 322 static const struct dcn31_apg_shift apg_shift = { 323 DCN31_APG_MASK_SH_LIST(__SHIFT) 324 }; 325 326 static const struct dcn31_apg_mask apg_mask = { 327 DCN31_APG_MASK_SH_LIST(_MASK) 328 }; 329 330 #define stream_enc_regs(id)\ 331 [id] = {\ 332 SE_DCN32_REG_LIST(id)\ 333 } 334 335 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 336 stream_enc_regs(0), 337 stream_enc_regs(1), 338 stream_enc_regs(2), 339 stream_enc_regs(3), 340 stream_enc_regs(4) 341 }; 342 343 static const struct dcn10_stream_encoder_shift se_shift = { 344 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 345 }; 346 347 static const struct dcn10_stream_encoder_mask se_mask = { 348 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 349 }; 350 351 352 #define aux_regs(id)\ 353 [id] = {\ 354 DCN2_AUX_REG_LIST(id)\ 355 } 356 357 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 358 aux_regs(0), 359 aux_regs(1), 360 aux_regs(2), 361 aux_regs(3), 362 aux_regs(4) 363 }; 364 365 #define hpd_regs(id)\ 366 [id] = {\ 367 HPD_REG_LIST(id)\ 368 } 369 370 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 371 hpd_regs(0), 372 hpd_regs(1), 373 hpd_regs(2), 374 hpd_regs(3), 375 hpd_regs(4) 376 }; 377 378 #define link_regs(id, phyid)\ 379 [id] = {\ 380 LE_DCN31_REG_LIST(id), \ 381 UNIPHY_DCN2_REG_LIST(phyid), \ 382 /*DPCS_DCN31_REG_LIST(id),*/ \ 383 } 384 385 static const struct dcn10_link_enc_registers link_enc_regs[] = { 386 link_regs(0, A), 387 link_regs(1, B), 388 link_regs(2, C), 389 link_regs(3, D), 390 link_regs(4, E) 391 }; 392 393 static const struct dcn10_link_enc_shift le_shift = { 394 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 395 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 396 }; 397 398 static const struct dcn10_link_enc_mask le_mask = { 399 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 400 401 //DPCS_DCN31_MASK_SH_LIST(_MASK) 402 }; 403 404 #define hpo_dp_stream_encoder_reg_list(id)\ 405 [id] = {\ 406 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 407 } 408 409 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 410 hpo_dp_stream_encoder_reg_list(0), 411 hpo_dp_stream_encoder_reg_list(1), 412 hpo_dp_stream_encoder_reg_list(2), 413 hpo_dp_stream_encoder_reg_list(3), 414 }; 415 416 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 417 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 418 }; 419 420 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 421 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 422 }; 423 424 425 #define hpo_dp_link_encoder_reg_list(id)\ 426 [id] = {\ 427 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 428 /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ 429 /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ 430 /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ 431 /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ 432 /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ 433 } 434 435 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 436 hpo_dp_link_encoder_reg_list(0), 437 hpo_dp_link_encoder_reg_list(1), 438 }; 439 440 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 441 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 442 }; 443 444 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 445 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 446 }; 447 448 #define dpp_regs(id)\ 449 [id] = {\ 450 DPP_REG_LIST_DCN30_COMMON(id),\ 451 } 452 453 static const struct dcn3_dpp_registers dpp_regs[] = { 454 dpp_regs(0), 455 dpp_regs(1), 456 dpp_regs(2), 457 dpp_regs(3) 458 }; 459 460 static const struct dcn3_dpp_shift tf_shift = { 461 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 462 }; 463 464 static const struct dcn3_dpp_mask tf_mask = { 465 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 466 }; 467 468 469 #define opp_regs(id)\ 470 [id] = {\ 471 OPP_REG_LIST_DCN30(id),\ 472 } 473 474 static const struct dcn20_opp_registers opp_regs[] = { 475 opp_regs(0), 476 opp_regs(1), 477 opp_regs(2), 478 opp_regs(3) 479 }; 480 481 static const struct dcn20_opp_shift opp_shift = { 482 OPP_MASK_SH_LIST_DCN20(__SHIFT) 483 }; 484 485 static const struct dcn20_opp_mask opp_mask = { 486 OPP_MASK_SH_LIST_DCN20(_MASK) 487 }; 488 489 #define aux_engine_regs(id)\ 490 [id] = {\ 491 AUX_COMMON_REG_LIST0(id), \ 492 .AUXN_IMPCAL = 0, \ 493 .AUXP_IMPCAL = 0, \ 494 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 495 } 496 497 static const struct dce110_aux_registers aux_engine_regs[] = { 498 aux_engine_regs(0), 499 aux_engine_regs(1), 500 aux_engine_regs(2), 501 aux_engine_regs(3), 502 aux_engine_regs(4) 503 }; 504 505 static const struct dce110_aux_registers_shift aux_shift = { 506 DCN_AUX_MASK_SH_LIST(__SHIFT) 507 }; 508 509 static const struct dce110_aux_registers_mask aux_mask = { 510 DCN_AUX_MASK_SH_LIST(_MASK) 511 }; 512 513 514 #define dwbc_regs_dcn3(id)\ 515 [id] = {\ 516 DWBC_COMMON_REG_LIST_DCN30(id),\ 517 } 518 519 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 520 dwbc_regs_dcn3(0), 521 }; 522 523 static const struct dcn30_dwbc_shift dwbc30_shift = { 524 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 525 }; 526 527 static const struct dcn30_dwbc_mask dwbc30_mask = { 528 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 529 }; 530 531 #define mcif_wb_regs_dcn3(id)\ 532 [id] = {\ 533 MCIF_WB_COMMON_REG_LIST_DCN32(id),\ 534 } 535 536 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 537 mcif_wb_regs_dcn3(0) 538 }; 539 540 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 541 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 542 }; 543 544 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 545 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 546 }; 547 548 #define dsc_regsDCN20(id)\ 549 [id] = {\ 550 DSC_REG_LIST_DCN20(id)\ 551 } 552 553 static const struct dcn20_dsc_registers dsc_regs[] = { 554 dsc_regsDCN20(0), 555 dsc_regsDCN20(1), 556 dsc_regsDCN20(2), 557 dsc_regsDCN20(3) 558 }; 559 560 static const struct dcn20_dsc_shift dsc_shift = { 561 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 562 }; 563 564 static const struct dcn20_dsc_mask dsc_mask = { 565 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 566 }; 567 568 static const struct dcn30_mpc_registers mpc_regs = { 569 MPC_REG_LIST_DCN3_2(0), 570 MPC_REG_LIST_DCN3_2(1), 571 MPC_REG_LIST_DCN3_2(2), 572 MPC_REG_LIST_DCN3_2(3), 573 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 574 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 575 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 576 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 577 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 578 }; 579 580 static const struct dcn30_mpc_shift mpc_shift = { 581 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 582 }; 583 584 static const struct dcn30_mpc_mask mpc_mask = { 585 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 586 }; 587 588 #define optc_regs(id)\ 589 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} 590 591 //#ifdef DIAGS_BUILD 592 //static struct dcn_optc_registers optc_regs[] = { 593 //#else 594 static const struct dcn_optc_registers optc_regs[] = { 595 //#endif 596 optc_regs(0), 597 optc_regs(1), 598 optc_regs(2), 599 optc_regs(3) 600 }; 601 602 static const struct dcn_optc_shift optc_shift = { 603 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 604 }; 605 606 static const struct dcn_optc_mask optc_mask = { 607 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 608 }; 609 610 #define hubp_regs(id)\ 611 [id] = {\ 612 HUBP_REG_LIST_DCN32(id)\ 613 } 614 615 static const struct dcn_hubp2_registers hubp_regs[] = { 616 hubp_regs(0), 617 hubp_regs(1), 618 hubp_regs(2), 619 hubp_regs(3) 620 }; 621 622 623 static const struct dcn_hubp2_shift hubp_shift = { 624 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 625 }; 626 627 static const struct dcn_hubp2_mask hubp_mask = { 628 HUBP_MASK_SH_LIST_DCN32(_MASK) 629 }; 630 static const struct dcn_hubbub_registers hubbub_reg = { 631 HUBBUB_REG_LIST_DCN32(0) 632 }; 633 634 static const struct dcn_hubbub_shift hubbub_shift = { 635 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 636 }; 637 638 static const struct dcn_hubbub_mask hubbub_mask = { 639 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 640 }; 641 642 static const struct dccg_registers dccg_regs = { 643 DCCG_REG_LIST_DCN32() 644 }; 645 646 static const struct dccg_shift dccg_shift = { 647 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 648 }; 649 650 static const struct dccg_mask dccg_mask = { 651 DCCG_MASK_SH_LIST_DCN32(_MASK) 652 }; 653 654 655 #define SRII2(reg_name_pre, reg_name_post, id)\ 656 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 657 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 658 reg ## reg_name_pre ## id ## _ ## reg_name_post 659 660 661 #define HWSEQ_DCN32_REG_LIST()\ 662 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 663 SR(DIO_MEM_PWR_CTRL), \ 664 SR(ODM_MEM_PWR_CTRL3), \ 665 SR(MMHUBBUB_MEM_PWR_CNTL), \ 666 SR(DCCG_GATE_DISABLE_CNTL), \ 667 SR(DCCG_GATE_DISABLE_CNTL2), \ 668 SR(DCFCLK_CNTL),\ 669 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 670 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 671 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 672 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 673 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 674 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 675 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 676 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 677 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 678 SR(MICROSECOND_TIME_BASE_DIV), \ 679 SR(MILLISECOND_TIME_BASE_DIV), \ 680 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 681 SR(RBBMIF_TIMEOUT_DIS), \ 682 SR(RBBMIF_TIMEOUT_DIS_2), \ 683 SR(DCHUBBUB_CRC_CTRL), \ 684 SR(DPP_TOP0_DPP_CRC_CTRL), \ 685 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 686 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 687 SR(MPC_CRC_CTRL), \ 688 SR(MPC_CRC_RESULT_GB), \ 689 SR(MPC_CRC_RESULT_C), \ 690 SR(MPC_CRC_RESULT_AR), \ 691 SR(DOMAIN0_PG_CONFIG), \ 692 SR(DOMAIN1_PG_CONFIG), \ 693 SR(DOMAIN2_PG_CONFIG), \ 694 SR(DOMAIN3_PG_CONFIG), \ 695 SR(DOMAIN16_PG_CONFIG), \ 696 SR(DOMAIN17_PG_CONFIG), \ 697 SR(DOMAIN18_PG_CONFIG), \ 698 SR(DOMAIN19_PG_CONFIG), \ 699 SR(DOMAIN0_PG_STATUS), \ 700 SR(DOMAIN1_PG_STATUS), \ 701 SR(DOMAIN2_PG_STATUS), \ 702 SR(DOMAIN3_PG_STATUS), \ 703 SR(DOMAIN16_PG_STATUS), \ 704 SR(DOMAIN17_PG_STATUS), \ 705 SR(DOMAIN18_PG_STATUS), \ 706 SR(DOMAIN19_PG_STATUS), \ 707 SR(D1VGA_CONTROL), \ 708 SR(D2VGA_CONTROL), \ 709 SR(D3VGA_CONTROL), \ 710 SR(D4VGA_CONTROL), \ 711 SR(D5VGA_CONTROL), \ 712 SR(D6VGA_CONTROL), \ 713 SR(DC_IP_REQUEST_CNTL), \ 714 SR(AZALIA_AUDIO_DTO), \ 715 SR(AZALIA_CONTROLLER_CLOCK_GATING) 716 717 static const struct dce_hwseq_registers hwseq_reg = { 718 HWSEQ_DCN32_REG_LIST() 719 }; 720 721 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 722 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 723 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 724 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 725 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 726 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 727 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 728 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 729 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 730 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 731 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 732 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 733 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 734 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 735 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 736 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 737 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 738 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 741 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 743 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 744 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 745 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 746 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 747 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 748 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 749 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 750 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 751 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 752 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 753 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 754 755 static const struct dce_hwseq_shift hwseq_shift = { 756 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 757 }; 758 759 static const struct dce_hwseq_mask hwseq_mask = { 760 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 761 }; 762 #define vmid_regs(id)\ 763 [id] = {\ 764 DCN20_VMID_REG_LIST(id)\ 765 } 766 767 static const struct dcn_vmid_registers vmid_regs[] = { 768 vmid_regs(0), 769 vmid_regs(1), 770 vmid_regs(2), 771 vmid_regs(3), 772 vmid_regs(4), 773 vmid_regs(5), 774 vmid_regs(6), 775 vmid_regs(7), 776 vmid_regs(8), 777 vmid_regs(9), 778 vmid_regs(10), 779 vmid_regs(11), 780 vmid_regs(12), 781 vmid_regs(13), 782 vmid_regs(14), 783 vmid_regs(15) 784 }; 785 786 static const struct dcn20_vmid_shift vmid_shifts = { 787 DCN20_VMID_MASK_SH_LIST(__SHIFT) 788 }; 789 790 static const struct dcn20_vmid_mask vmid_masks = { 791 DCN20_VMID_MASK_SH_LIST(_MASK) 792 }; 793 794 static const struct resource_caps res_cap_dcn32 = { 795 .num_timing_generator = 4, 796 .num_opp = 4, 797 .num_video_plane = 4, 798 .num_audio = 5, 799 .num_stream_encoder = 5, 800 .num_hpo_dp_stream_encoder = 4, 801 .num_hpo_dp_link_encoder = 2, 802 .num_pll = 5, 803 .num_dwb = 1, 804 .num_ddc = 5, 805 .num_vmid = 16, 806 .num_mpc_3dlut = 4, 807 .num_dsc = 4, 808 }; 809 810 static const struct dc_plane_cap plane_cap = { 811 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 812 .blends_with_above = true, 813 .blends_with_below = true, 814 .per_pixel_alpha = true, 815 816 .pixel_format_support = { 817 .argb8888 = true, 818 .nv12 = true, 819 .fp16 = true, 820 .p010 = true, 821 .ayuv = false, 822 }, 823 824 .max_upscale_factor = { 825 .argb8888 = 16000, 826 .nv12 = 16000, 827 .fp16 = 16000 828 }, 829 830 // 6:1 downscaling ratio: 1000/6 = 166.666 831 .max_downscale_factor = { 832 .argb8888 = 167, 833 .nv12 = 167, 834 .fp16 = 167 835 }, 836 64, 837 64 838 }; 839 840 static const struct dc_debug_options debug_defaults_drv = { 841 .disable_dmcu = true, 842 .force_abm_enable = false, 843 .timing_trace = false, 844 .clock_trace = true, 845 .disable_pplib_clock_request = false, 846 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 847 .force_single_disp_pipe_split = false, 848 .disable_dcc = DCC_ENABLE, 849 .vsr_support = true, 850 .performance_trace = false, 851 .max_downscale_src_width = 7680,/*upto 8K*/ 852 .disable_pplib_wm_range = false, 853 .scl_reset_length10 = true, 854 .sanity_checks = false, 855 .underflow_assert_delay_us = 0xFFFFFFFF, 856 .dwb_fi_phase = -1, // -1 = disable, 857 .dmub_command_table = true, 858 .enable_mem_low_power = { 859 .bits = { 860 .vga = false, 861 .i2c = false, 862 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 863 .dscl = false, 864 .cm = false, 865 .mpc = false, 866 .optc = true, 867 } 868 }, 869 .use_max_lb = true, 870 .force_disable_subvp = true, 871 .enable_single_display_2to1_odm_policy = true, 872 .enable_dp_dig_pixel_rate_div_policy = 1, 873 }; 874 875 static const struct dc_debug_options debug_defaults_diags = { 876 .disable_dmcu = true, 877 .force_abm_enable = false, 878 .timing_trace = true, 879 .clock_trace = true, 880 .disable_dpp_power_gate = true, 881 .disable_hubp_power_gate = true, 882 .disable_dsc_power_gate = true, 883 .disable_clock_gate = true, 884 .disable_pplib_clock_request = true, 885 .disable_pplib_wm_range = true, 886 .disable_stutter = false, 887 .scl_reset_length10 = true, 888 .dwb_fi_phase = -1, // -1 = disable 889 .dmub_command_table = true, 890 .enable_tri_buf = true, 891 .use_max_lb = true, 892 .force_disable_subvp = true 893 }; 894 895 static struct dce_aux *dcn32_aux_engine_create( 896 struct dc_context *ctx, 897 uint32_t inst) 898 { 899 struct aux_engine_dce110 *aux_engine = 900 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 901 902 if (!aux_engine) 903 return NULL; 904 905 dce110_aux_engine_construct(aux_engine, ctx, inst, 906 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 907 &aux_engine_regs[inst], 908 &aux_mask, 909 &aux_shift, 910 ctx->dc->caps.extended_aux_timeout_support); 911 912 return &aux_engine->base; 913 } 914 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 915 916 static const struct dce_i2c_registers i2c_hw_regs[] = { 917 i2c_inst_regs(1), 918 i2c_inst_regs(2), 919 i2c_inst_regs(3), 920 i2c_inst_regs(4), 921 i2c_inst_regs(5), 922 }; 923 924 static const struct dce_i2c_shift i2c_shifts = { 925 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 926 }; 927 928 static const struct dce_i2c_mask i2c_masks = { 929 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 930 }; 931 932 static struct dce_i2c_hw *dcn32_i2c_hw_create( 933 struct dc_context *ctx, 934 uint32_t inst) 935 { 936 struct dce_i2c_hw *dce_i2c_hw = 937 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 938 939 if (!dce_i2c_hw) 940 return NULL; 941 942 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 943 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 944 945 return dce_i2c_hw; 946 } 947 948 static struct clock_source *dcn32_clock_source_create( 949 struct dc_context *ctx, 950 struct dc_bios *bios, 951 enum clock_source_id id, 952 const struct dce110_clk_src_regs *regs, 953 bool dp_clk_src) 954 { 955 struct dce110_clk_src *clk_src = 956 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 957 958 if (!clk_src) 959 return NULL; 960 961 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 962 regs, &cs_shift, &cs_mask)) { 963 clk_src->base.dp_clk_src = dp_clk_src; 964 return &clk_src->base; 965 } 966 967 BREAK_TO_DEBUGGER(); 968 return NULL; 969 } 970 971 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 972 { 973 int i; 974 975 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 976 GFP_KERNEL); 977 978 if (!hubbub2) 979 return NULL; 980 981 hubbub32_construct(hubbub2, ctx, 982 &hubbub_reg, 983 &hubbub_shift, 984 &hubbub_mask, 985 ctx->dc->dml.ip.det_buffer_size_kbytes, 986 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 987 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 988 989 990 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 991 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 992 993 vmid->ctx = ctx; 994 995 vmid->regs = &vmid_regs[i]; 996 vmid->shifts = &vmid_shifts; 997 vmid->masks = &vmid_masks; 998 } 999 1000 return &hubbub2->base; 1001 } 1002 1003 static struct hubp *dcn32_hubp_create( 1004 struct dc_context *ctx, 1005 uint32_t inst) 1006 { 1007 struct dcn20_hubp *hubp2 = 1008 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1009 1010 if (!hubp2) 1011 return NULL; 1012 1013 if (hubp32_construct(hubp2, ctx, inst, 1014 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1015 return &hubp2->base; 1016 1017 BREAK_TO_DEBUGGER(); 1018 kfree(hubp2); 1019 return NULL; 1020 } 1021 1022 static void dcn32_dpp_destroy(struct dpp **dpp) 1023 { 1024 kfree(TO_DCN30_DPP(*dpp)); 1025 *dpp = NULL; 1026 } 1027 1028 static struct dpp *dcn32_dpp_create( 1029 struct dc_context *ctx, 1030 uint32_t inst) 1031 { 1032 struct dcn3_dpp *dpp3 = 1033 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1034 1035 if (!dpp3) 1036 return NULL; 1037 1038 if (dpp32_construct(dpp3, ctx, inst, 1039 &dpp_regs[inst], &tf_shift, &tf_mask)) 1040 return &dpp3->base; 1041 1042 BREAK_TO_DEBUGGER(); 1043 kfree(dpp3); 1044 return NULL; 1045 } 1046 1047 static struct mpc *dcn32_mpc_create( 1048 struct dc_context *ctx, 1049 int num_mpcc, 1050 int num_rmu) 1051 { 1052 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1053 GFP_KERNEL); 1054 1055 if (!mpc30) 1056 return NULL; 1057 1058 dcn32_mpc_construct(mpc30, ctx, 1059 &mpc_regs, 1060 &mpc_shift, 1061 &mpc_mask, 1062 num_mpcc, 1063 num_rmu); 1064 1065 return &mpc30->base; 1066 } 1067 1068 static struct output_pixel_processor *dcn32_opp_create( 1069 struct dc_context *ctx, uint32_t inst) 1070 { 1071 struct dcn20_opp *opp2 = 1072 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1073 1074 if (!opp2) { 1075 BREAK_TO_DEBUGGER(); 1076 return NULL; 1077 } 1078 1079 dcn20_opp_construct(opp2, ctx, inst, 1080 &opp_regs[inst], &opp_shift, &opp_mask); 1081 return &opp2->base; 1082 } 1083 1084 1085 static struct timing_generator *dcn32_timing_generator_create( 1086 struct dc_context *ctx, 1087 uint32_t instance) 1088 { 1089 struct optc *tgn10 = 1090 kzalloc(sizeof(struct optc), GFP_KERNEL); 1091 1092 if (!tgn10) 1093 return NULL; 1094 1095 tgn10->base.inst = instance; 1096 tgn10->base.ctx = ctx; 1097 1098 tgn10->tg_regs = &optc_regs[instance]; 1099 tgn10->tg_shift = &optc_shift; 1100 tgn10->tg_mask = &optc_mask; 1101 1102 dcn32_timing_generator_init(tgn10); 1103 1104 return &tgn10->base; 1105 } 1106 1107 static const struct encoder_feature_support link_enc_feature = { 1108 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1109 .max_hdmi_pixel_clock = 600000, 1110 .hdmi_ycbcr420_supported = true, 1111 .dp_ycbcr420_supported = true, 1112 .fec_supported = true, 1113 .flags.bits.IS_HBR2_CAPABLE = true, 1114 .flags.bits.IS_HBR3_CAPABLE = true, 1115 .flags.bits.IS_TPS3_CAPABLE = true, 1116 .flags.bits.IS_TPS4_CAPABLE = true 1117 }; 1118 1119 static struct link_encoder *dcn32_link_encoder_create( 1120 const struct encoder_init_data *enc_init_data) 1121 { 1122 struct dcn20_link_encoder *enc20 = 1123 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1124 1125 if (!enc20) 1126 return NULL; 1127 1128 dcn32_link_encoder_construct(enc20, 1129 enc_init_data, 1130 &link_enc_feature, 1131 &link_enc_regs[enc_init_data->transmitter], 1132 &link_enc_aux_regs[enc_init_data->channel - 1], 1133 &link_enc_hpd_regs[enc_init_data->hpd_source], 1134 &le_shift, 1135 &le_mask); 1136 1137 return &enc20->enc10.base; 1138 } 1139 1140 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1141 { 1142 struct dcn31_panel_cntl *panel_cntl = 1143 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1144 1145 if (!panel_cntl) 1146 return NULL; 1147 1148 dcn31_panel_cntl_construct(panel_cntl, init_data); 1149 1150 return &panel_cntl->base; 1151 } 1152 1153 static void read_dce_straps( 1154 struct dc_context *ctx, 1155 struct resource_straps *straps) 1156 { 1157 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1158 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1159 1160 } 1161 1162 static struct audio *dcn32_create_audio( 1163 struct dc_context *ctx, unsigned int inst) 1164 { 1165 return dce_audio_create(ctx, inst, 1166 &audio_regs[inst], &audio_shift, &audio_mask); 1167 } 1168 1169 static struct vpg *dcn32_vpg_create( 1170 struct dc_context *ctx, 1171 uint32_t inst) 1172 { 1173 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1174 1175 if (!vpg3) 1176 return NULL; 1177 1178 vpg3_construct(vpg3, ctx, inst, 1179 &vpg_regs[inst], 1180 &vpg_shift, 1181 &vpg_mask); 1182 1183 return &vpg3->base; 1184 } 1185 1186 static struct afmt *dcn32_afmt_create( 1187 struct dc_context *ctx, 1188 uint32_t inst) 1189 { 1190 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1191 1192 if (!afmt3) 1193 return NULL; 1194 1195 afmt3_construct(afmt3, ctx, inst, 1196 &afmt_regs[inst], 1197 &afmt_shift, 1198 &afmt_mask); 1199 1200 return &afmt3->base; 1201 } 1202 1203 static struct apg *dcn31_apg_create( 1204 struct dc_context *ctx, 1205 uint32_t inst) 1206 { 1207 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1208 1209 if (!apg31) 1210 return NULL; 1211 1212 apg31_construct(apg31, ctx, inst, 1213 &apg_regs[inst], 1214 &apg_shift, 1215 &apg_mask); 1216 1217 return &apg31->base; 1218 } 1219 1220 static struct stream_encoder *dcn32_stream_encoder_create( 1221 enum engine_id eng_id, 1222 struct dc_context *ctx) 1223 { 1224 struct dcn10_stream_encoder *enc1; 1225 struct vpg *vpg; 1226 struct afmt *afmt; 1227 int vpg_inst; 1228 int afmt_inst; 1229 1230 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1231 if (eng_id <= ENGINE_ID_DIGF) { 1232 vpg_inst = eng_id; 1233 afmt_inst = eng_id; 1234 } else 1235 return NULL; 1236 1237 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1238 vpg = dcn32_vpg_create(ctx, vpg_inst); 1239 afmt = dcn32_afmt_create(ctx, afmt_inst); 1240 1241 if (!enc1 || !vpg || !afmt) { 1242 kfree(enc1); 1243 kfree(vpg); 1244 kfree(afmt); 1245 return NULL; 1246 } 1247 1248 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1249 eng_id, vpg, afmt, 1250 &stream_enc_regs[eng_id], 1251 &se_shift, &se_mask); 1252 1253 return &enc1->base; 1254 } 1255 1256 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1257 enum engine_id eng_id, 1258 struct dc_context *ctx) 1259 { 1260 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1261 struct vpg *vpg; 1262 struct apg *apg; 1263 uint32_t hpo_dp_inst; 1264 uint32_t vpg_inst; 1265 uint32_t apg_inst; 1266 1267 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1268 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1269 1270 /* Mapping of VPG register blocks to HPO DP block instance: 1271 * VPG[6] -> HPO_DP[0] 1272 * VPG[7] -> HPO_DP[1] 1273 * VPG[8] -> HPO_DP[2] 1274 * VPG[9] -> HPO_DP[3] 1275 */ 1276 vpg_inst = hpo_dp_inst + 6; 1277 1278 /* Mapping of APG register blocks to HPO DP block instance: 1279 * APG[0] -> HPO_DP[0] 1280 * APG[1] -> HPO_DP[1] 1281 * APG[2] -> HPO_DP[2] 1282 * APG[3] -> HPO_DP[3] 1283 */ 1284 apg_inst = hpo_dp_inst; 1285 1286 /* allocate HPO stream encoder and create VPG sub-block */ 1287 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1288 vpg = dcn32_vpg_create(ctx, vpg_inst); 1289 apg = dcn31_apg_create(ctx, apg_inst); 1290 1291 if (!hpo_dp_enc31 || !vpg || !apg) { 1292 kfree(hpo_dp_enc31); 1293 kfree(vpg); 1294 kfree(apg); 1295 return NULL; 1296 } 1297 1298 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1299 hpo_dp_inst, eng_id, vpg, apg, 1300 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1301 &hpo_dp_se_shift, &hpo_dp_se_mask); 1302 1303 return &hpo_dp_enc31->base; 1304 } 1305 1306 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1307 uint8_t inst, 1308 struct dc_context *ctx) 1309 { 1310 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1311 1312 /* allocate HPO link encoder */ 1313 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1314 1315 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1316 &hpo_dp_link_enc_regs[inst], 1317 &hpo_dp_le_shift, &hpo_dp_le_mask); 1318 1319 return &hpo_dp_enc31->base; 1320 } 1321 1322 static struct dce_hwseq *dcn32_hwseq_create( 1323 struct dc_context *ctx) 1324 { 1325 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1326 1327 if (hws) { 1328 hws->ctx = ctx; 1329 hws->regs = &hwseq_reg; 1330 hws->shifts = &hwseq_shift; 1331 hws->masks = &hwseq_mask; 1332 } 1333 return hws; 1334 } 1335 static const struct resource_create_funcs res_create_funcs = { 1336 .read_dce_straps = read_dce_straps, 1337 .create_audio = dcn32_create_audio, 1338 .create_stream_encoder = dcn32_stream_encoder_create, 1339 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1340 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1341 .create_hwseq = dcn32_hwseq_create, 1342 }; 1343 1344 static const struct resource_create_funcs res_create_maximus_funcs = { 1345 .read_dce_straps = NULL, 1346 .create_audio = NULL, 1347 .create_stream_encoder = NULL, 1348 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1349 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1350 .create_hwseq = dcn32_hwseq_create, 1351 }; 1352 1353 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1354 { 1355 unsigned int i; 1356 1357 for (i = 0; i < pool->base.stream_enc_count; i++) { 1358 if (pool->base.stream_enc[i] != NULL) { 1359 if (pool->base.stream_enc[i]->vpg != NULL) { 1360 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1361 pool->base.stream_enc[i]->vpg = NULL; 1362 } 1363 if (pool->base.stream_enc[i]->afmt != NULL) { 1364 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1365 pool->base.stream_enc[i]->afmt = NULL; 1366 } 1367 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1368 pool->base.stream_enc[i] = NULL; 1369 } 1370 } 1371 1372 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1373 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1374 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1375 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1376 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1377 } 1378 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1379 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1380 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1381 } 1382 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1383 pool->base.hpo_dp_stream_enc[i] = NULL; 1384 } 1385 } 1386 1387 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1388 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1389 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1390 pool->base.hpo_dp_link_enc[i] = NULL; 1391 } 1392 } 1393 1394 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1395 if (pool->base.dscs[i] != NULL) 1396 dcn20_dsc_destroy(&pool->base.dscs[i]); 1397 } 1398 1399 if (pool->base.mpc != NULL) { 1400 kfree(TO_DCN20_MPC(pool->base.mpc)); 1401 pool->base.mpc = NULL; 1402 } 1403 if (pool->base.hubbub != NULL) { 1404 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1405 pool->base.hubbub = NULL; 1406 } 1407 for (i = 0; i < pool->base.pipe_count; i++) { 1408 if (pool->base.dpps[i] != NULL) 1409 dcn32_dpp_destroy(&pool->base.dpps[i]); 1410 1411 if (pool->base.ipps[i] != NULL) 1412 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1413 1414 if (pool->base.hubps[i] != NULL) { 1415 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1416 pool->base.hubps[i] = NULL; 1417 } 1418 1419 if (pool->base.irqs != NULL) { 1420 dal_irq_service_destroy(&pool->base.irqs); 1421 } 1422 } 1423 1424 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1425 if (pool->base.engines[i] != NULL) 1426 dce110_engine_destroy(&pool->base.engines[i]); 1427 if (pool->base.hw_i2cs[i] != NULL) { 1428 kfree(pool->base.hw_i2cs[i]); 1429 pool->base.hw_i2cs[i] = NULL; 1430 } 1431 if (pool->base.sw_i2cs[i] != NULL) { 1432 kfree(pool->base.sw_i2cs[i]); 1433 pool->base.sw_i2cs[i] = NULL; 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1438 if (pool->base.opps[i] != NULL) 1439 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1440 } 1441 1442 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1443 if (pool->base.timing_generators[i] != NULL) { 1444 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1445 pool->base.timing_generators[i] = NULL; 1446 } 1447 } 1448 1449 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1450 if (pool->base.dwbc[i] != NULL) { 1451 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1452 pool->base.dwbc[i] = NULL; 1453 } 1454 if (pool->base.mcif_wb[i] != NULL) { 1455 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1456 pool->base.mcif_wb[i] = NULL; 1457 } 1458 } 1459 1460 for (i = 0; i < pool->base.audio_count; i++) { 1461 if (pool->base.audios[i]) 1462 dce_aud_destroy(&pool->base.audios[i]); 1463 } 1464 1465 for (i = 0; i < pool->base.clk_src_count; i++) { 1466 if (pool->base.clock_sources[i] != NULL) { 1467 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1468 pool->base.clock_sources[i] = NULL; 1469 } 1470 } 1471 1472 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1473 if (pool->base.mpc_lut[i] != NULL) { 1474 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1475 pool->base.mpc_lut[i] = NULL; 1476 } 1477 if (pool->base.mpc_shaper[i] != NULL) { 1478 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1479 pool->base.mpc_shaper[i] = NULL; 1480 } 1481 } 1482 1483 if (pool->base.dp_clock_source != NULL) { 1484 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1485 pool->base.dp_clock_source = NULL; 1486 } 1487 1488 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1489 if (pool->base.multiple_abms[i] != NULL) 1490 dce_abm_destroy(&pool->base.multiple_abms[i]); 1491 } 1492 1493 if (pool->base.psr != NULL) 1494 dmub_psr_destroy(&pool->base.psr); 1495 1496 if (pool->base.dccg != NULL) 1497 dcn_dccg_destroy(&pool->base.dccg); 1498 1499 if (pool->base.oem_device != NULL) 1500 dal_ddc_service_destroy(&pool->base.oem_device); 1501 } 1502 1503 1504 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1505 { 1506 int i; 1507 uint32_t dwb_count = pool->res_cap->num_dwb; 1508 1509 for (i = 0; i < dwb_count; i++) { 1510 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1511 GFP_KERNEL); 1512 1513 if (!dwbc30) { 1514 dm_error("DC: failed to create dwbc30!\n"); 1515 return false; 1516 } 1517 1518 dcn30_dwbc_construct(dwbc30, ctx, 1519 &dwbc30_regs[i], 1520 &dwbc30_shift, 1521 &dwbc30_mask, 1522 i); 1523 1524 pool->dwbc[i] = &dwbc30->base; 1525 } 1526 return true; 1527 } 1528 1529 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1530 { 1531 int i; 1532 uint32_t dwb_count = pool->res_cap->num_dwb; 1533 1534 for (i = 0; i < dwb_count; i++) { 1535 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1536 GFP_KERNEL); 1537 1538 if (!mcif_wb30) { 1539 dm_error("DC: failed to create mcif_wb30!\n"); 1540 return false; 1541 } 1542 1543 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1544 &mcif_wb30_regs[i], 1545 &mcif_wb30_shift, 1546 &mcif_wb30_mask, 1547 i); 1548 1549 pool->mcif_wb[i] = &mcif_wb30->base; 1550 } 1551 return true; 1552 } 1553 1554 static struct display_stream_compressor *dcn32_dsc_create( 1555 struct dc_context *ctx, uint32_t inst) 1556 { 1557 struct dcn20_dsc *dsc = 1558 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1559 1560 if (!dsc) { 1561 BREAK_TO_DEBUGGER(); 1562 return NULL; 1563 } 1564 1565 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1566 1567 dsc->max_image_width = 6016; 1568 1569 return &dsc->base; 1570 } 1571 1572 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1573 { 1574 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1575 1576 dcn32_resource_destruct(dcn32_pool); 1577 kfree(dcn32_pool); 1578 *pool = NULL; 1579 } 1580 1581 bool dcn32_acquire_post_bldn_3dlut( 1582 struct resource_context *res_ctx, 1583 const struct resource_pool *pool, 1584 int mpcc_id, 1585 struct dc_3dlut **lut, 1586 struct dc_transfer_func **shaper) 1587 { 1588 bool ret = false; 1589 union dc_3dlut_state *state; 1590 1591 ASSERT(*lut == NULL && *shaper == NULL); 1592 *lut = NULL; 1593 *shaper = NULL; 1594 1595 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1596 *lut = pool->mpc_lut[mpcc_id]; 1597 *shaper = pool->mpc_shaper[mpcc_id]; 1598 state = &pool->mpc_lut[mpcc_id]->state; 1599 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1600 ret = true; 1601 } 1602 return ret; 1603 } 1604 1605 bool dcn32_release_post_bldn_3dlut( 1606 struct resource_context *res_ctx, 1607 const struct resource_pool *pool, 1608 struct dc_3dlut **lut, 1609 struct dc_transfer_func **shaper) 1610 { 1611 int i; 1612 bool ret = false; 1613 1614 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1615 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1616 res_ctx->is_mpc_3dlut_acquired[i] = false; 1617 pool->mpc_lut[i]->state.raw = 0; 1618 *lut = NULL; 1619 *shaper = NULL; 1620 ret = true; 1621 break; 1622 } 1623 } 1624 return ret; 1625 } 1626 1627 static void dcn32_enable_phantom_plane(struct dc *dc, 1628 struct dc_state *context, 1629 struct dc_stream_state *phantom_stream, 1630 unsigned int dc_pipe_idx) 1631 { 1632 struct dc_plane_state *phantom_plane = NULL; 1633 struct dc_plane_state *prev_phantom_plane = NULL; 1634 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1635 1636 while (curr_pipe) { 1637 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1638 phantom_plane = prev_phantom_plane; 1639 else 1640 phantom_plane = dc_create_plane_state(dc); 1641 1642 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1643 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1644 sizeof(phantom_plane->scaling_quality)); 1645 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1646 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1647 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1648 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1649 sizeof(phantom_plane->plane_size)); 1650 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1651 sizeof(phantom_plane->tiling_info)); 1652 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1653 phantom_plane->format = curr_pipe->plane_state->format; 1654 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1655 phantom_plane->visible = curr_pipe->plane_state->visible; 1656 1657 /* Shadow pipe has small viewport. */ 1658 phantom_plane->clip_rect.y = 0; 1659 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; 1660 1661 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1662 1663 curr_pipe = curr_pipe->bottom_pipe; 1664 prev_phantom_plane = phantom_plane; 1665 } 1666 } 1667 1668 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1669 struct dc_state *context, 1670 display_e2e_pipe_params_st *pipes, 1671 unsigned int pipe_cnt, 1672 unsigned int dc_pipe_idx) 1673 { 1674 struct dc_stream_state *phantom_stream = NULL; 1675 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1676 1677 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1678 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1679 phantom_stream->dpms_off = true; 1680 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1681 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1682 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1683 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1684 1685 /* stream has limited viewport and small timing */ 1686 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1687 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1688 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1689 DC_FP_START(); 1690 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1691 DC_FP_END(); 1692 1693 dc_add_stream_to_ctx(dc, context, phantom_stream); 1694 return phantom_stream; 1695 } 1696 1697 // return true if removed piped from ctx, false otherwise 1698 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) 1699 { 1700 int i; 1701 bool removed_pipe = false; 1702 1703 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1704 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1705 // build scaling params for phantom pipes 1706 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1707 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1708 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1709 removed_pipe = true; 1710 } 1711 1712 // Clear all phantom stream info 1713 if (pipe->stream) { 1714 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1715 pipe->stream->mall_stream_config.paired_stream = NULL; 1716 } 1717 } 1718 return removed_pipe; 1719 } 1720 1721 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1722 * require a phantom pipe / stream 1723 */ 1724 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1725 display_e2e_pipe_params_st *pipes, 1726 unsigned int pipe_cnt, 1727 unsigned int index) 1728 { 1729 struct dc_stream_state *phantom_stream = NULL; 1730 unsigned int i; 1731 1732 // The index of the DC pipe passed into this function is guarenteed to 1733 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1734 // already have phantom pipe assigned, etc.) by previous checks. 1735 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1736 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1737 1738 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1739 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1740 1741 // Build scaling params for phantom pipes which were newly added. 1742 // We determine which phantom pipes were added by comparing with 1743 // the phantom stream. 1744 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1745 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1746 pipe->stream->use_dynamic_meta = false; 1747 pipe->plane_state->flip_immediate = false; 1748 if (!resource_build_scaling_params(pipe)) { 1749 // Log / remove phantom pipes since failed to build scaling params 1750 } 1751 } 1752 } 1753 } 1754 1755 bool dcn32_validate_bandwidth(struct dc *dc, 1756 struct dc_state *context, 1757 bool fast_validate) 1758 { 1759 bool out = false; 1760 1761 BW_VAL_TRACE_SETUP(); 1762 1763 int vlevel = 0; 1764 int pipe_cnt = 0; 1765 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1766 DC_LOGGER_INIT(dc->ctx->logger); 1767 1768 BW_VAL_TRACE_COUNT(); 1769 1770 DC_FP_START(); 1771 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1772 DC_FP_END(); 1773 1774 if (pipe_cnt == 0) 1775 goto validate_out; 1776 1777 if (!out) 1778 goto validate_fail; 1779 1780 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1781 1782 if (fast_validate) { 1783 BW_VAL_TRACE_SKIP(fast); 1784 goto validate_out; 1785 } 1786 1787 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1788 1789 BW_VAL_TRACE_END_WATERMARKS(); 1790 1791 goto validate_out; 1792 1793 validate_fail: 1794 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1795 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1796 1797 BW_VAL_TRACE_SKIP(fail); 1798 out = false; 1799 1800 validate_out: 1801 kfree(pipes); 1802 1803 BW_VAL_TRACE_FINISH(); 1804 1805 return out; 1806 } 1807 1808 1809 static bool is_dual_plane(enum surface_pixel_format format) 1810 { 1811 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1812 } 1813 1814 int dcn32_populate_dml_pipes_from_context( 1815 struct dc *dc, struct dc_state *context, 1816 display_e2e_pipe_params_st *pipes, 1817 bool fast_validate) 1818 { 1819 int i, pipe_cnt; 1820 struct resource_context *res_ctx = &context->res_ctx; 1821 struct pipe_ctx *pipe; 1822 bool subvp_in_use = false, is_pipe_split_expected[MAX_PIPES]; 1823 1824 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1825 1826 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1827 struct dc_crtc_timing *timing; 1828 1829 if (!res_ctx->pipe_ctx[i].stream) 1830 continue; 1831 pipe = &res_ctx->pipe_ctx[i]; 1832 timing = &pipe->stream->timing; 1833 1834 pipes[pipe_cnt].pipe.src.gpuvm = true; 1835 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1836 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1837 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1838 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1839 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1840 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1841 1842 switch (pipe->stream->mall_stream_config.type) { 1843 case SUBVP_MAIN: 1844 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1845 subvp_in_use = true; 1846 break; 1847 case SUBVP_PHANTOM: 1848 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1849 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1850 // Disallow unbounded req for SubVP according to DCHUB programming guide 1851 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1852 break; 1853 case SUBVP_NONE: 1854 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1855 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1856 break; 1857 default: 1858 break; 1859 } 1860 1861 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1862 if (pipes[pipe_cnt].dout.dsc_enable) { 1863 switch (timing->display_color_depth) { 1864 case COLOR_DEPTH_888: 1865 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1866 break; 1867 case COLOR_DEPTH_101010: 1868 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1869 break; 1870 case COLOR_DEPTH_121212: 1871 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1872 break; 1873 default: 1874 ASSERT(0); 1875 break; 1876 } 1877 } 1878 1879 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1880 if (context->stream_count == 1) { 1881 if (dc->debug.enable_single_display_2to1_odm_policy) 1882 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1883 } 1884 1885 DC_FP_START(); 1886 is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, pipes[i].pipe, i); 1887 DC_FP_END(); 1888 1889 pipe_cnt++; 1890 } 1891 1892 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 1893 * the DET available for each pipe). Use the DET override input to maintain our driver 1894 * policy. 1895 */ 1896 if (pipe_cnt == 1 && !is_pipe_split_expected[0]) { 1897 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; 1898 if (pipe->plane_state && !dc->debug.disable_z9_mpc) { 1899 if (!is_dual_plane(pipe->plane_state->format)) { 1900 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; 1901 pipes[0].pipe.src.unbounded_req_mode = true; 1902 if (pipe->plane_state->src_rect.width >= 5120 && 1903 pipe->plane_state->src_rect.height >= 2880) 1904 pipes[0].pipe.src.det_size_override = 320; // 5K or higher 1905 } 1906 } 1907 } else 1908 dcn32_determine_det_override(context, pipes, is_pipe_split_expected, dc->res_pool->pipe_count); 1909 1910 // In general cases we want to keep the dram clock change requirement 1911 // (prefer configs that support MCLK switch). Only override to false 1912 // for SubVP 1913 if (subvp_in_use) 1914 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 1915 else 1916 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1917 1918 return pipe_cnt; 1919 } 1920 1921 static struct dc_cap_funcs cap_funcs = { 1922 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1923 }; 1924 1925 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 1926 display_e2e_pipe_params_st *pipes, 1927 int pipe_cnt, 1928 int vlevel) 1929 { 1930 DC_FP_START(); 1931 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 1932 DC_FP_END(); 1933 } 1934 1935 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1936 { 1937 DC_FP_START(); 1938 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 1939 DC_FP_END(); 1940 } 1941 1942 static struct resource_funcs dcn32_res_pool_funcs = { 1943 .destroy = dcn32_destroy_resource_pool, 1944 .link_enc_create = dcn32_link_encoder_create, 1945 .link_enc_create_minimal = NULL, 1946 .panel_cntl_create = dcn32_panel_cntl_create, 1947 .validate_bandwidth = dcn32_validate_bandwidth, 1948 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 1949 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 1950 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1951 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1952 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1953 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1954 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1955 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1956 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1957 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1958 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1959 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 1960 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1961 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1962 .add_phantom_pipes = dcn32_add_phantom_pipes, 1963 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 1964 }; 1965 1966 1967 static bool dcn32_resource_construct( 1968 uint8_t num_virtual_links, 1969 struct dc *dc, 1970 struct dcn32_resource_pool *pool) 1971 { 1972 int i, j; 1973 struct dc_context *ctx = dc->ctx; 1974 struct irq_service_init_data init_data; 1975 struct ddc_service_init_data ddc_init_data = {0}; 1976 uint32_t pipe_fuses = 0; 1977 uint32_t num_pipes = 4; 1978 1979 DC_FP_START(); 1980 1981 ctx->dc_bios->regs = &bios_regs; 1982 1983 pool->base.res_cap = &res_cap_dcn32; 1984 /* max number of pipes for ASIC before checking for pipe fuses */ 1985 num_pipes = pool->base.res_cap->num_timing_generator; 1986 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1987 1988 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1989 if (pipe_fuses & 1 << i) 1990 num_pipes--; 1991 1992 if (pipe_fuses & 1) 1993 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 1994 1995 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1996 ASSERT(0); //Entire DCN is harvested! 1997 1998 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 1999 * value will be changed, update max_num_dpp and max_num_otg for dml. 2000 */ 2001 dcn3_2_ip.max_num_dpp = num_pipes; 2002 dcn3_2_ip.max_num_otg = num_pipes; 2003 2004 pool->base.funcs = &dcn32_res_pool_funcs; 2005 2006 /************************************************* 2007 * Resource + asic cap harcoding * 2008 *************************************************/ 2009 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2010 pool->base.timing_generator_count = num_pipes; 2011 pool->base.pipe_count = num_pipes; 2012 pool->base.mpcc_count = num_pipes; 2013 dc->caps.max_downscale_ratio = 600; 2014 dc->caps.i2c_speed_in_khz = 100; 2015 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2016 dc->caps.max_cursor_size = 256; 2017 dc->caps.min_horizontal_blanking_period = 80; 2018 dc->caps.dmdata_alloc_size = 2048; 2019 dc->caps.mall_size_per_mem_channel = 0; 2020 dc->caps.mall_size_total = 0; 2021 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2022 2023 dc->caps.cache_line_size = 64; 2024 dc->caps.cache_num_ways = 16; 2025 dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64 2026 dc->caps.subvp_fw_processing_delay_us = 15; 2027 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2028 dc->caps.subvp_pstate_allow_width_us = 20; 2029 dc->caps.subvp_vertical_int_margin_us = 30; 2030 2031 dc->caps.max_slave_planes = 2; 2032 dc->caps.max_slave_yuv_planes = 2; 2033 dc->caps.max_slave_rgb_planes = 2; 2034 dc->caps.post_blend_color_processing = true; 2035 dc->caps.force_dp_tps4_for_cp2520 = true; 2036 dc->caps.dp_hpo = true; 2037 dc->caps.dp_hdmi21_pcon_support = true; 2038 dc->caps.edp_dsc_support = true; 2039 dc->caps.extended_aux_timeout_support = true; 2040 dc->caps.dmcub_support = true; 2041 2042 /* Color pipeline capabilities */ 2043 dc->caps.color.dpp.dcn_arch = 1; 2044 dc->caps.color.dpp.input_lut_shared = 0; 2045 dc->caps.color.dpp.icsc = 1; 2046 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2047 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2048 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2049 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2050 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2051 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2052 dc->caps.color.dpp.post_csc = 1; 2053 dc->caps.color.dpp.gamma_corr = 1; 2054 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2055 2056 dc->caps.color.dpp.hw_3d_lut = 1; 2057 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2058 // no OGAM ROM on DCN2 and later ASICs 2059 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2060 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2061 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2062 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2063 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2064 dc->caps.color.dpp.ocsc = 0; 2065 2066 dc->caps.color.mpc.gamut_remap = 1; 2067 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2068 dc->caps.color.mpc.ogam_ram = 1; 2069 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2070 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2071 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2072 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2073 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2074 dc->caps.color.mpc.ocsc = 1; 2075 2076 /* Use pipe context based otg sync logic */ 2077 dc->config.use_pipe_ctx_sync_logic = true; 2078 2079 /* read VBIOS LTTPR caps */ 2080 { 2081 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2082 enum bp_result bp_query_result; 2083 uint8_t is_vbios_lttpr_enable = 0; 2084 2085 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2086 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2087 } 2088 2089 /* interop bit is implicit */ 2090 { 2091 dc->caps.vbios_lttpr_aware = true; 2092 } 2093 } 2094 2095 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2096 dc->debug = debug_defaults_drv; 2097 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2098 dc->debug = debug_defaults_diags; 2099 } else 2100 dc->debug = debug_defaults_diags; 2101 // Init the vm_helper 2102 if (dc->vm_helper) 2103 vm_helper_init(dc->vm_helper, 16); 2104 2105 /************************************************* 2106 * Create resources * 2107 *************************************************/ 2108 2109 /* Clock Sources for Pixel Clock*/ 2110 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2111 dcn32_clock_source_create(ctx, ctx->dc_bios, 2112 CLOCK_SOURCE_COMBO_PHY_PLL0, 2113 &clk_src_regs[0], false); 2114 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2115 dcn32_clock_source_create(ctx, ctx->dc_bios, 2116 CLOCK_SOURCE_COMBO_PHY_PLL1, 2117 &clk_src_regs[1], false); 2118 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2119 dcn32_clock_source_create(ctx, ctx->dc_bios, 2120 CLOCK_SOURCE_COMBO_PHY_PLL2, 2121 &clk_src_regs[2], false); 2122 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2123 dcn32_clock_source_create(ctx, ctx->dc_bios, 2124 CLOCK_SOURCE_COMBO_PHY_PLL3, 2125 &clk_src_regs[3], false); 2126 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2127 dcn32_clock_source_create(ctx, ctx->dc_bios, 2128 CLOCK_SOURCE_COMBO_PHY_PLL4, 2129 &clk_src_regs[4], false); 2130 2131 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2132 2133 /* todo: not reuse phy_pll registers */ 2134 pool->base.dp_clock_source = 2135 dcn32_clock_source_create(ctx, ctx->dc_bios, 2136 CLOCK_SOURCE_ID_DP_DTO, 2137 &clk_src_regs[0], true); 2138 2139 for (i = 0; i < pool->base.clk_src_count; i++) { 2140 if (pool->base.clock_sources[i] == NULL) { 2141 dm_error("DC: failed to create clock sources!\n"); 2142 BREAK_TO_DEBUGGER(); 2143 goto create_fail; 2144 } 2145 } 2146 2147 /* DCCG */ 2148 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2149 if (pool->base.dccg == NULL) { 2150 dm_error("DC: failed to create dccg!\n"); 2151 BREAK_TO_DEBUGGER(); 2152 goto create_fail; 2153 } 2154 2155 /* DML */ 2156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2157 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2158 2159 /* IRQ Service */ 2160 init_data.ctx = dc->ctx; 2161 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2162 if (!pool->base.irqs) 2163 goto create_fail; 2164 2165 /* HUBBUB */ 2166 pool->base.hubbub = dcn32_hubbub_create(ctx); 2167 if (pool->base.hubbub == NULL) { 2168 BREAK_TO_DEBUGGER(); 2169 dm_error("DC: failed to create hubbub!\n"); 2170 goto create_fail; 2171 } 2172 2173 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2174 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2175 2176 /* if pipe is disabled, skip instance of HW pipe, 2177 * i.e, skip ASIC register instance 2178 */ 2179 if (pipe_fuses & 1 << i) 2180 continue; 2181 2182 /* HUBPs */ 2183 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2184 if (pool->base.hubps[j] == NULL) { 2185 BREAK_TO_DEBUGGER(); 2186 dm_error( 2187 "DC: failed to create hubps!\n"); 2188 goto create_fail; 2189 } 2190 2191 /* DPPs */ 2192 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2193 if (pool->base.dpps[j] == NULL) { 2194 BREAK_TO_DEBUGGER(); 2195 dm_error( 2196 "DC: failed to create dpps!\n"); 2197 goto create_fail; 2198 } 2199 2200 /* OPPs */ 2201 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2202 if (pool->base.opps[j] == NULL) { 2203 BREAK_TO_DEBUGGER(); 2204 dm_error( 2205 "DC: failed to create output pixel processor!\n"); 2206 goto create_fail; 2207 } 2208 2209 /* TGs */ 2210 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2211 ctx, i); 2212 if (pool->base.timing_generators[j] == NULL) { 2213 BREAK_TO_DEBUGGER(); 2214 dm_error("DC: failed to create tg!\n"); 2215 goto create_fail; 2216 } 2217 2218 /* ABMs */ 2219 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2220 &abm_regs[i], 2221 &abm_shift, 2222 &abm_mask); 2223 if (pool->base.multiple_abms[j] == NULL) { 2224 dm_error("DC: failed to create abm for pipe %d!\n", i); 2225 BREAK_TO_DEBUGGER(); 2226 goto create_fail; 2227 } 2228 2229 /* index for resource pool arrays for next valid pipe */ 2230 j++; 2231 } 2232 2233 /* PSR */ 2234 pool->base.psr = dmub_psr_create(ctx); 2235 if (pool->base.psr == NULL) { 2236 dm_error("DC: failed to create psr obj!\n"); 2237 BREAK_TO_DEBUGGER(); 2238 goto create_fail; 2239 } 2240 2241 /* MPCCs */ 2242 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2243 if (pool->base.mpc == NULL) { 2244 BREAK_TO_DEBUGGER(); 2245 dm_error("DC: failed to create mpc!\n"); 2246 goto create_fail; 2247 } 2248 2249 /* DSCs */ 2250 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2251 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2252 if (pool->base.dscs[i] == NULL) { 2253 BREAK_TO_DEBUGGER(); 2254 dm_error("DC: failed to create display stream compressor %d!\n", i); 2255 goto create_fail; 2256 } 2257 } 2258 2259 /* DWB */ 2260 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2261 BREAK_TO_DEBUGGER(); 2262 dm_error("DC: failed to create dwbc!\n"); 2263 goto create_fail; 2264 } 2265 2266 /* MMHUBBUB */ 2267 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2268 BREAK_TO_DEBUGGER(); 2269 dm_error("DC: failed to create mcif_wb!\n"); 2270 goto create_fail; 2271 } 2272 2273 /* AUX and I2C */ 2274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2275 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2276 if (pool->base.engines[i] == NULL) { 2277 BREAK_TO_DEBUGGER(); 2278 dm_error( 2279 "DC:failed to create aux engine!!\n"); 2280 goto create_fail; 2281 } 2282 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2283 if (pool->base.hw_i2cs[i] == NULL) { 2284 BREAK_TO_DEBUGGER(); 2285 dm_error( 2286 "DC:failed to create hw i2c!!\n"); 2287 goto create_fail; 2288 } 2289 pool->base.sw_i2cs[i] = NULL; 2290 } 2291 2292 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2293 if (!resource_construct(num_virtual_links, dc, &pool->base, 2294 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2295 &res_create_funcs : &res_create_maximus_funcs))) 2296 goto create_fail; 2297 2298 /* HW Sequencer init functions and Plane caps */ 2299 dcn32_hw_sequencer_init_functions(dc); 2300 2301 dc->caps.max_planes = pool->base.pipe_count; 2302 2303 for (i = 0; i < dc->caps.max_planes; ++i) 2304 dc->caps.planes[i] = plane_cap; 2305 2306 dc->cap_funcs = cap_funcs; 2307 2308 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2309 ddc_init_data.ctx = dc->ctx; 2310 ddc_init_data.link = NULL; 2311 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2312 ddc_init_data.id.enum_id = 0; 2313 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2314 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2315 } else { 2316 pool->base.oem_device = NULL; 2317 } 2318 2319 DC_FP_END(); 2320 2321 return true; 2322 2323 create_fail: 2324 2325 DC_FP_END(); 2326 2327 dcn32_resource_destruct(pool); 2328 2329 return false; 2330 } 2331 2332 struct resource_pool *dcn32_create_resource_pool( 2333 const struct dc_init_data *init_data, 2334 struct dc *dc) 2335 { 2336 struct dcn32_resource_pool *pool = 2337 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2338 2339 if (!pool) 2340 return NULL; 2341 2342 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2343 return &pool->base; 2344 2345 BREAK_TO_DEBUGGER(); 2346 kfree(pool); 2347 return NULL; 2348 } 2349