1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn32_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn32_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn32/dcn32_hubbub.h" 43 #include "dcn32/dcn32_mpc.h" 44 #include "dcn32_hubp.h" 45 #include "irq/dcn32/irq_service_dcn32.h" 46 #include "dcn32/dcn32_dpp.h" 47 #include "dcn32/dcn32_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn32/dcn32_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 60 #include "dcn31/dcn31_apg.h" 61 #include "dcn31/dcn31_dio_link_encoder.h" 62 #include "dcn32/dcn32_dio_link_encoder.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn32/dcn32_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "link.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn32/dcn32_mmhubbub.h" 76 77 #include "dcn/dcn_3_2_0_offset.h" 78 #include "dcn/dcn_3_2_0_sh_mask.h" 79 #include "nbio/nbio_4_3_0_offset.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/display_mode_vba_30.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dml/dcn32/dcn32_fpu.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 enum dcn32_clk_src_array_id { 95 DCN32_CLK_SRC_PLL0, 96 DCN32_CLK_SRC_PLL1, 97 DCN32_CLK_SRC_PLL2, 98 DCN32_CLK_SRC_PLL3, 99 DCN32_CLK_SRC_PLL4, 100 DCN32_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 109 110 #define BASE(seg) BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 114 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 117 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name = value 120 121 #define SRI(reg_name, block, id)\ 122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 reg ## block ## id ## _ ## reg_name 124 125 #define SRI_ARR(reg_name, block, id)\ 126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 127 reg ## block ## id ## _ ## reg_name 128 129 #define SR_ARR_I2C(reg_name, id) \ 130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 131 132 #define SRI_ARR_I2C(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 138 reg ## block ## id ## _ ## reg_name 139 140 #define SRI2(reg_name, block, id)\ 141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 142 reg ## reg_name 143 #define SRI2_ARR(reg_name, block, id)\ 144 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRIR(var_name, reg_name, block, id)\ 148 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRII(reg_name, block, id)\ 152 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 153 reg ## block ## id ## _ ## reg_name 154 155 #define SRII_ARR_2(reg_name, block, id, inst)\ 156 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII_MPC_RMU(reg_name, block, id)\ 160 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_DWB(reg_name, temp_name, block, id)\ 164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## temp_name 166 167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define DCCG_SRII(reg_name, block, id)\ 171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define VUPDATE_SRII(reg_name, block, id)\ 175 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 176 reg ## reg_name ## _ ## block ## id 177 178 /* NBIO */ 179 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 180 181 #define NBIO_BASE(seg) \ 182 NBIO_BASE_INNER(seg) 183 184 #define NBIO_SR(reg_name)\ 185 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 186 regBIF_BX0_ ## reg_name 187 #define NBIO_SR_ARR(reg_name, id)\ 188 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 189 regBIF_BX0_ ## reg_name 190 191 #undef CTX 192 #define CTX ctx 193 #define REG(reg_name) \ 194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 195 196 static struct bios_registers bios_regs; 197 198 #define bios_regs_init() \ 199 ( \ 200 NBIO_SR(BIOS_SCRATCH_3),\ 201 NBIO_SR(BIOS_SCRATCH_6)\ 202 ) 203 204 #define clk_src_regs_init(index, pllid)\ 205 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 206 207 static struct dce110_clk_src_regs clk_src_regs[5]; 208 209 static const struct dce110_clk_src_shift cs_shift = { 210 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 211 }; 212 213 static const struct dce110_clk_src_mask cs_mask = { 214 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 215 }; 216 217 #define abm_regs_init(id)\ 218 ABM_DCN32_REG_LIST_RI(id) 219 220 static struct dce_abm_registers abm_regs[4]; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN32(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN32(_MASK) 228 }; 229 230 #define audio_regs_init(id)\ 231 AUD_COMMON_REG_LIST_RI(id) 232 233 static struct dce_audio_registers audio_regs[5]; 234 235 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 237 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 238 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 239 240 static const struct dce_audio_shift audio_shift = { 241 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dce_audio_mask audio_mask = { 245 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 246 }; 247 248 #define vpg_regs_init(id)\ 249 VPG_DCN3_REG_LIST_RI(id) 250 251 static struct dcn30_vpg_registers vpg_regs[10]; 252 253 static const struct dcn30_vpg_shift vpg_shift = { 254 DCN3_VPG_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dcn30_vpg_mask vpg_mask = { 258 DCN3_VPG_MASK_SH_LIST(_MASK) 259 }; 260 261 #define afmt_regs_init(id)\ 262 AFMT_DCN3_REG_LIST_RI(id) 263 264 static struct dcn30_afmt_registers afmt_regs[6]; 265 266 static const struct dcn30_afmt_shift afmt_shift = { 267 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dcn30_afmt_mask afmt_mask = { 271 DCN3_AFMT_MASK_SH_LIST(_MASK) 272 }; 273 274 #define apg_regs_init(id)\ 275 APG_DCN31_REG_LIST_RI(id) 276 277 static struct dcn31_apg_registers apg_regs[4]; 278 279 static const struct dcn31_apg_shift apg_shift = { 280 DCN31_APG_MASK_SH_LIST(__SHIFT) 281 }; 282 283 static const struct dcn31_apg_mask apg_mask = { 284 DCN31_APG_MASK_SH_LIST(_MASK) 285 }; 286 287 #define stream_enc_regs_init(id)\ 288 SE_DCN32_REG_LIST_RI(id) 289 290 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 291 292 static const struct dcn10_stream_encoder_shift se_shift = { 293 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 294 }; 295 296 static const struct dcn10_stream_encoder_mask se_mask = { 297 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 298 }; 299 300 301 #define aux_regs_init(id)\ 302 DCN2_AUX_REG_LIST_RI(id) 303 304 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 305 306 #define hpd_regs_init(id)\ 307 HPD_REG_LIST_RI(id) 308 309 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 310 311 #define link_regs_init(id, phyid)\ 312 ( \ 313 LE_DCN31_REG_LIST_RI(id), \ 314 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 315 ) 316 /*DPCS_DCN31_REG_LIST(id),*/ \ 317 318 static struct dcn10_link_enc_registers link_enc_regs[5]; 319 320 static const struct dcn10_link_enc_shift le_shift = { 321 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 322 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn10_link_enc_mask le_mask = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 328 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 }; 330 331 #define hpo_dp_stream_encoder_reg_init(id)\ 332 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 333 334 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 335 336 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 337 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 342 }; 343 344 345 #define hpo_dp_link_encoder_reg_init(id)\ 346 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 347 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 348 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 351 352 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 353 354 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 355 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 360 }; 361 362 #define dpp_regs_init(id)\ 363 DPP_REG_LIST_DCN30_COMMON_RI(id) 364 365 static struct dcn3_dpp_registers dpp_regs[4]; 366 367 static const struct dcn3_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 369 }; 370 371 static const struct dcn3_dpp_mask tf_mask = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 373 }; 374 375 376 #define opp_regs_init(id)\ 377 OPP_REG_LIST_DCN30_RI(id) 378 379 static struct dcn20_opp_registers opp_regs[4]; 380 381 static const struct dcn20_opp_shift opp_shift = { 382 OPP_MASK_SH_LIST_DCN20(__SHIFT) 383 }; 384 385 static const struct dcn20_opp_mask opp_mask = { 386 OPP_MASK_SH_LIST_DCN20(_MASK) 387 }; 388 389 #define aux_engine_regs_init(id)\ 390 ( \ 391 AUX_COMMON_REG_LIST0_RI(id), \ 392 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 396 ) 397 398 static struct dce110_aux_registers aux_engine_regs[5]; 399 400 static const struct dce110_aux_registers_shift aux_shift = { 401 DCN_AUX_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce110_aux_registers_mask aux_mask = { 405 DCN_AUX_MASK_SH_LIST(_MASK) 406 }; 407 408 #define dwbc_regs_dcn3_init(id)\ 409 DWBC_COMMON_REG_LIST_DCN30_RI(id) 410 411 static struct dcn30_dwbc_registers dwbc30_regs[1]; 412 413 static const struct dcn30_dwbc_shift dwbc30_shift = { 414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 415 }; 416 417 static const struct dcn30_dwbc_mask dwbc30_mask = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 419 }; 420 421 #define mcif_wb_regs_dcn3_init(id)\ 422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 423 424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 425 426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 428 }; 429 430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 432 }; 433 434 #define dsc_regsDCN20_init(id)\ 435 DSC_REG_LIST_DCN20_RI(id) 436 437 static struct dcn20_dsc_registers dsc_regs[4]; 438 439 static const struct dcn20_dsc_shift dsc_shift = { 440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 441 }; 442 443 static const struct dcn20_dsc_mask dsc_mask = { 444 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 445 }; 446 447 static struct dcn30_mpc_registers mpc_regs; 448 449 #define dcn_mpc_regs_init() \ 450 MPC_REG_LIST_DCN3_2_RI(0),\ 451 MPC_REG_LIST_DCN3_2_RI(1),\ 452 MPC_REG_LIST_DCN3_2_RI(2),\ 453 MPC_REG_LIST_DCN3_2_RI(3),\ 454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 458 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 459 460 static const struct dcn30_mpc_shift mpc_shift = { 461 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 462 }; 463 464 static const struct dcn30_mpc_mask mpc_mask = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 466 }; 467 468 #define optc_regs_init(id)\ 469 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 470 471 static struct dcn_optc_registers optc_regs[4]; 472 473 static const struct dcn_optc_shift optc_shift = { 474 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 475 }; 476 477 static const struct dcn_optc_mask optc_mask = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 479 }; 480 481 #define hubp_regs_init(id)\ 482 HUBP_REG_LIST_DCN32_RI(id) 483 484 static struct dcn_hubp2_registers hubp_regs[4]; 485 486 487 static const struct dcn_hubp2_shift hubp_shift = { 488 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 489 }; 490 491 static const struct dcn_hubp2_mask hubp_mask = { 492 HUBP_MASK_SH_LIST_DCN32(_MASK) 493 }; 494 495 static struct dcn_hubbub_registers hubbub_reg; 496 #define hubbub_reg_init()\ 497 HUBBUB_REG_LIST_DCN32_RI(0) 498 499 static const struct dcn_hubbub_shift hubbub_shift = { 500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 501 }; 502 503 static const struct dcn_hubbub_mask hubbub_mask = { 504 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 505 }; 506 507 static struct dccg_registers dccg_regs; 508 509 #define dccg_regs_init()\ 510 DCCG_REG_LIST_DCN32_RI() 511 512 static const struct dccg_shift dccg_shift = { 513 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 514 }; 515 516 static const struct dccg_mask dccg_mask = { 517 DCCG_MASK_SH_LIST_DCN32(_MASK) 518 }; 519 520 521 #define SRII2(reg_name_pre, reg_name_post, id)\ 522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 524 reg ## reg_name_pre ## id ## _ ## reg_name_post 525 526 527 #define HWSEQ_DCN32_REG_LIST()\ 528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 529 SR(DIO_MEM_PWR_CTRL), \ 530 SR(ODM_MEM_PWR_CTRL3), \ 531 SR(MMHUBBUB_MEM_PWR_CNTL), \ 532 SR(DCCG_GATE_DISABLE_CNTL), \ 533 SR(DCCG_GATE_DISABLE_CNTL2), \ 534 SR(DCFCLK_CNTL),\ 535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 536 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 537 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 538 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 539 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 544 SR(MICROSECOND_TIME_BASE_DIV), \ 545 SR(MILLISECOND_TIME_BASE_DIV), \ 546 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 547 SR(RBBMIF_TIMEOUT_DIS), \ 548 SR(RBBMIF_TIMEOUT_DIS_2), \ 549 SR(DCHUBBUB_CRC_CTRL), \ 550 SR(DPP_TOP0_DPP_CRC_CTRL), \ 551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 553 SR(MPC_CRC_CTRL), \ 554 SR(MPC_CRC_RESULT_GB), \ 555 SR(MPC_CRC_RESULT_C), \ 556 SR(MPC_CRC_RESULT_AR), \ 557 SR(DOMAIN0_PG_CONFIG), \ 558 SR(DOMAIN1_PG_CONFIG), \ 559 SR(DOMAIN2_PG_CONFIG), \ 560 SR(DOMAIN3_PG_CONFIG), \ 561 SR(DOMAIN16_PG_CONFIG), \ 562 SR(DOMAIN17_PG_CONFIG), \ 563 SR(DOMAIN18_PG_CONFIG), \ 564 SR(DOMAIN19_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN19_PG_STATUS), \ 573 SR(D1VGA_CONTROL), \ 574 SR(D2VGA_CONTROL), \ 575 SR(D3VGA_CONTROL), \ 576 SR(D4VGA_CONTROL), \ 577 SR(D5VGA_CONTROL), \ 578 SR(D6VGA_CONTROL), \ 579 SR(DC_IP_REQUEST_CNTL), \ 580 SR(AZALIA_AUDIO_DTO), \ 581 SR(AZALIA_CONTROLLER_CLOCK_GATING) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init()\ 586 HWSEQ_DCN32_REG_LIST() 587 588 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 621 622 static const struct dce_hwseq_shift hwseq_shift = { 623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 624 }; 625 626 static const struct dce_hwseq_mask hwseq_mask = { 627 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 628 }; 629 #define vmid_regs_init(id)\ 630 DCN20_VMID_REG_LIST_RI(id) 631 632 static struct dcn_vmid_registers vmid_regs[16]; 633 634 static const struct dcn20_vmid_shift vmid_shifts = { 635 DCN20_VMID_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dcn20_vmid_mask vmid_masks = { 639 DCN20_VMID_MASK_SH_LIST(_MASK) 640 }; 641 642 static const struct resource_caps res_cap_dcn32 = { 643 .num_timing_generator = 4, 644 .num_opp = 4, 645 .num_video_plane = 4, 646 .num_audio = 5, 647 .num_stream_encoder = 5, 648 .num_hpo_dp_stream_encoder = 4, 649 .num_hpo_dp_link_encoder = 2, 650 .num_pll = 5, 651 .num_dwb = 1, 652 .num_ddc = 5, 653 .num_vmid = 16, 654 .num_mpc_3dlut = 4, 655 .num_dsc = 4, 656 }; 657 658 static const struct dc_plane_cap plane_cap = { 659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 660 .blends_with_above = true, 661 .blends_with_below = true, 662 .per_pixel_alpha = true, 663 664 .pixel_format_support = { 665 .argb8888 = true, 666 .nv12 = true, 667 .fp16 = true, 668 .p010 = true, 669 .ayuv = false, 670 }, 671 672 .max_upscale_factor = { 673 .argb8888 = 16000, 674 .nv12 = 16000, 675 .fp16 = 16000 676 }, 677 678 // 6:1 downscaling ratio: 1000/6 = 166.666 679 .max_downscale_factor = { 680 .argb8888 = 167, 681 .nv12 = 167, 682 .fp16 = 167 683 }, 684 64, 685 64 686 }; 687 688 static const struct dc_debug_options debug_defaults_drv = { 689 .disable_dmcu = true, 690 .force_abm_enable = false, 691 .timing_trace = false, 692 .clock_trace = true, 693 .disable_pplib_clock_request = false, 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 695 .force_single_disp_pipe_split = false, 696 .disable_dcc = DCC_ENABLE, 697 .vsr_support = true, 698 .performance_trace = false, 699 .max_downscale_src_width = 7680,/*upto 8K*/ 700 .disable_pplib_wm_range = false, 701 .scl_reset_length10 = true, 702 .sanity_checks = false, 703 .underflow_assert_delay_us = 0xFFFFFFFF, 704 .dwb_fi_phase = -1, // -1 = disable, 705 .dmub_command_table = true, 706 .enable_mem_low_power = { 707 .bits = { 708 .vga = false, 709 .i2c = false, 710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 711 .dscl = false, 712 .cm = false, 713 .mpc = false, 714 .optc = true, 715 } 716 }, 717 .use_max_lb = true, 718 .force_disable_subvp = false, 719 .exit_idle_opt_for_cursor_updates = true, 720 .enable_single_display_2to1_odm_policy = true, 721 722 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 723 .enable_double_buffered_dsc_pg_support = true, 724 .enable_dp_dig_pixel_rate_div_policy = 1, 725 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 726 .alloc_extra_way_for_cursor = true, 727 .min_prefetch_in_strobe_ns = 60000, // 60us 728 .disable_unbounded_requesting = false, 729 .override_dispclk_programming = true, 730 }; 731 732 static const struct dc_debug_options debug_defaults_diags = { 733 .disable_dmcu = true, 734 .force_abm_enable = false, 735 .timing_trace = true, 736 .clock_trace = true, 737 .disable_dpp_power_gate = true, 738 .disable_hubp_power_gate = true, 739 .disable_dsc_power_gate = true, 740 .disable_clock_gate = true, 741 .disable_pplib_clock_request = true, 742 .disable_pplib_wm_range = true, 743 .disable_stutter = false, 744 .scl_reset_length10 = true, 745 .dwb_fi_phase = -1, // -1 = disable 746 .dmub_command_table = true, 747 .enable_tri_buf = true, 748 .use_max_lb = true, 749 .force_disable_subvp = true 750 }; 751 752 static struct dce_aux *dcn32_aux_engine_create( 753 struct dc_context *ctx, 754 uint32_t inst) 755 { 756 struct aux_engine_dce110 *aux_engine = 757 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 758 759 if (!aux_engine) 760 return NULL; 761 762 #undef REG_STRUCT 763 #define REG_STRUCT aux_engine_regs 764 aux_engine_regs_init(0), 765 aux_engine_regs_init(1), 766 aux_engine_regs_init(2), 767 aux_engine_regs_init(3), 768 aux_engine_regs_init(4); 769 770 dce110_aux_engine_construct(aux_engine, ctx, inst, 771 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 772 &aux_engine_regs[inst], 773 &aux_mask, 774 &aux_shift, 775 ctx->dc->caps.extended_aux_timeout_support); 776 777 return &aux_engine->base; 778 } 779 #define i2c_inst_regs_init(id)\ 780 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 781 782 static struct dce_i2c_registers i2c_hw_regs[5]; 783 784 static const struct dce_i2c_shift i2c_shifts = { 785 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 786 }; 787 788 static const struct dce_i2c_mask i2c_masks = { 789 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 790 }; 791 792 static struct dce_i2c_hw *dcn32_i2c_hw_create( 793 struct dc_context *ctx, 794 uint32_t inst) 795 { 796 struct dce_i2c_hw *dce_i2c_hw = 797 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 798 799 if (!dce_i2c_hw) 800 return NULL; 801 802 #undef REG_STRUCT 803 #define REG_STRUCT i2c_hw_regs 804 i2c_inst_regs_init(1), 805 i2c_inst_regs_init(2), 806 i2c_inst_regs_init(3), 807 i2c_inst_regs_init(4), 808 i2c_inst_regs_init(5); 809 810 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 811 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 812 813 return dce_i2c_hw; 814 } 815 816 static struct clock_source *dcn32_clock_source_create( 817 struct dc_context *ctx, 818 struct dc_bios *bios, 819 enum clock_source_id id, 820 const struct dce110_clk_src_regs *regs, 821 bool dp_clk_src) 822 { 823 struct dce110_clk_src *clk_src = 824 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 825 826 if (!clk_src) 827 return NULL; 828 829 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 830 regs, &cs_shift, &cs_mask)) { 831 clk_src->base.dp_clk_src = dp_clk_src; 832 return &clk_src->base; 833 } 834 835 kfree(clk_src); 836 BREAK_TO_DEBUGGER(); 837 return NULL; 838 } 839 840 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 841 { 842 int i; 843 844 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 845 GFP_KERNEL); 846 847 if (!hubbub2) 848 return NULL; 849 850 #undef REG_STRUCT 851 #define REG_STRUCT hubbub_reg 852 hubbub_reg_init(); 853 854 #undef REG_STRUCT 855 #define REG_STRUCT vmid_regs 856 vmid_regs_init(0), 857 vmid_regs_init(1), 858 vmid_regs_init(2), 859 vmid_regs_init(3), 860 vmid_regs_init(4), 861 vmid_regs_init(5), 862 vmid_regs_init(6), 863 vmid_regs_init(7), 864 vmid_regs_init(8), 865 vmid_regs_init(9), 866 vmid_regs_init(10), 867 vmid_regs_init(11), 868 vmid_regs_init(12), 869 vmid_regs_init(13), 870 vmid_regs_init(14), 871 vmid_regs_init(15); 872 873 hubbub32_construct(hubbub2, ctx, 874 &hubbub_reg, 875 &hubbub_shift, 876 &hubbub_mask, 877 ctx->dc->dml.ip.det_buffer_size_kbytes, 878 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 879 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 880 881 882 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 883 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 884 885 vmid->ctx = ctx; 886 887 vmid->regs = &vmid_regs[i]; 888 vmid->shifts = &vmid_shifts; 889 vmid->masks = &vmid_masks; 890 } 891 892 return &hubbub2->base; 893 } 894 895 static struct hubp *dcn32_hubp_create( 896 struct dc_context *ctx, 897 uint32_t inst) 898 { 899 struct dcn20_hubp *hubp2 = 900 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 901 902 if (!hubp2) 903 return NULL; 904 905 #undef REG_STRUCT 906 #define REG_STRUCT hubp_regs 907 hubp_regs_init(0), 908 hubp_regs_init(1), 909 hubp_regs_init(2), 910 hubp_regs_init(3); 911 912 if (hubp32_construct(hubp2, ctx, inst, 913 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 914 return &hubp2->base; 915 916 BREAK_TO_DEBUGGER(); 917 kfree(hubp2); 918 return NULL; 919 } 920 921 static void dcn32_dpp_destroy(struct dpp **dpp) 922 { 923 kfree(TO_DCN30_DPP(*dpp)); 924 *dpp = NULL; 925 } 926 927 static struct dpp *dcn32_dpp_create( 928 struct dc_context *ctx, 929 uint32_t inst) 930 { 931 struct dcn3_dpp *dpp3 = 932 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 933 934 if (!dpp3) 935 return NULL; 936 937 #undef REG_STRUCT 938 #define REG_STRUCT dpp_regs 939 dpp_regs_init(0), 940 dpp_regs_init(1), 941 dpp_regs_init(2), 942 dpp_regs_init(3); 943 944 if (dpp32_construct(dpp3, ctx, inst, 945 &dpp_regs[inst], &tf_shift, &tf_mask)) 946 return &dpp3->base; 947 948 BREAK_TO_DEBUGGER(); 949 kfree(dpp3); 950 return NULL; 951 } 952 953 static struct mpc *dcn32_mpc_create( 954 struct dc_context *ctx, 955 int num_mpcc, 956 int num_rmu) 957 { 958 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 959 GFP_KERNEL); 960 961 if (!mpc30) 962 return NULL; 963 964 #undef REG_STRUCT 965 #define REG_STRUCT mpc_regs 966 dcn_mpc_regs_init(); 967 968 dcn32_mpc_construct(mpc30, ctx, 969 &mpc_regs, 970 &mpc_shift, 971 &mpc_mask, 972 num_mpcc, 973 num_rmu); 974 975 return &mpc30->base; 976 } 977 978 static struct output_pixel_processor *dcn32_opp_create( 979 struct dc_context *ctx, uint32_t inst) 980 { 981 struct dcn20_opp *opp2 = 982 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 983 984 if (!opp2) { 985 BREAK_TO_DEBUGGER(); 986 return NULL; 987 } 988 989 #undef REG_STRUCT 990 #define REG_STRUCT opp_regs 991 opp_regs_init(0), 992 opp_regs_init(1), 993 opp_regs_init(2), 994 opp_regs_init(3); 995 996 dcn20_opp_construct(opp2, ctx, inst, 997 &opp_regs[inst], &opp_shift, &opp_mask); 998 return &opp2->base; 999 } 1000 1001 1002 static struct timing_generator *dcn32_timing_generator_create( 1003 struct dc_context *ctx, 1004 uint32_t instance) 1005 { 1006 struct optc *tgn10 = 1007 kzalloc(sizeof(struct optc), GFP_KERNEL); 1008 1009 if (!tgn10) 1010 return NULL; 1011 1012 #undef REG_STRUCT 1013 #define REG_STRUCT optc_regs 1014 optc_regs_init(0), 1015 optc_regs_init(1), 1016 optc_regs_init(2), 1017 optc_regs_init(3); 1018 1019 tgn10->base.inst = instance; 1020 tgn10->base.ctx = ctx; 1021 1022 tgn10->tg_regs = &optc_regs[instance]; 1023 tgn10->tg_shift = &optc_shift; 1024 tgn10->tg_mask = &optc_mask; 1025 1026 dcn32_timing_generator_init(tgn10); 1027 1028 return &tgn10->base; 1029 } 1030 1031 static const struct encoder_feature_support link_enc_feature = { 1032 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1033 .max_hdmi_pixel_clock = 600000, 1034 .hdmi_ycbcr420_supported = true, 1035 .dp_ycbcr420_supported = true, 1036 .fec_supported = true, 1037 .flags.bits.IS_HBR2_CAPABLE = true, 1038 .flags.bits.IS_HBR3_CAPABLE = true, 1039 .flags.bits.IS_TPS3_CAPABLE = true, 1040 .flags.bits.IS_TPS4_CAPABLE = true 1041 }; 1042 1043 static struct link_encoder *dcn32_link_encoder_create( 1044 struct dc_context *ctx, 1045 const struct encoder_init_data *enc_init_data) 1046 { 1047 struct dcn20_link_encoder *enc20 = 1048 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1049 1050 if (!enc20) 1051 return NULL; 1052 1053 #undef REG_STRUCT 1054 #define REG_STRUCT link_enc_aux_regs 1055 aux_regs_init(0), 1056 aux_regs_init(1), 1057 aux_regs_init(2), 1058 aux_regs_init(3), 1059 aux_regs_init(4); 1060 1061 #undef REG_STRUCT 1062 #define REG_STRUCT link_enc_hpd_regs 1063 hpd_regs_init(0), 1064 hpd_regs_init(1), 1065 hpd_regs_init(2), 1066 hpd_regs_init(3), 1067 hpd_regs_init(4); 1068 1069 #undef REG_STRUCT 1070 #define REG_STRUCT link_enc_regs 1071 link_regs_init(0, A), 1072 link_regs_init(1, B), 1073 link_regs_init(2, C), 1074 link_regs_init(3, D), 1075 link_regs_init(4, E); 1076 1077 dcn32_link_encoder_construct(enc20, 1078 enc_init_data, 1079 &link_enc_feature, 1080 &link_enc_regs[enc_init_data->transmitter], 1081 &link_enc_aux_regs[enc_init_data->channel - 1], 1082 &link_enc_hpd_regs[enc_init_data->hpd_source], 1083 &le_shift, 1084 &le_mask); 1085 1086 return &enc20->enc10.base; 1087 } 1088 1089 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1090 { 1091 struct dcn31_panel_cntl *panel_cntl = 1092 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1093 1094 if (!panel_cntl) 1095 return NULL; 1096 1097 dcn31_panel_cntl_construct(panel_cntl, init_data); 1098 1099 return &panel_cntl->base; 1100 } 1101 1102 static void read_dce_straps( 1103 struct dc_context *ctx, 1104 struct resource_straps *straps) 1105 { 1106 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1107 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1108 1109 } 1110 1111 static struct audio *dcn32_create_audio( 1112 struct dc_context *ctx, unsigned int inst) 1113 { 1114 1115 #undef REG_STRUCT 1116 #define REG_STRUCT audio_regs 1117 audio_regs_init(0), 1118 audio_regs_init(1), 1119 audio_regs_init(2), 1120 audio_regs_init(3), 1121 audio_regs_init(4); 1122 1123 return dce_audio_create(ctx, inst, 1124 &audio_regs[inst], &audio_shift, &audio_mask); 1125 } 1126 1127 static struct vpg *dcn32_vpg_create( 1128 struct dc_context *ctx, 1129 uint32_t inst) 1130 { 1131 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1132 1133 if (!vpg3) 1134 return NULL; 1135 1136 #undef REG_STRUCT 1137 #define REG_STRUCT vpg_regs 1138 vpg_regs_init(0), 1139 vpg_regs_init(1), 1140 vpg_regs_init(2), 1141 vpg_regs_init(3), 1142 vpg_regs_init(4), 1143 vpg_regs_init(5), 1144 vpg_regs_init(6), 1145 vpg_regs_init(7), 1146 vpg_regs_init(8), 1147 vpg_regs_init(9); 1148 1149 vpg3_construct(vpg3, ctx, inst, 1150 &vpg_regs[inst], 1151 &vpg_shift, 1152 &vpg_mask); 1153 1154 return &vpg3->base; 1155 } 1156 1157 static struct afmt *dcn32_afmt_create( 1158 struct dc_context *ctx, 1159 uint32_t inst) 1160 { 1161 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1162 1163 if (!afmt3) 1164 return NULL; 1165 1166 #undef REG_STRUCT 1167 #define REG_STRUCT afmt_regs 1168 afmt_regs_init(0), 1169 afmt_regs_init(1), 1170 afmt_regs_init(2), 1171 afmt_regs_init(3), 1172 afmt_regs_init(4), 1173 afmt_regs_init(5); 1174 1175 afmt3_construct(afmt3, ctx, inst, 1176 &afmt_regs[inst], 1177 &afmt_shift, 1178 &afmt_mask); 1179 1180 return &afmt3->base; 1181 } 1182 1183 static struct apg *dcn31_apg_create( 1184 struct dc_context *ctx, 1185 uint32_t inst) 1186 { 1187 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1188 1189 if (!apg31) 1190 return NULL; 1191 1192 #undef REG_STRUCT 1193 #define REG_STRUCT apg_regs 1194 apg_regs_init(0), 1195 apg_regs_init(1), 1196 apg_regs_init(2), 1197 apg_regs_init(3); 1198 1199 apg31_construct(apg31, ctx, inst, 1200 &apg_regs[inst], 1201 &apg_shift, 1202 &apg_mask); 1203 1204 return &apg31->base; 1205 } 1206 1207 static struct stream_encoder *dcn32_stream_encoder_create( 1208 enum engine_id eng_id, 1209 struct dc_context *ctx) 1210 { 1211 struct dcn10_stream_encoder *enc1; 1212 struct vpg *vpg; 1213 struct afmt *afmt; 1214 int vpg_inst; 1215 int afmt_inst; 1216 1217 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1218 if (eng_id <= ENGINE_ID_DIGF) { 1219 vpg_inst = eng_id; 1220 afmt_inst = eng_id; 1221 } else 1222 return NULL; 1223 1224 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1225 vpg = dcn32_vpg_create(ctx, vpg_inst); 1226 afmt = dcn32_afmt_create(ctx, afmt_inst); 1227 1228 if (!enc1 || !vpg || !afmt) { 1229 kfree(enc1); 1230 kfree(vpg); 1231 kfree(afmt); 1232 return NULL; 1233 } 1234 1235 #undef REG_STRUCT 1236 #define REG_STRUCT stream_enc_regs 1237 stream_enc_regs_init(0), 1238 stream_enc_regs_init(1), 1239 stream_enc_regs_init(2), 1240 stream_enc_regs_init(3), 1241 stream_enc_regs_init(4); 1242 1243 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1244 eng_id, vpg, afmt, 1245 &stream_enc_regs[eng_id], 1246 &se_shift, &se_mask); 1247 1248 return &enc1->base; 1249 } 1250 1251 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1252 enum engine_id eng_id, 1253 struct dc_context *ctx) 1254 { 1255 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1256 struct vpg *vpg; 1257 struct apg *apg; 1258 uint32_t hpo_dp_inst; 1259 uint32_t vpg_inst; 1260 uint32_t apg_inst; 1261 1262 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1263 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1264 1265 /* Mapping of VPG register blocks to HPO DP block instance: 1266 * VPG[6] -> HPO_DP[0] 1267 * VPG[7] -> HPO_DP[1] 1268 * VPG[8] -> HPO_DP[2] 1269 * VPG[9] -> HPO_DP[3] 1270 */ 1271 vpg_inst = hpo_dp_inst + 6; 1272 1273 /* Mapping of APG register blocks to HPO DP block instance: 1274 * APG[0] -> HPO_DP[0] 1275 * APG[1] -> HPO_DP[1] 1276 * APG[2] -> HPO_DP[2] 1277 * APG[3] -> HPO_DP[3] 1278 */ 1279 apg_inst = hpo_dp_inst; 1280 1281 /* allocate HPO stream encoder and create VPG sub-block */ 1282 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1283 vpg = dcn32_vpg_create(ctx, vpg_inst); 1284 apg = dcn31_apg_create(ctx, apg_inst); 1285 1286 if (!hpo_dp_enc31 || !vpg || !apg) { 1287 kfree(hpo_dp_enc31); 1288 kfree(vpg); 1289 kfree(apg); 1290 return NULL; 1291 } 1292 1293 #undef REG_STRUCT 1294 #define REG_STRUCT hpo_dp_stream_enc_regs 1295 hpo_dp_stream_encoder_reg_init(0), 1296 hpo_dp_stream_encoder_reg_init(1), 1297 hpo_dp_stream_encoder_reg_init(2), 1298 hpo_dp_stream_encoder_reg_init(3); 1299 1300 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1301 hpo_dp_inst, eng_id, vpg, apg, 1302 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1303 &hpo_dp_se_shift, &hpo_dp_se_mask); 1304 1305 return &hpo_dp_enc31->base; 1306 } 1307 1308 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1309 uint8_t inst, 1310 struct dc_context *ctx) 1311 { 1312 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1313 1314 /* allocate HPO link encoder */ 1315 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1316 1317 #undef REG_STRUCT 1318 #define REG_STRUCT hpo_dp_link_enc_regs 1319 hpo_dp_link_encoder_reg_init(0), 1320 hpo_dp_link_encoder_reg_init(1); 1321 1322 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1323 &hpo_dp_link_enc_regs[inst], 1324 &hpo_dp_le_shift, &hpo_dp_le_mask); 1325 1326 return &hpo_dp_enc31->base; 1327 } 1328 1329 static struct dce_hwseq *dcn32_hwseq_create( 1330 struct dc_context *ctx) 1331 { 1332 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1333 1334 #undef REG_STRUCT 1335 #define REG_STRUCT hwseq_reg 1336 hwseq_reg_init(); 1337 1338 if (hws) { 1339 hws->ctx = ctx; 1340 hws->regs = &hwseq_reg; 1341 hws->shifts = &hwseq_shift; 1342 hws->masks = &hwseq_mask; 1343 } 1344 return hws; 1345 } 1346 static const struct resource_create_funcs res_create_funcs = { 1347 .read_dce_straps = read_dce_straps, 1348 .create_audio = dcn32_create_audio, 1349 .create_stream_encoder = dcn32_stream_encoder_create, 1350 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1351 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1352 .create_hwseq = dcn32_hwseq_create, 1353 }; 1354 1355 static const struct resource_create_funcs res_create_maximus_funcs = { 1356 .read_dce_straps = NULL, 1357 .create_audio = NULL, 1358 .create_stream_encoder = NULL, 1359 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1360 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1361 .create_hwseq = dcn32_hwseq_create, 1362 }; 1363 1364 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1365 { 1366 unsigned int i; 1367 1368 for (i = 0; i < pool->base.stream_enc_count; i++) { 1369 if (pool->base.stream_enc[i] != NULL) { 1370 if (pool->base.stream_enc[i]->vpg != NULL) { 1371 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1372 pool->base.stream_enc[i]->vpg = NULL; 1373 } 1374 if (pool->base.stream_enc[i]->afmt != NULL) { 1375 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1376 pool->base.stream_enc[i]->afmt = NULL; 1377 } 1378 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1379 pool->base.stream_enc[i] = NULL; 1380 } 1381 } 1382 1383 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1384 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1385 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1386 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1387 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1388 } 1389 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1390 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1391 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1392 } 1393 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1394 pool->base.hpo_dp_stream_enc[i] = NULL; 1395 } 1396 } 1397 1398 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1399 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1400 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1401 pool->base.hpo_dp_link_enc[i] = NULL; 1402 } 1403 } 1404 1405 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1406 if (pool->base.dscs[i] != NULL) 1407 dcn20_dsc_destroy(&pool->base.dscs[i]); 1408 } 1409 1410 if (pool->base.mpc != NULL) { 1411 kfree(TO_DCN20_MPC(pool->base.mpc)); 1412 pool->base.mpc = NULL; 1413 } 1414 if (pool->base.hubbub != NULL) { 1415 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1416 pool->base.hubbub = NULL; 1417 } 1418 for (i = 0; i < pool->base.pipe_count; i++) { 1419 if (pool->base.dpps[i] != NULL) 1420 dcn32_dpp_destroy(&pool->base.dpps[i]); 1421 1422 if (pool->base.ipps[i] != NULL) 1423 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1424 1425 if (pool->base.hubps[i] != NULL) { 1426 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1427 pool->base.hubps[i] = NULL; 1428 } 1429 1430 if (pool->base.irqs != NULL) { 1431 dal_irq_service_destroy(&pool->base.irqs); 1432 } 1433 } 1434 1435 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1436 if (pool->base.engines[i] != NULL) 1437 dce110_engine_destroy(&pool->base.engines[i]); 1438 if (pool->base.hw_i2cs[i] != NULL) { 1439 kfree(pool->base.hw_i2cs[i]); 1440 pool->base.hw_i2cs[i] = NULL; 1441 } 1442 if (pool->base.sw_i2cs[i] != NULL) { 1443 kfree(pool->base.sw_i2cs[i]); 1444 pool->base.sw_i2cs[i] = NULL; 1445 } 1446 } 1447 1448 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1449 if (pool->base.opps[i] != NULL) 1450 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1451 } 1452 1453 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1454 if (pool->base.timing_generators[i] != NULL) { 1455 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1456 pool->base.timing_generators[i] = NULL; 1457 } 1458 } 1459 1460 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1461 if (pool->base.dwbc[i] != NULL) { 1462 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1463 pool->base.dwbc[i] = NULL; 1464 } 1465 if (pool->base.mcif_wb[i] != NULL) { 1466 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1467 pool->base.mcif_wb[i] = NULL; 1468 } 1469 } 1470 1471 for (i = 0; i < pool->base.audio_count; i++) { 1472 if (pool->base.audios[i]) 1473 dce_aud_destroy(&pool->base.audios[i]); 1474 } 1475 1476 for (i = 0; i < pool->base.clk_src_count; i++) { 1477 if (pool->base.clock_sources[i] != NULL) { 1478 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1479 pool->base.clock_sources[i] = NULL; 1480 } 1481 } 1482 1483 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1484 if (pool->base.mpc_lut[i] != NULL) { 1485 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1486 pool->base.mpc_lut[i] = NULL; 1487 } 1488 if (pool->base.mpc_shaper[i] != NULL) { 1489 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1490 pool->base.mpc_shaper[i] = NULL; 1491 } 1492 } 1493 1494 if (pool->base.dp_clock_source != NULL) { 1495 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1496 pool->base.dp_clock_source = NULL; 1497 } 1498 1499 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1500 if (pool->base.multiple_abms[i] != NULL) 1501 dce_abm_destroy(&pool->base.multiple_abms[i]); 1502 } 1503 1504 if (pool->base.psr != NULL) 1505 dmub_psr_destroy(&pool->base.psr); 1506 1507 if (pool->base.dccg != NULL) 1508 dcn_dccg_destroy(&pool->base.dccg); 1509 1510 if (pool->base.oem_device != NULL) 1511 link_destroy_ddc_service(&pool->base.oem_device); 1512 } 1513 1514 1515 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1516 { 1517 int i; 1518 uint32_t dwb_count = pool->res_cap->num_dwb; 1519 1520 for (i = 0; i < dwb_count; i++) { 1521 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1522 GFP_KERNEL); 1523 1524 if (!dwbc30) { 1525 dm_error("DC: failed to create dwbc30!\n"); 1526 return false; 1527 } 1528 1529 #undef REG_STRUCT 1530 #define REG_STRUCT dwbc30_regs 1531 dwbc_regs_dcn3_init(0); 1532 1533 dcn30_dwbc_construct(dwbc30, ctx, 1534 &dwbc30_regs[i], 1535 &dwbc30_shift, 1536 &dwbc30_mask, 1537 i); 1538 1539 pool->dwbc[i] = &dwbc30->base; 1540 } 1541 return true; 1542 } 1543 1544 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1545 { 1546 int i; 1547 uint32_t dwb_count = pool->res_cap->num_dwb; 1548 1549 for (i = 0; i < dwb_count; i++) { 1550 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1551 GFP_KERNEL); 1552 1553 if (!mcif_wb30) { 1554 dm_error("DC: failed to create mcif_wb30!\n"); 1555 return false; 1556 } 1557 1558 #undef REG_STRUCT 1559 #define REG_STRUCT mcif_wb30_regs 1560 mcif_wb_regs_dcn3_init(0); 1561 1562 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1563 &mcif_wb30_regs[i], 1564 &mcif_wb30_shift, 1565 &mcif_wb30_mask, 1566 i); 1567 1568 pool->mcif_wb[i] = &mcif_wb30->base; 1569 } 1570 return true; 1571 } 1572 1573 static struct display_stream_compressor *dcn32_dsc_create( 1574 struct dc_context *ctx, uint32_t inst) 1575 { 1576 struct dcn20_dsc *dsc = 1577 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1578 1579 if (!dsc) { 1580 BREAK_TO_DEBUGGER(); 1581 return NULL; 1582 } 1583 1584 #undef REG_STRUCT 1585 #define REG_STRUCT dsc_regs 1586 dsc_regsDCN20_init(0), 1587 dsc_regsDCN20_init(1), 1588 dsc_regsDCN20_init(2), 1589 dsc_regsDCN20_init(3); 1590 1591 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1592 1593 dsc->max_image_width = 6016; 1594 1595 return &dsc->base; 1596 } 1597 1598 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1599 { 1600 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1601 1602 dcn32_resource_destruct(dcn32_pool); 1603 kfree(dcn32_pool); 1604 *pool = NULL; 1605 } 1606 1607 bool dcn32_acquire_post_bldn_3dlut( 1608 struct resource_context *res_ctx, 1609 const struct resource_pool *pool, 1610 int mpcc_id, 1611 struct dc_3dlut **lut, 1612 struct dc_transfer_func **shaper) 1613 { 1614 bool ret = false; 1615 1616 ASSERT(*lut == NULL && *shaper == NULL); 1617 *lut = NULL; 1618 *shaper = NULL; 1619 1620 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1621 *lut = pool->mpc_lut[mpcc_id]; 1622 *shaper = pool->mpc_shaper[mpcc_id]; 1623 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1624 ret = true; 1625 } 1626 return ret; 1627 } 1628 1629 bool dcn32_release_post_bldn_3dlut( 1630 struct resource_context *res_ctx, 1631 const struct resource_pool *pool, 1632 struct dc_3dlut **lut, 1633 struct dc_transfer_func **shaper) 1634 { 1635 int i; 1636 bool ret = false; 1637 1638 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1639 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1640 res_ctx->is_mpc_3dlut_acquired[i] = false; 1641 pool->mpc_lut[i]->state.raw = 0; 1642 *lut = NULL; 1643 *shaper = NULL; 1644 ret = true; 1645 break; 1646 } 1647 } 1648 return ret; 1649 } 1650 1651 static void dcn32_enable_phantom_plane(struct dc *dc, 1652 struct dc_state *context, 1653 struct dc_stream_state *phantom_stream, 1654 unsigned int dc_pipe_idx) 1655 { 1656 struct dc_plane_state *phantom_plane = NULL; 1657 struct dc_plane_state *prev_phantom_plane = NULL; 1658 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1659 1660 while (curr_pipe) { 1661 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1662 phantom_plane = prev_phantom_plane; 1663 else 1664 phantom_plane = dc_create_plane_state(dc); 1665 1666 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1667 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1668 sizeof(phantom_plane->scaling_quality)); 1669 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1670 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1671 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1672 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1673 sizeof(phantom_plane->plane_size)); 1674 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1675 sizeof(phantom_plane->tiling_info)); 1676 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1677 phantom_plane->format = curr_pipe->plane_state->format; 1678 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1679 phantom_plane->visible = curr_pipe->plane_state->visible; 1680 1681 /* Shadow pipe has small viewport. */ 1682 phantom_plane->clip_rect.y = 0; 1683 phantom_plane->clip_rect.height = phantom_stream->src.height; 1684 1685 phantom_plane->is_phantom = true; 1686 1687 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); 1688 1689 curr_pipe = curr_pipe->bottom_pipe; 1690 prev_phantom_plane = phantom_plane; 1691 } 1692 } 1693 1694 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1695 struct dc_state *context, 1696 display_e2e_pipe_params_st *pipes, 1697 unsigned int pipe_cnt, 1698 unsigned int dc_pipe_idx) 1699 { 1700 struct dc_stream_state *phantom_stream = NULL; 1701 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1702 1703 phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); 1704 phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; 1705 phantom_stream->dpms_off = true; 1706 phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; 1707 phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; 1708 ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; 1709 ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; 1710 1711 /* stream has limited viewport and small timing */ 1712 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1713 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1714 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1715 DC_FP_START(); 1716 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1717 DC_FP_END(); 1718 1719 dc_add_stream_to_ctx(dc, context, phantom_stream); 1720 return phantom_stream; 1721 } 1722 1723 void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) 1724 { 1725 int i; 1726 struct dc_plane_state *phantom_plane = NULL; 1727 struct dc_stream_state *phantom_stream = NULL; 1728 1729 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1730 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1731 1732 if (!pipe->top_pipe && !pipe->prev_odm_pipe && 1733 pipe->plane_state && pipe->stream && 1734 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1735 phantom_plane = pipe->plane_state; 1736 phantom_stream = pipe->stream; 1737 1738 dc_plane_state_retain(phantom_plane); 1739 dc_stream_retain(phantom_stream); 1740 } 1741 } 1742 } 1743 1744 // return true if removed piped from ctx, false otherwise 1745 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update) 1746 { 1747 int i; 1748 bool removed_pipe = false; 1749 struct dc_plane_state *phantom_plane = NULL; 1750 struct dc_stream_state *phantom_stream = NULL; 1751 1752 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1753 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1754 // build scaling params for phantom pipes 1755 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1756 phantom_plane = pipe->plane_state; 1757 phantom_stream = pipe->stream; 1758 1759 dc_rem_all_planes_for_stream(dc, pipe->stream, context); 1760 dc_remove_stream_from_ctx(dc, context, pipe->stream); 1761 1762 /* Ref count is incremented on allocation and also when added to the context. 1763 * Therefore we must call release for the the phantom plane and stream once 1764 * they are removed from the ctx to finally decrement the refcount to 0 to free. 1765 */ 1766 dc_plane_state_release(phantom_plane); 1767 dc_stream_release(phantom_stream); 1768 1769 removed_pipe = true; 1770 } 1771 1772 /* For non-full updates, a shallow copy of the current state 1773 * is created. In this case we don't want to erase the current 1774 * state (there can be 2 HIRQL threads, one in flip, and one in 1775 * checkMPO) that can cause a race condition. 1776 * 1777 * This is just a workaround, needs a proper fix. 1778 */ 1779 if (!fast_update) { 1780 // Clear all phantom stream info 1781 if (pipe->stream) { 1782 pipe->stream->mall_stream_config.type = SUBVP_NONE; 1783 pipe->stream->mall_stream_config.paired_stream = NULL; 1784 } 1785 1786 if (pipe->plane_state) { 1787 pipe->plane_state->is_phantom = false; 1788 } 1789 } 1790 } 1791 return removed_pipe; 1792 } 1793 1794 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1795 * require a phantom pipe / stream 1796 */ 1797 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1798 display_e2e_pipe_params_st *pipes, 1799 unsigned int pipe_cnt, 1800 unsigned int index) 1801 { 1802 struct dc_stream_state *phantom_stream = NULL; 1803 unsigned int i; 1804 1805 // The index of the DC pipe passed into this function is guarenteed to 1806 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1807 // already have phantom pipe assigned, etc.) by previous checks. 1808 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1809 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1810 1811 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1812 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1813 1814 // Build scaling params for phantom pipes which were newly added. 1815 // We determine which phantom pipes were added by comparing with 1816 // the phantom stream. 1817 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1818 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1819 pipe->stream->use_dynamic_meta = false; 1820 pipe->plane_state->flip_immediate = false; 1821 if (!resource_build_scaling_params(pipe)) { 1822 // Log / remove phantom pipes since failed to build scaling params 1823 } 1824 } 1825 } 1826 } 1827 1828 bool dcn32_validate_bandwidth(struct dc *dc, 1829 struct dc_state *context, 1830 bool fast_validate) 1831 { 1832 bool out = false; 1833 1834 BW_VAL_TRACE_SETUP(); 1835 1836 int vlevel = 0; 1837 int pipe_cnt = 0; 1838 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1839 struct mall_temp_config mall_temp_config; 1840 1841 /* To handle Freesync properly, setting FreeSync DML parameters 1842 * to its default state for the first stage of validation 1843 */ 1844 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1845 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1846 1847 DC_LOGGER_INIT(dc->ctx->logger); 1848 1849 /* For fast validation, there are situations where a shallow copy of 1850 * of the dc->current_state is created for the validation. In this case 1851 * we want to save and restore the mall config because we always 1852 * teardown subvp at the beginning of validation (and don't attempt 1853 * to add it back if it's fast validation). If we don't restore the 1854 * subvp config in cases of fast validation + shallow copy of the 1855 * dc->current_state, the dc->current_state will have a partially 1856 * removed subvp state when we did not intend to remove it. 1857 */ 1858 if (fast_validate) { 1859 memset(&mall_temp_config, 0, sizeof(mall_temp_config)); 1860 dcn32_save_mall_state(dc, context, &mall_temp_config); 1861 } 1862 1863 BW_VAL_TRACE_COUNT(); 1864 1865 DC_FP_START(); 1866 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1867 DC_FP_END(); 1868 1869 if (fast_validate) 1870 dcn32_restore_mall_state(dc, context, &mall_temp_config); 1871 1872 if (pipe_cnt == 0) 1873 goto validate_out; 1874 1875 if (!out) 1876 goto validate_fail; 1877 1878 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1879 1880 if (fast_validate) { 1881 BW_VAL_TRACE_SKIP(fast); 1882 goto validate_out; 1883 } 1884 1885 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1886 1887 BW_VAL_TRACE_END_WATERMARKS(); 1888 1889 goto validate_out; 1890 1891 validate_fail: 1892 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1893 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1894 1895 BW_VAL_TRACE_SKIP(fail); 1896 out = false; 1897 1898 validate_out: 1899 kfree(pipes); 1900 1901 BW_VAL_TRACE_FINISH(); 1902 1903 return out; 1904 } 1905 1906 int dcn32_populate_dml_pipes_from_context( 1907 struct dc *dc, struct dc_state *context, 1908 display_e2e_pipe_params_st *pipes, 1909 bool fast_validate) 1910 { 1911 int i, pipe_cnt; 1912 struct resource_context *res_ctx = &context->res_ctx; 1913 struct pipe_ctx *pipe; 1914 bool subvp_in_use = false; 1915 struct dc_crtc_timing *timing; 1916 1917 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1918 1919 /* Determine whether we will apply ODM 2to1 policy: 1920 * Applies to single display and where the number of planes is less than 3. 1921 * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. 1922 * 1923 * Apply pipe split policy first so we can predict the pipe split correctly 1924 * (dcn32_predict_pipe_split). 1925 */ 1926 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1927 if (!res_ctx->pipe_ctx[i].stream) 1928 continue; 1929 pipe = &res_ctx->pipe_ctx[i]; 1930 timing = &pipe->stream->timing; 1931 1932 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1933 if (context->stream_count == 1 && 1934 context->stream_status[0].plane_count == 1 && 1935 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1936 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1937 pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1938 dc->debug.enable_single_display_2to1_odm_policy) { 1939 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1940 } 1941 pipe_cnt++; 1942 } 1943 1944 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1945 1946 if (!res_ctx->pipe_ctx[i].stream) 1947 continue; 1948 pipe = &res_ctx->pipe_ctx[i]; 1949 timing = &pipe->stream->timing; 1950 1951 pipes[pipe_cnt].pipe.src.gpuvm = true; 1952 DC_FP_START(); 1953 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1954 DC_FP_END(); 1955 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1956 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1957 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1958 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1959 1960 /* Only populate DML input with subvp info for full updates. 1961 * This is just a workaround -- needs a proper fix. 1962 */ 1963 if (!fast_validate) { 1964 switch (pipe->stream->mall_stream_config.type) { 1965 case SUBVP_MAIN: 1966 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1967 subvp_in_use = true; 1968 break; 1969 case SUBVP_PHANTOM: 1970 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1971 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1972 // Disallow unbounded req for SubVP according to DCHUB programming guide 1973 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1974 break; 1975 case SUBVP_NONE: 1976 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1977 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1978 break; 1979 default: 1980 break; 1981 } 1982 } 1983 1984 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1985 if (pipes[pipe_cnt].dout.dsc_enable) { 1986 switch (timing->display_color_depth) { 1987 case COLOR_DEPTH_888: 1988 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1989 break; 1990 case COLOR_DEPTH_101010: 1991 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1992 break; 1993 case COLOR_DEPTH_121212: 1994 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1995 break; 1996 default: 1997 ASSERT(0); 1998 break; 1999 } 2000 } 2001 2002 DC_FP_START(); 2003 dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); 2004 DC_FP_END(); 2005 2006 pipe_cnt++; 2007 } 2008 2009 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2010 * the DET available for each pipe). Use the DET override input to maintain our driver 2011 * policy. 2012 */ 2013 dcn32_set_det_allocations(dc, context, pipes); 2014 2015 // In general cases we want to keep the dram clock change requirement 2016 // (prefer configs that support MCLK switch). Only override to false 2017 // for SubVP 2018 if (subvp_in_use) 2019 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2020 else 2021 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2022 2023 return pipe_cnt; 2024 } 2025 2026 static struct dc_cap_funcs cap_funcs = { 2027 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2028 }; 2029 2030 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2031 display_e2e_pipe_params_st *pipes, 2032 int pipe_cnt, 2033 int vlevel) 2034 { 2035 DC_FP_START(); 2036 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2037 DC_FP_END(); 2038 } 2039 2040 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2041 { 2042 DC_FP_START(); 2043 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2044 DC_FP_END(); 2045 } 2046 2047 static struct resource_funcs dcn32_res_pool_funcs = { 2048 .destroy = dcn32_destroy_resource_pool, 2049 .link_enc_create = dcn32_link_encoder_create, 2050 .link_enc_create_minimal = NULL, 2051 .panel_cntl_create = dcn32_panel_cntl_create, 2052 .validate_bandwidth = dcn32_validate_bandwidth, 2053 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2054 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2055 .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, 2056 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2057 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2058 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2059 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2060 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2061 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2062 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2063 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2064 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2065 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2066 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2067 .add_phantom_pipes = dcn32_add_phantom_pipes, 2068 .remove_phantom_pipes = dcn32_remove_phantom_pipes, 2069 .retain_phantom_pipes = dcn32_retain_phantom_pipes, 2070 .save_mall_state = dcn32_save_mall_state, 2071 .restore_mall_state = dcn32_restore_mall_state, 2072 }; 2073 2074 2075 static bool dcn32_resource_construct( 2076 uint8_t num_virtual_links, 2077 struct dc *dc, 2078 struct dcn32_resource_pool *pool) 2079 { 2080 int i, j; 2081 struct dc_context *ctx = dc->ctx; 2082 struct irq_service_init_data init_data; 2083 struct ddc_service_init_data ddc_init_data = {0}; 2084 uint32_t pipe_fuses = 0; 2085 uint32_t num_pipes = 4; 2086 2087 #undef REG_STRUCT 2088 #define REG_STRUCT bios_regs 2089 bios_regs_init(); 2090 2091 #undef REG_STRUCT 2092 #define REG_STRUCT clk_src_regs 2093 clk_src_regs_init(0, A), 2094 clk_src_regs_init(1, B), 2095 clk_src_regs_init(2, C), 2096 clk_src_regs_init(3, D), 2097 clk_src_regs_init(4, E); 2098 #undef REG_STRUCT 2099 #define REG_STRUCT abm_regs 2100 abm_regs_init(0), 2101 abm_regs_init(1), 2102 abm_regs_init(2), 2103 abm_regs_init(3); 2104 2105 #undef REG_STRUCT 2106 #define REG_STRUCT dccg_regs 2107 dccg_regs_init(); 2108 2109 DC_FP_START(); 2110 2111 ctx->dc_bios->regs = &bios_regs; 2112 2113 pool->base.res_cap = &res_cap_dcn32; 2114 /* max number of pipes for ASIC before checking for pipe fuses */ 2115 num_pipes = pool->base.res_cap->num_timing_generator; 2116 pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2117 2118 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2119 if (pipe_fuses & 1 << i) 2120 num_pipes--; 2121 2122 if (pipe_fuses & 1) 2123 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2124 2125 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2126 ASSERT(0); //Entire DCN is harvested! 2127 2128 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2129 * value will be changed, update max_num_dpp and max_num_otg for dml. 2130 */ 2131 dcn3_2_ip.max_num_dpp = num_pipes; 2132 dcn3_2_ip.max_num_otg = num_pipes; 2133 2134 pool->base.funcs = &dcn32_res_pool_funcs; 2135 2136 /************************************************* 2137 * Resource + asic cap harcoding * 2138 *************************************************/ 2139 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2140 pool->base.timing_generator_count = num_pipes; 2141 pool->base.pipe_count = num_pipes; 2142 pool->base.mpcc_count = num_pipes; 2143 dc->caps.max_downscale_ratio = 600; 2144 dc->caps.i2c_speed_in_khz = 100; 2145 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2146 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2147 dc->caps.max_cursor_size = 64; 2148 dc->caps.min_horizontal_blanking_period = 80; 2149 dc->caps.dmdata_alloc_size = 2048; 2150 dc->caps.mall_size_per_mem_channel = 4; 2151 dc->caps.mall_size_total = 0; 2152 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2153 2154 dc->caps.cache_line_size = 64; 2155 dc->caps.cache_num_ways = 16; 2156 2157 /* Calculate the available MALL space */ 2158 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2159 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2160 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2161 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2162 2163 dc->caps.subvp_fw_processing_delay_us = 15; 2164 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2165 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2166 dc->caps.subvp_swath_height_margin_lines = 16; 2167 dc->caps.subvp_pstate_allow_width_us = 20; 2168 dc->caps.subvp_vertical_int_margin_us = 30; 2169 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2170 2171 dc->caps.max_slave_planes = 2; 2172 dc->caps.max_slave_yuv_planes = 2; 2173 dc->caps.max_slave_rgb_planes = 2; 2174 dc->caps.post_blend_color_processing = true; 2175 dc->caps.force_dp_tps4_for_cp2520 = true; 2176 if (dc->config.forceHBR2CP2520) 2177 dc->caps.force_dp_tps4_for_cp2520 = false; 2178 dc->caps.dp_hpo = true; 2179 dc->caps.dp_hdmi21_pcon_support = true; 2180 dc->caps.edp_dsc_support = true; 2181 dc->caps.extended_aux_timeout_support = true; 2182 dc->caps.dmcub_support = true; 2183 2184 /* Color pipeline capabilities */ 2185 dc->caps.color.dpp.dcn_arch = 1; 2186 dc->caps.color.dpp.input_lut_shared = 0; 2187 dc->caps.color.dpp.icsc = 1; 2188 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2189 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2190 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2191 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2192 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2193 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2194 dc->caps.color.dpp.post_csc = 1; 2195 dc->caps.color.dpp.gamma_corr = 1; 2196 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2197 2198 dc->caps.color.dpp.hw_3d_lut = 1; 2199 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2200 // no OGAM ROM on DCN2 and later ASICs 2201 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2202 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2203 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2204 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2205 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2206 dc->caps.color.dpp.ocsc = 0; 2207 2208 dc->caps.color.mpc.gamut_remap = 1; 2209 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2210 dc->caps.color.mpc.ogam_ram = 1; 2211 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2212 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2213 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2214 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2215 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2216 dc->caps.color.mpc.ocsc = 1; 2217 2218 /* Use pipe context based otg sync logic */ 2219 dc->config.use_pipe_ctx_sync_logic = true; 2220 2221 /* read VBIOS LTTPR caps */ 2222 { 2223 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2224 enum bp_result bp_query_result; 2225 uint8_t is_vbios_lttpr_enable = 0; 2226 2227 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2228 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2229 } 2230 2231 /* interop bit is implicit */ 2232 { 2233 dc->caps.vbios_lttpr_aware = true; 2234 } 2235 } 2236 2237 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2238 dc->debug = debug_defaults_drv; 2239 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2240 dc->debug = debug_defaults_diags; 2241 } else 2242 dc->debug = debug_defaults_diags; 2243 // Init the vm_helper 2244 if (dc->vm_helper) 2245 vm_helper_init(dc->vm_helper, 16); 2246 2247 /************************************************* 2248 * Create resources * 2249 *************************************************/ 2250 2251 /* Clock Sources for Pixel Clock*/ 2252 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2253 dcn32_clock_source_create(ctx, ctx->dc_bios, 2254 CLOCK_SOURCE_COMBO_PHY_PLL0, 2255 &clk_src_regs[0], false); 2256 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2257 dcn32_clock_source_create(ctx, ctx->dc_bios, 2258 CLOCK_SOURCE_COMBO_PHY_PLL1, 2259 &clk_src_regs[1], false); 2260 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2261 dcn32_clock_source_create(ctx, ctx->dc_bios, 2262 CLOCK_SOURCE_COMBO_PHY_PLL2, 2263 &clk_src_regs[2], false); 2264 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2265 dcn32_clock_source_create(ctx, ctx->dc_bios, 2266 CLOCK_SOURCE_COMBO_PHY_PLL3, 2267 &clk_src_regs[3], false); 2268 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2269 dcn32_clock_source_create(ctx, ctx->dc_bios, 2270 CLOCK_SOURCE_COMBO_PHY_PLL4, 2271 &clk_src_regs[4], false); 2272 2273 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2274 2275 /* todo: not reuse phy_pll registers */ 2276 pool->base.dp_clock_source = 2277 dcn32_clock_source_create(ctx, ctx->dc_bios, 2278 CLOCK_SOURCE_ID_DP_DTO, 2279 &clk_src_regs[0], true); 2280 2281 for (i = 0; i < pool->base.clk_src_count; i++) { 2282 if (pool->base.clock_sources[i] == NULL) { 2283 dm_error("DC: failed to create clock sources!\n"); 2284 BREAK_TO_DEBUGGER(); 2285 goto create_fail; 2286 } 2287 } 2288 2289 /* DCCG */ 2290 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2291 if (pool->base.dccg == NULL) { 2292 dm_error("DC: failed to create dccg!\n"); 2293 BREAK_TO_DEBUGGER(); 2294 goto create_fail; 2295 } 2296 2297 /* DML */ 2298 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2299 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2300 2301 /* IRQ Service */ 2302 init_data.ctx = dc->ctx; 2303 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2304 if (!pool->base.irqs) 2305 goto create_fail; 2306 2307 /* HUBBUB */ 2308 pool->base.hubbub = dcn32_hubbub_create(ctx); 2309 if (pool->base.hubbub == NULL) { 2310 BREAK_TO_DEBUGGER(); 2311 dm_error("DC: failed to create hubbub!\n"); 2312 goto create_fail; 2313 } 2314 2315 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2316 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2317 2318 /* if pipe is disabled, skip instance of HW pipe, 2319 * i.e, skip ASIC register instance 2320 */ 2321 if (pipe_fuses & 1 << i) 2322 continue; 2323 2324 /* HUBPs */ 2325 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2326 if (pool->base.hubps[j] == NULL) { 2327 BREAK_TO_DEBUGGER(); 2328 dm_error( 2329 "DC: failed to create hubps!\n"); 2330 goto create_fail; 2331 } 2332 2333 /* DPPs */ 2334 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2335 if (pool->base.dpps[j] == NULL) { 2336 BREAK_TO_DEBUGGER(); 2337 dm_error( 2338 "DC: failed to create dpps!\n"); 2339 goto create_fail; 2340 } 2341 2342 /* OPPs */ 2343 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2344 if (pool->base.opps[j] == NULL) { 2345 BREAK_TO_DEBUGGER(); 2346 dm_error( 2347 "DC: failed to create output pixel processor!\n"); 2348 goto create_fail; 2349 } 2350 2351 /* TGs */ 2352 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2353 ctx, i); 2354 if (pool->base.timing_generators[j] == NULL) { 2355 BREAK_TO_DEBUGGER(); 2356 dm_error("DC: failed to create tg!\n"); 2357 goto create_fail; 2358 } 2359 2360 /* ABMs */ 2361 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2362 &abm_regs[i], 2363 &abm_shift, 2364 &abm_mask); 2365 if (pool->base.multiple_abms[j] == NULL) { 2366 dm_error("DC: failed to create abm for pipe %d!\n", i); 2367 BREAK_TO_DEBUGGER(); 2368 goto create_fail; 2369 } 2370 2371 /* index for resource pool arrays for next valid pipe */ 2372 j++; 2373 } 2374 2375 /* PSR */ 2376 pool->base.psr = dmub_psr_create(ctx); 2377 if (pool->base.psr == NULL) { 2378 dm_error("DC: failed to create psr obj!\n"); 2379 BREAK_TO_DEBUGGER(); 2380 goto create_fail; 2381 } 2382 2383 /* MPCCs */ 2384 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2385 if (pool->base.mpc == NULL) { 2386 BREAK_TO_DEBUGGER(); 2387 dm_error("DC: failed to create mpc!\n"); 2388 goto create_fail; 2389 } 2390 2391 /* DSCs */ 2392 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2393 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2394 if (pool->base.dscs[i] == NULL) { 2395 BREAK_TO_DEBUGGER(); 2396 dm_error("DC: failed to create display stream compressor %d!\n", i); 2397 goto create_fail; 2398 } 2399 } 2400 2401 /* DWB */ 2402 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2403 BREAK_TO_DEBUGGER(); 2404 dm_error("DC: failed to create dwbc!\n"); 2405 goto create_fail; 2406 } 2407 2408 /* MMHUBBUB */ 2409 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2410 BREAK_TO_DEBUGGER(); 2411 dm_error("DC: failed to create mcif_wb!\n"); 2412 goto create_fail; 2413 } 2414 2415 /* AUX and I2C */ 2416 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2417 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2418 if (pool->base.engines[i] == NULL) { 2419 BREAK_TO_DEBUGGER(); 2420 dm_error( 2421 "DC:failed to create aux engine!!\n"); 2422 goto create_fail; 2423 } 2424 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2425 if (pool->base.hw_i2cs[i] == NULL) { 2426 BREAK_TO_DEBUGGER(); 2427 dm_error( 2428 "DC:failed to create hw i2c!!\n"); 2429 goto create_fail; 2430 } 2431 pool->base.sw_i2cs[i] = NULL; 2432 } 2433 2434 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2435 if (!resource_construct(num_virtual_links, dc, &pool->base, 2436 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2437 &res_create_funcs : &res_create_maximus_funcs))) 2438 goto create_fail; 2439 2440 /* HW Sequencer init functions and Plane caps */ 2441 dcn32_hw_sequencer_init_functions(dc); 2442 2443 dc->caps.max_planes = pool->base.pipe_count; 2444 2445 for (i = 0; i < dc->caps.max_planes; ++i) 2446 dc->caps.planes[i] = plane_cap; 2447 2448 dc->cap_funcs = cap_funcs; 2449 2450 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2451 ddc_init_data.ctx = dc->ctx; 2452 ddc_init_data.link = NULL; 2453 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2454 ddc_init_data.id.enum_id = 0; 2455 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2456 pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2457 } else { 2458 pool->base.oem_device = NULL; 2459 } 2460 2461 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2462 dc->config.sdpif_request_limit_words_per_umc = 16; 2463 2464 DC_FP_END(); 2465 2466 return true; 2467 2468 create_fail: 2469 2470 DC_FP_END(); 2471 2472 dcn32_resource_destruct(pool); 2473 2474 return false; 2475 } 2476 2477 struct resource_pool *dcn32_create_resource_pool( 2478 const struct dc_init_data *init_data, 2479 struct dc *dc) 2480 { 2481 struct dcn32_resource_pool *pool = 2482 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2483 2484 if (!pool) 2485 return NULL; 2486 2487 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2488 return &pool->base; 2489 2490 BREAK_TO_DEBUGGER(); 2491 kfree(pool); 2492 return NULL; 2493 } 2494 2495 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2496 struct resource_context *res_ctx, 2497 const struct resource_pool *pool, 2498 const struct pipe_ctx *primary_pipe) 2499 { 2500 int i; 2501 struct pipe_ctx *secondary_pipe = NULL; 2502 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2503 int primary_index, preferred_pipe_idx; 2504 struct pipe_ctx *old_primary_pipe = NULL; 2505 2506 /* 2507 * Modified from find_idle_secondary_pipe 2508 * With windowed MPO and ODM, we want to avoid the case where we want a 2509 * free pipe for the left side but the free pipe is being used on the 2510 * right side. 2511 * Add check on current_state if the primary_pipe is the left side, 2512 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2513 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2514 * - If so, then don't use this pipe 2515 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2516 * - in this case, the primary pipe has already gotten a free pipe for the 2517 * MPO window in the left 2518 * - when it tries to get a free pipe for the MPO window on the right, 2519 * it will see that it is already assigned to the right side 2520 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2521 * free pipe, since it will be for the right side. So add an 2522 * additional condition, that skipping the free pipe on the right only 2523 * applies if the primary pipe has no bottom pipe currently assigned 2524 */ 2525 if (primary_pipe) { 2526 primary_index = primary_pipe->pipe_idx; 2527 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2528 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2529 && (!primary_pipe->bottom_pipe)) 2530 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2531 2532 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2533 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2534 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2535 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2536 secondary_pipe->pipe_idx = preferred_pipe_idx; 2537 } 2538 } 2539 2540 /* 2541 * search backwards for the second pipe to keep pipe 2542 * assignment more consistent 2543 */ 2544 if (!secondary_pipe) 2545 for (i = pool->pipe_count - 1; i >= 0; i--) { 2546 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2547 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2548 secondary_pipe = &res_ctx->pipe_ctx[i]; 2549 secondary_pipe->pipe_idx = i; 2550 break; 2551 } 2552 } 2553 2554 return secondary_pipe; 2555 } 2556 2557 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2558 struct dc_state *state, 2559 const struct resource_pool *pool, 2560 struct dc_stream_state *stream, 2561 struct pipe_ctx *head_pipe) 2562 { 2563 struct resource_context *res_ctx = &state->res_ctx; 2564 struct pipe_ctx *idle_pipe, *pipe; 2565 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2566 int head_index; 2567 2568 if (!head_pipe) 2569 ASSERT(0); 2570 2571 /* 2572 * Modified from dcn20_acquire_idle_pipe_for_layer 2573 * Check if head_pipe in old_context already has bottom_pipe allocated. 2574 * - If so, check if that pipe is available in the current context. 2575 * -- If so, reuse pipe from old_context 2576 */ 2577 head_index = head_pipe->pipe_idx; 2578 pipe = &old_ctx->pipe_ctx[head_index]; 2579 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2580 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2581 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2582 } else { 2583 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2584 if (!idle_pipe) 2585 return NULL; 2586 } 2587 2588 idle_pipe->stream = head_pipe->stream; 2589 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2590 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2591 2592 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2593 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2594 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2595 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2596 2597 return idle_pipe; 2598 } 2599 2600 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2601 { 2602 /* 2603 * DCN32 and DCN321 SKUs may have different sizes for MALL 2604 * but we may not be able to access all the MALL space. 2605 * If the num_chans is power of 2, then we can access all 2606 * of the available MALL space. Otherwise, we can only 2607 * access: 2608 * 2609 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2610 * ((2^floor(log2(num_chans)))/num_chans) 2611 * 2612 * Calculating the MALL sizes for all available SKUs, we 2613 * have come up with the follow simplified check. 2614 * - we have max_chans which provides the max MALL size. 2615 * Each chans supports 4MB of MALL so: 2616 * 2617 * total_cache_size_in_bytes = max_chans * 4 MB 2618 * 2619 * - we have avail_chans which shows the number of channels 2620 * we can use if we can't access the entire MALL space. 2621 * It is generally half of max_chans 2622 * - so we use the following checks: 2623 * 2624 * if (num_chans == max_chans), return max_chans 2625 * if (num_chans < max_chans), return avail_chans 2626 * 2627 * - exception is GC_11_0_0 where we can't access max_chans, 2628 * so we define max_avail_chans as the maximum available 2629 * MALL space 2630 * 2631 */ 2632 int gc_11_0_0_max_chans = 48; 2633 int gc_11_0_0_max_avail_chans = 32; 2634 int gc_11_0_0_avail_chans = 16; 2635 int gc_11_0_3_max_chans = 16; 2636 int gc_11_0_3_avail_chans = 8; 2637 int gc_11_0_2_max_chans = 8; 2638 int gc_11_0_2_avail_chans = 4; 2639 2640 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2641 return (num_chans == gc_11_0_0_max_chans) ? 2642 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2643 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2644 return (num_chans == gc_11_0_2_max_chans) ? 2645 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2646 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2647 return (num_chans == gc_11_0_3_max_chans) ? 2648 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2649 } 2650 } 2651