1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn32_optc.h" 27 28 #include "dcn30/dcn30_optc.h" 29 #include "dcn31/dcn31_optc.h" 30 #include "reg_helper.h" 31 #include "dc.h" 32 #include "dcn_calc_math.h" 33 #include "dc_dmub_srv.h" 34 35 #define REG(reg)\ 36 optc1->tg_regs->reg 37 38 #define CTX \ 39 optc1->base.ctx 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 44 45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 46 struct dc_crtc_timing *timing) 47 { 48 struct optc *optc1 = DCN10TG_FROM_TG(optc); 49 uint32_t memory_mask = 0; 50 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 51 int mpcc_hactive = h_active / opp_cnt; 52 /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */ 53 int odm_mem_count = (h_active + 2047) / 2048; 54 55 /* 56 * display <= 4k : 2 memories + 2 pipes 57 * 4k < display <= 8k : 4 memories + 2 pipes 58 * 8k < display <= 12k : 6 memories + 4 pipes 59 */ 60 if (opp_cnt == 4) { 61 if (odm_mem_count <= 2) 62 memory_mask = 0x3; 63 else if (odm_mem_count <= 4) 64 memory_mask = 0xf; 65 else 66 memory_mask = 0x3f; 67 } else { 68 if (odm_mem_count <= 2) 69 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 70 else if (odm_mem_count <= 4) 71 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 72 else 73 memory_mask = 0x77; 74 } 75 76 REG_SET(OPTC_MEMORY_CONFIG, 0, 77 OPTC_MEM_SEL, memory_mask); 78 79 if (opp_cnt == 2) { 80 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 81 OPTC_NUM_OF_INPUT_SEGMENT, 1, 82 OPTC_SEG0_SRC_SEL, opp_id[0], 83 OPTC_SEG1_SRC_SEL, opp_id[1]); 84 } else if (opp_cnt == 4) { 85 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 86 OPTC_NUM_OF_INPUT_SEGMENT, 3, 87 OPTC_SEG0_SRC_SEL, opp_id[0], 88 OPTC_SEG1_SRC_SEL, opp_id[1], 89 OPTC_SEG2_SRC_SEL, opp_id[2], 90 OPTC_SEG3_SRC_SEL, opp_id[3]); 91 } 92 93 REG_UPDATE(OPTC_WIDTH_CONTROL, 94 OPTC_SEGMENT_WIDTH, mpcc_hactive); 95 96 REG_UPDATE(OTG_H_TIMING_CNTL, 97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 98 optc1->opp_count = opp_cnt; 99 } 100 101 void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) 102 { 103 struct optc *optc1 = DCN10TG_FROM_TG(optc); 104 105 REG_UPDATE(OTG_H_TIMING_CNTL, 106 OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0); 107 } 108 /** 109 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator. 110 * 111 * @optc: timing_generator instance. 112 * 113 * Return: If CRTC is enabled, return true. 114 */ 115 static bool optc32_enable_crtc(struct timing_generator *optc) 116 { 117 struct optc *optc1 = DCN10TG_FROM_TG(optc); 118 119 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 120 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 121 OPTC_SEG0_SRC_SEL, optc->inst); 122 123 /* VTG enable first is for HW workaround */ 124 REG_UPDATE(CONTROL, 125 VTG0_ENABLE, 1); 126 127 REG_SEQ_START(); 128 129 /* Enable CRTC */ 130 REG_UPDATE_2(OTG_CONTROL, 131 OTG_DISABLE_POINT_CNTL, 2, 132 OTG_MASTER_EN, 1); 133 134 REG_SEQ_SUBMIT(); 135 REG_SEQ_WAIT_DONE(); 136 137 return true; 138 } 139 140 /* disable_crtc */ 141 static bool optc32_disable_crtc(struct timing_generator *optc) 142 { 143 struct optc *optc1 = DCN10TG_FROM_TG(optc); 144 145 /* disable otg request until end of the first line 146 * in the vertical blank region 147 */ 148 REG_UPDATE(OTG_CONTROL, 149 OTG_MASTER_EN, 0); 150 151 REG_UPDATE(CONTROL, 152 VTG0_ENABLE, 0); 153 154 /* CRTC disabled, so disable clock. */ 155 REG_WAIT(OTG_CLOCK_CONTROL, 156 OTG_BUSY, 0, 157 1, 150000); 158 159 return true; 160 } 161 162 static void optc32_phantom_crtc_post_enable(struct timing_generator *optc) 163 { 164 struct optc *optc1 = DCN10TG_FROM_TG(optc); 165 166 /* Disable immediately. */ 167 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); 168 169 /* CRTC disabled, so disable clock. */ 170 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); 171 } 172 173 static void optc32_disable_phantom_otg(struct timing_generator *optc) 174 { 175 struct optc *optc1 = DCN10TG_FROM_TG(optc); 176 177 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); 178 } 179 180 static void optc32_set_odm_bypass(struct timing_generator *optc, 181 const struct dc_crtc_timing *dc_crtc_timing) 182 { 183 struct optc *optc1 = DCN10TG_FROM_TG(optc); 184 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 185 186 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 187 OPTC_NUM_OF_INPUT_SEGMENT, 0, 188 OPTC_SEG0_SRC_SEL, optc->inst, 189 OPTC_SEG1_SRC_SEL, 0xf, 190 OPTC_SEG2_SRC_SEL, 0xf, 191 OPTC_SEG3_SRC_SEL, 0xf 192 ); 193 194 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); 195 REG_UPDATE(OTG_H_TIMING_CNTL, 196 OTG_H_TIMING_DIV_MODE, h_div); 197 198 REG_SET(OPTC_MEMORY_CONFIG, 0, 199 OPTC_MEM_SEL, 0); 200 optc1->opp_count = 1; 201 } 202 203 static void optc32_setup_manual_trigger(struct timing_generator *optc) 204 { 205 struct optc *optc1 = DCN10TG_FROM_TG(optc); 206 struct dc *dc = optc->ctx->dc; 207 208 if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams) 209 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst); 210 else { 211 /* 212 * MIN_MASK_EN is gone and MASK is now always enabled. 213 * 214 * To get it to it work with manual trigger we need to make sure 215 * we program the correct bit. 216 */ 217 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 218 OTG_V_TOTAL_MIN_SEL, 1, 219 OTG_V_TOTAL_MAX_SEL, 1, 220 OTG_FORCE_LOCK_ON_EVENT, 0, 221 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 222 223 // Setup manual flow control for EOF via TRIG_A 224 optc->funcs->setup_manual_trigger(optc); 225 } 226 } 227 228 static void optc32_set_drr( 229 struct timing_generator *optc, 230 const struct drr_params *params) 231 { 232 struct optc *optc1 = DCN10TG_FROM_TG(optc); 233 234 if (params != NULL && 235 params->vertical_total_max > 0 && 236 params->vertical_total_min > 0) { 237 238 if (params->vertical_total_mid != 0) { 239 240 REG_SET(OTG_V_TOTAL_MID, 0, 241 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 242 243 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 244 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 245 OTG_VTOTAL_MID_FRAME_NUM, 246 (uint8_t)params->vertical_total_mid_frame_num); 247 248 } 249 250 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 251 } 252 253 optc32_setup_manual_trigger(optc); 254 } 255 256 static struct timing_generator_funcs dcn32_tg_funcs = { 257 .validate_timing = optc1_validate_timing, 258 .program_timing = optc1_program_timing, 259 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 260 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 261 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 262 .program_global_sync = optc1_program_global_sync, 263 .enable_crtc = optc32_enable_crtc, 264 .disable_crtc = optc32_disable_crtc, 265 .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, 266 .disable_phantom_crtc = optc32_disable_phantom_otg, 267 /* used by enable_timing_synchronization. Not need for FPGA */ 268 .is_counter_moving = optc1_is_counter_moving, 269 .get_position = optc1_get_position, 270 .get_frame_count = optc1_get_vblank_counter, 271 .get_scanoutpos = optc1_get_crtc_scanoutpos, 272 .get_otg_active_size = optc1_get_otg_active_size, 273 .set_early_control = optc1_set_early_control, 274 /* used by enable_timing_synchronization. Not need for FPGA */ 275 .wait_for_state = optc1_wait_for_state, 276 .set_blank_color = optc3_program_blank_color, 277 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 278 .triplebuffer_lock = optc3_triplebuffer_lock, 279 .triplebuffer_unlock = optc2_triplebuffer_unlock, 280 .enable_reset_trigger = optc1_enable_reset_trigger, 281 .enable_crtc_reset = optc1_enable_crtc_reset, 282 .disable_reset_trigger = optc1_disable_reset_trigger, 283 .lock = optc3_lock, 284 .unlock = optc1_unlock, 285 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 286 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 287 .enable_optc_clock = optc1_enable_optc_clock, 288 .set_drr = optc32_set_drr, 289 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 290 .set_vtotal_min_max = optc3_set_vtotal_min_max, 291 .set_static_screen_control = optc1_set_static_screen_control, 292 .program_stereo = optc1_program_stereo, 293 .is_stereo_left_eye = optc1_is_stereo_left_eye, 294 .tg_init = optc3_tg_init, 295 .is_tg_enabled = optc1_is_tg_enabled, 296 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 297 .clear_optc_underflow = optc1_clear_optc_underflow, 298 .setup_global_swap_lock = NULL, 299 .get_crc = optc1_get_crc, 300 .configure_crc = optc1_configure_crc, 301 .set_dsc_config = optc3_set_dsc_config, 302 .get_dsc_status = optc2_get_dsc_status, 303 .set_dwb_source = NULL, 304 .set_odm_bypass = optc32_set_odm_bypass, 305 .set_odm_combine = optc32_set_odm_combine, 306 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, 307 .get_optc_source = optc2_get_optc_source, 308 .set_out_mux = optc3_set_out_mux, 309 .set_drr_trigger_window = optc3_set_drr_trigger_window, 310 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 311 .set_gsl = optc2_set_gsl, 312 .set_gsl_source_select = optc2_set_gsl_source_select, 313 .set_vtg_params = optc1_set_vtg_params, 314 .program_manual_trigger = optc2_program_manual_trigger, 315 .setup_manual_trigger = optc2_setup_manual_trigger, 316 .get_hw_timing = optc1_get_hw_timing, 317 }; 318 319 void dcn32_timing_generator_init(struct optc *optc1) 320 { 321 optc1->base.funcs = &dcn32_tg_funcs; 322 323 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 324 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 325 326 optc1->min_h_blank = 32; 327 optc1->min_v_blank = 3; 328 optc1->min_v_blank_interlace = 5; 329 optc1->min_h_sync_width = 4; 330 optc1->min_v_sync_width = 1; 331 } 332 333