1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn32_optc.h" 27 28 #include "dcn30/dcn30_optc.h" 29 #include "reg_helper.h" 30 #include "dc.h" 31 #include "dcn_calc_math.h" 32 33 #define REG(reg)\ 34 optc1->tg_regs->reg 35 36 #define CTX \ 37 optc1->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name 42 43 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 44 struct dc_crtc_timing *timing) 45 { 46 struct optc *optc1 = DCN10TG_FROM_TG(optc); 47 uint32_t memory_mask = 0; 48 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 49 int mpcc_hactive = h_active / opp_cnt; 50 /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */ 51 int odm_mem_count = (h_active + 2047) / 2048; 52 53 /* 54 * display <= 4k : 2 memories + 2 pipes 55 * 4k < display <= 8k : 4 memories + 2 pipes 56 * 8k < display <= 12k : 6 memories + 4 pipes 57 */ 58 if (opp_cnt == 4) { 59 if (odm_mem_count <= 2) 60 memory_mask = 0x3; 61 else if (odm_mem_count <= 4) 62 memory_mask = 0xf; 63 else 64 memory_mask = 0x3f; 65 } else { 66 if (odm_mem_count <= 2) 67 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 68 else if (odm_mem_count <= 4) 69 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 70 else 71 memory_mask = 0x77; 72 } 73 74 REG_SET(OPTC_MEMORY_CONFIG, 0, 75 OPTC_MEM_SEL, memory_mask); 76 77 if (opp_cnt == 2) { 78 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 79 OPTC_NUM_OF_INPUT_SEGMENT, 1, 80 OPTC_SEG0_SRC_SEL, opp_id[0], 81 OPTC_SEG1_SRC_SEL, opp_id[1]); 82 } else if (opp_cnt == 4) { 83 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 84 OPTC_NUM_OF_INPUT_SEGMENT, 3, 85 OPTC_SEG0_SRC_SEL, opp_id[0], 86 OPTC_SEG1_SRC_SEL, opp_id[1], 87 OPTC_SEG2_SRC_SEL, opp_id[2], 88 OPTC_SEG3_SRC_SEL, opp_id[3]); 89 } 90 91 REG_UPDATE(OPTC_WIDTH_CONTROL, 92 OPTC_SEGMENT_WIDTH, mpcc_hactive); 93 94 REG_UPDATE(OTG_H_TIMING_CNTL, 95 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 96 optc1->opp_count = opp_cnt; 97 } 98 99 static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) 100 { 101 struct optc *optc1 = DCN10TG_FROM_TG(optc); 102 103 REG_UPDATE(OTG_H_TIMING_CNTL, 104 OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0); 105 } 106 /** 107 * Enable CRTC 108 * Enable CRTC - call ASIC Control Object to enable Timing generator. 109 */ 110 static bool optc32_enable_crtc(struct timing_generator *optc) 111 { 112 struct optc *optc1 = DCN10TG_FROM_TG(optc); 113 114 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 115 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 116 OPTC_SEG0_SRC_SEL, optc->inst); 117 118 /* VTG enable first is for HW workaround */ 119 REG_UPDATE(CONTROL, 120 VTG0_ENABLE, 1); 121 122 REG_SEQ_START(); 123 124 /* Enable CRTC */ 125 REG_UPDATE_2(OTG_CONTROL, 126 OTG_DISABLE_POINT_CNTL, 2, 127 OTG_MASTER_EN, 1); 128 129 REG_SEQ_SUBMIT(); 130 REG_SEQ_WAIT_DONE(); 131 132 return true; 133 } 134 135 /* disable_crtc */ 136 static bool optc32_disable_crtc(struct timing_generator *optc) 137 { 138 struct optc *optc1 = DCN10TG_FROM_TG(optc); 139 140 /* disable otg request until end of the first line 141 * in the vertical blank region 142 */ 143 REG_UPDATE(OTG_CONTROL, 144 OTG_MASTER_EN, 0); 145 146 REG_UPDATE(CONTROL, 147 VTG0_ENABLE, 0); 148 149 /* CRTC disabled, so disable clock. */ 150 REG_WAIT(OTG_CLOCK_CONTROL, 151 OTG_BUSY, 0, 152 1, 100000); 153 154 return true; 155 } 156 157 void optc32_phantom_crtc_post_enable(struct timing_generator *optc) 158 { 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 /* Disable immediately. */ 162 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); 163 164 /* CRTC disabled, so disable clock. */ 165 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); 166 } 167 168 static void optc32_set_odm_bypass(struct timing_generator *optc, 169 const struct dc_crtc_timing *dc_crtc_timing) 170 { 171 struct optc *optc1 = DCN10TG_FROM_TG(optc); 172 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 173 174 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 175 OPTC_NUM_OF_INPUT_SEGMENT, 0, 176 OPTC_SEG0_SRC_SEL, optc->inst, 177 OPTC_SEG1_SRC_SEL, 0xf, 178 OPTC_SEG2_SRC_SEL, 0xf, 179 OPTC_SEG3_SRC_SEL, 0xf 180 ); 181 182 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); 183 REG_UPDATE(OTG_H_TIMING_CNTL, 184 OTG_H_TIMING_DIV_MODE, h_div); 185 186 REG_SET(OPTC_MEMORY_CONFIG, 0, 187 OPTC_MEM_SEL, 0); 188 optc1->opp_count = 1; 189 } 190 191 192 static struct timing_generator_funcs dcn32_tg_funcs = { 193 .validate_timing = optc1_validate_timing, 194 .program_timing = optc1_program_timing, 195 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 196 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 197 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 198 .program_global_sync = optc1_program_global_sync, 199 .enable_crtc = optc32_enable_crtc, 200 .disable_crtc = optc32_disable_crtc, 201 .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, 202 /* used by enable_timing_synchronization. Not need for FPGA */ 203 .is_counter_moving = optc1_is_counter_moving, 204 .get_position = optc1_get_position, 205 .get_frame_count = optc1_get_vblank_counter, 206 .get_scanoutpos = optc1_get_crtc_scanoutpos, 207 .get_otg_active_size = optc1_get_otg_active_size, 208 .set_early_control = optc1_set_early_control, 209 /* used by enable_timing_synchronization. Not need for FPGA */ 210 .wait_for_state = optc1_wait_for_state, 211 .set_blank_color = optc3_program_blank_color, 212 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 213 .triplebuffer_lock = optc3_triplebuffer_lock, 214 .triplebuffer_unlock = optc2_triplebuffer_unlock, 215 .enable_reset_trigger = optc1_enable_reset_trigger, 216 .enable_crtc_reset = optc1_enable_crtc_reset, 217 .disable_reset_trigger = optc1_disable_reset_trigger, 218 .lock = optc3_lock, 219 .unlock = optc1_unlock, 220 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 221 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 222 .enable_optc_clock = optc1_enable_optc_clock, 223 .set_vrr_m_const = optc3_set_vrr_m_const, 224 .set_drr = optc1_set_drr, 225 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 226 .set_vtotal_min_max = optc1_set_vtotal_min_max, 227 .set_static_screen_control = optc1_set_static_screen_control, 228 .program_stereo = optc1_program_stereo, 229 .is_stereo_left_eye = optc1_is_stereo_left_eye, 230 .tg_init = optc3_tg_init, 231 .is_tg_enabled = optc1_is_tg_enabled, 232 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 233 .clear_optc_underflow = optc1_clear_optc_underflow, 234 .setup_global_swap_lock = NULL, 235 .get_crc = optc1_get_crc, 236 .configure_crc = optc1_configure_crc, 237 .set_dsc_config = optc3_set_dsc_config, 238 .get_dsc_status = optc2_get_dsc_status, 239 .set_dwb_source = NULL, 240 .set_odm_bypass = optc32_set_odm_bypass, 241 .set_odm_combine = optc32_set_odm_combine, 242 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, 243 .get_optc_source = optc2_get_optc_source, 244 .set_out_mux = optc3_set_out_mux, 245 .set_drr_trigger_window = optc3_set_drr_trigger_window, 246 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 247 .set_gsl = optc2_set_gsl, 248 .set_gsl_source_select = optc2_set_gsl_source_select, 249 .set_vtg_params = optc1_set_vtg_params, 250 .program_manual_trigger = optc2_program_manual_trigger, 251 .setup_manual_trigger = optc2_setup_manual_trigger, 252 .get_hw_timing = optc1_get_hw_timing, 253 }; 254 255 void dcn32_timing_generator_init(struct optc *optc1) 256 { 257 optc1->base.funcs = &dcn32_tg_funcs; 258 259 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 260 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 261 262 optc1->min_h_blank = 32; 263 optc1->min_v_blank = 3; 264 optc1->min_v_blank_interlace = 5; 265 optc1->min_h_sync_width = 4; 266 optc1->min_v_sync_width = 1; 267 } 268 269